TW201306489A - Clamping circuit and common voltage generating circuit - Google Patents

Abstract

A clamping circuit, comprising: a control circuit, for generating a control signal; at least one adjustable current source, for receiving the control signal, to provide at least one charging current to charge at least one capacitor or let the capacitor discharge, to generate a clamping voltage; and a comparator, for generating a comparing result according to the clamping voltage and a reference voltage, wherein the control circuit generates the comparing result to generate the control signal.

Description

Clamp circuit and common mode voltage generating circuit

The present invention relates to a clamp circuit and a common mode voltage generating circuit, and more particularly to a clamp circuit using a variable current source and a common mode voltage generating circuit.

Traditionally, a clamp circuit is used to provide the common mode voltage of an analog digital converter. FIG. 1 is a schematic diagram showing the use of a clamp circuit to provide a common mode voltage in the prior art. The circuit shown in FIG. 1 is a television signal processing circuit including a digital signal processing circuit 101, an analog digital converter 103, a clamp circuit 105, and two capacitors 107, 109. The analog digital converter 103 has two inputs 104, 106 for receiving the television signals V _in and V _ip , respectively, to form a differential signal. The analog digital converter 103 is configured to receive the analog television signal and convert it into a digital television signal for processing by the digital signal processing circuit 101. As to when and how much common mode voltage is to be supplied to the analog digital converter 103 for processing television signals, as will be appreciated by those skilled in the art, no further details are provided herein.

Clamp circuit 105 is used to charge capacitors 107 and 109 on the input path of analog-to-digital converter 103 to provide common mode voltage V _cm to analog digital converter 103. However, conventional clamp circuits typically provide a fixed charging current. Taking the clamp circuit 105 in Fig. 1 as an example, it is composed of a plurality of resistors 111, 113 and 115 and switching elements 117, 119. Therefore, if the switching elements 117, 119 are turned on, the resistors 111, 113, and 115 form a voltage dividing circuit to generate _Vmid , and accordingly, current is output to the capacitors 107, 109 for charging. However, such a current structure is liable to cause a waste of charging current. For example, when the capacitor is already charged to the maximum voltage, the current flowing to the A path becomes smaller, and the current flowing to the B path becomes larger. As a result, most of the current is wasted, resulting in unnecessary power consumption.

It is therefore an object of the present invention to provide a clamp circuit that dynamically adjusts the charge and discharge current.

Another object of the present invention is to provide a common mode voltage generating circuit that can dynamically adjust a charge and discharge current.

An embodiment of the present invention discloses a clamping circuit including: a control circuit for generating a control signal; and at least one adjustable current source for receiving the control signal to provide at least one charging current for at least one Capacitor charging or discharging the capacitor to generate a clamping voltage; and a comparator, generating a comparison result according to the clamping voltage and a reference voltage, and the control circuit generates the control signal according to the comparison result .

Another embodiment of the present invention discloses a common mode voltage generating circuit for generating a common mode voltage of an analog converter, comprising: a control circuit for generating a control signal; and at least one adjustable current source for Receiving the control signal to provide at least one charging current to charge and discharge at least one capacitor on the signal input path of the analog-to-digital converter to generate the common mode voltage; and a comparator according to the common mode voltage and a The reference voltage is used to generate a comparison result, and the control circuit generates the control signal based on the comparison result.

According to the foregoing embodiment, the charging and discharging current is dynamically adjusted in accordance with the visual charging condition, and thus unnecessary power consumption can be reduced.

Certain terms are used throughout the description and following claims to refer to particular elements. Those of ordinary skill in the art should understand that a hardware manufacturer may refer to the same component by a different noun. The scope of this specification and the subsequent patent application do not use the difference of the names as the means for distinguishing the elements, but the difference in function of the elements as the criterion for distinguishing. The term "including" as used throughout the specification and subsequent claims is an open term and should be interpreted as "including but not limited to". In addition, the term "coupled" is used herein to include any direct and indirect electrical connection. Therefore, if a first device is coupled to a second device, it means that the first device can be directly electrically connected to the second device or indirectly electrically connected to the second device through other devices or connection means.

FIG. 2 is a circuit diagram of a clamp circuit 200 in accordance with an embodiment of the present invention. Clamp circuit 200 uses a single adjustable current source to charge and discharge different capacitors to generate a clamping voltage. As shown in FIG. 2, the clamp circuit 200 includes a control circuit 201, an adjustable current source 203, and a comparator 205. The control circuit 201 is configured to generate a control signal CS. Clamp circuit 200 can also be considered as a common mode voltage generating circuit for generating a common mode voltage to an analog to digital converter. However, the clamp circuit 200 can also be applied to other electronic devices to provide a clamp voltage to a target electronic device. The adjustable current source 203 is configured to receive the control signal CS to provide a charging current I _C1 , I _C2 to charge the capacitors 209 , 211 or to provide a discharge path of the capacitors 209 , 211 to generate a clamping voltage V _clamp . The comparator 205 (in this example, a hysteresis comparator) generates a comparison result based on the clamp voltage V _clamp and a reference voltage V _ref , and the control circuit 201 generates the control signal CS based on the comparison result. Please note that in this embodiment, the signals V _ip and V _in received by the inputs 212 and 214 can be single-ended input signals, that is, only one of V _ip and V _in has a small signal portion. Alternatively, both V _ip and V _in can have small signal portions. In this embodiment, the tunable current source 203 has an N-type MOS transistor 215 and a P-type MOS transistor 217. The gates of these MOS transistors receive the control signal CS, respectively, so that different currents can be generated according to different control signals CS. Please note that the adjustable current source 203 can also be replaced by other circuits, and is not limited to being composed of a P-type MOS transistor and an N-type MOS transistor.

The clamping circuit 200 can further have a switching element 208 for making a voltage equal to the clamping voltage V _clamp of the two signal receiving paths on the analog converter 213. The detailed operation mode is that the clamp circuit 200 can operate in a normal mode and a clamp mode. In the normal mode, the switching element 208 is not turned on, and the clamp circuit 200 does not operate (ie, the MOS transistor in the modulating current source 203 is turned off), and the analog digital converter 213 is formed according to the capacitors 209 and 211. The clamp voltage V _{clamp operates} . In the clamp mode, the switching element 208 is turned on before the clamping circuit 200 charges or discharges the capacitors 209 and 211 according to the foregoing actions, so that the clamping voltage of the two signal receiving paths on the analog-to-digital converter 213 can be made. The V _clamp becomes the same level, and then the clamp circuit 200 charges or discharges the capacitors 209 and 211 in accordance with the aforementioned actions. In one embodiment, the signals V _ip and V _in are controlled _in the clamp mode to have no small signal portions so as not to interfere with the determination of the clamp voltage.

FIG. 3 is a schematic diagram showing the operation of the clamp circuit according to an embodiment of the present invention. The control circuit 201 is implemented as a D-type flip-flop. And an adjustable current source 203 in the power MOS crystal system is controlled by a combination of the comparator outputs S ₀ and 205. The output control circuit 201 is S _1. For example, a logic circuit 202 can receive an output signal Out after receiving S ₀ , S ₁ , but does not limit the logic circuit using hardware to control the MOS transistor in the adjustable current source 203 according to S ₀ , S _{1 .} It can also be controlled by other means. As shown in FIG. 3, when the value of the signal S ₀ outputted from the comparator 205 is 0, and the signal S ₁ output from the control circuit 201 is 0, the P-type MOS transistor 215 of the adjustable current source 203 To be turned on, the N-type MOS transistor 217 is non-conductive. At this time, the adjustable current source 203 charges the capacitors 209 and 211. When the value of the signal S ₀ is 1, and the signal S ₁ is 1, the P-type MOS transistor 215 of the adjustable current source 203 is non-conductive, and the N-type MOS transistor 217 is turned on. At this time, the capacitors 209, and 211 are discharged. The above charging or discharging action is the aforementioned clamping mode. When the combination of the signal S ₀ and the signal S ₁ is (0, 1) or (1, 0), it is the normal mode, the P-type MOS transistor 215 and the N-type MOS semiconductor of the adjustable current source 203. The transistors 217 are all non-conductive.

FIG. 4 is a circuit diagram of a clamp circuit 400 in accordance with another embodiment of the present invention. Compared with the clamp circuit 200, the clamp circuit 400 also has a control circuit 401, adjustable current sources 403, 407 and a comparator 405. The adjustable current sources 403, 407 are also controlled by the control circuit 401 for the analog digital converter 413. Capacitors 409 and 411 on the two signal receiving paths are charged and discharged. The difference between the clamp circuit 200 and the clamp circuit 400 is that the clamp circuit 200 charges and discharges the different capacitors 209 and 211 by the same adjustable current source 203, and the clamp circuit 400 uses different adjustable current sources 403, 407 to charge and discharge the different capacitors 409, 411, respectively, so the circuit structure of the clamp circuit 200 and the clamp circuit 400 are slightly different. Clamp circuit 400 does not include switching element 208 of clamp circuit 200 and has two comparators 405, 406. The adjustable current sources 403, 407 charge and discharge the capacitors 409, 411, respectively, and the comparators 405, 406 compare the clamp voltages formed by the capacitors 409 and 411, respectively, and transmit the comparison results to the control circuit 401.

The action of the clamp circuit 400 can be as follows: When the clamp circuit 400 operates in a clamp mode, the comparators 405 and 406 compare the clamp voltage and the reference voltage V _{ref , respectively,} to generate the control signal CS. When the clamp circuit 400 is operated in a normal mode, the adjustable current sources 403, 407 are inactive (ie, the P-type MOS transistors 415, 419 and the N-type MOS transistors 417, 421 are turned off). The analog digital converter 413 operates normally according to the clamp voltage generated by the capacitors 409 and 411. Other operations or circuit details of the clamp circuit 400 are the same as those of the clamp circuit 200, and therefore will not be described herein.

According to the foregoing embodiment, the charging and discharging current is dynamically adjusted in accordance with the visual charging condition, and thus unnecessary power consumption can be reduced.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

200, 400. . . Clamp circuit

201, 401. . . Control circuit

202. . . Logic circuit

203, 403, 407. . . Adjustable current source

205, 405, 406. . . Comparators

208. . . Switching element

209, 211, 409, 411. . . capacitance

212, 214, 412, 414. . . Input

213, 413. . . Analog digital converter

215, 415, 419. . . N-type MOS transistor

217, 417, 421. . . P-type MOS transistor

FIG. 1 is a schematic diagram showing the use of a clamp circuit to provide a common mode voltage in the prior art.

FIG. 2 is a circuit diagram of a clamp circuit in accordance with an embodiment of the present invention.

FIG. 3 is a schematic diagram showing the operation of the clamp circuit according to an embodiment of the present invention.

FIG. 4 is a circuit diagram of a clamp circuit in accordance with another embodiment of the present invention.

200. . . Clamp circuit

201. . . Control circuit

203. . . Adjustable current source

205. . . Comparators

208. . . Switching element

209, 211. . . capacitance

212, 214. . . Input

213. . . Analog digital converter

215. . . N-type MOS transistor

217. . . P-type MOS transistor

Claims (10)

A clamping circuit includes: a control circuit for generating a control signal; and at least one adjustable current source for receiving the control signal to provide at least one charging current to charge or enable the at least one capacitor Discharging to generate a clamping voltage; and a comparator for generating a comparison result based on the clamping voltage and a reference voltage, and the control circuit generates the control signal according to the comparison result. The clamp circuit of claim 1, wherein the number of the capacitors is at least two, and the clamp circuit uses the same adjustable power source to charge and discharge the plurality of capacitors to generate the clamp voltage. . The clamp circuit according to claim 1 is characterized in that different adjustable current sources are used to respectively charge and discharge different capacitors to generate the clamp voltage. The clamping circuit of claim 1, further comprising a switching component, wherein the number of the capacitors is at least two, the switching component is coupled to the capacitors for generating the capacitors when conducting The voltages are equal. The clamping circuit of claim 4, wherein the clamping circuit generates the clamping voltage in a clamping mode, and turns on the switching component to generate the capacitors before generating the clamping voltage. The voltages are equal. A common mode voltage generating circuit for generating a common mode voltage of an analog converter includes: a control circuit for generating a control signal; and at least one adjustable current source for receiving the control signal to provide at least a charging current to charge and discharge at least one capacitor on the signal input path of the analog to digital converter to generate the common mode voltage; and a comparator to generate a comparison result according to the common mode voltage and a reference voltage, and The control circuit generates the control signal based on the comparison result. The common mode voltage generating circuit of claim 6, wherein the number of the capacitors is at least two, and the clamp circuit uses the same adjustable power source to charge and discharge the plurality of capacitors to generate the total Mode voltage. For example, the common mode voltage generating circuit described in claim 6 uses different adjustable current sources to respectively charge and discharge different capacitors to generate the common mode voltage. The common mode voltage generating circuit of claim 6, further comprising a switching component, wherein the number of the capacitors is at least two, the switching component is coupled to the capacitors for enabling the capacitors when conducting The generated voltages are equal. The common mode voltage generating circuit of claim 9, wherein the common mode voltage generating circuit generates the common mode voltage in a common mode voltage generating mode, and turns on the switching element before generating the common mode voltage These capacitors produce equal voltages.