TWI454007B - Power supply with open-loop and short-circuit protection - Google Patents

Description

Power supply with open circuit protection and short circuit protection

The present invention relates to a power supply, and more particularly to a power supply having open circuit protection and short circuit protection.

A typical power supply provides stable voltage and current. In order to comply with safety regulations, the power supply must provide open-loop protection and short circuit protection to ensure that the power supply itself and the application circuitry on the load side are unaffected. Referring to Figure 1, it is a circuit diagram of a conventional power supply with open loop protection. The conventional power supply includes a transformer T ₁ , a reset circuit 14 , a signal generating circuit 10 , an oscillator 12 , a power switch Q ₁ , a feedback detecting circuit 16 , a delay circuit 18 , and a driving circuit 20 .

As shown in Fig. 1, the transformer T ₁ has a primary side winding N _P and a secondary side winding N _S for storing energy and power conversion. The transformer T _{1 is} coupled to the input voltage V _{IN of the} power supply to generate an output voltage V _O . The power switch Q ₁ switches the transformer T ₁ to convert the energy stored in the primary winding N _{P of the} transformer T ₁ to the secondary winding N _S . The energy converted to the secondary winding N _S is rectified by the output rectifier D _O and the output capacitor C _{O to} generate an output voltage V _O . The current sense resistor R _{S is} connected in series with the power switch Q ₁ . The current sense resistor R _S generates a current signal V _CS according to the primary side switching current I _{P of the} transformer T ₁ . In addition, the output voltage V _{O of the} power supply provides the feedback signal V _FB to the reset circuit 14 and the feedback detection circuit 16 through a feedback mode.

The reset circuit 14 includes a logic circuit 144, a power limit comparator 146, and a PWM (Pulse Width Modulation) comparator 148. The reset circuit 14 generates a clear signal CLR according to the current signal V _CS , the power limit signal V _LMT and the feedback signal V _FB to turn off the switching signal V _PWM . The power limit comparator 146 and an input of the PWM comparator 148 are coupled to the current sense resistor R _S to receive the current signal V _CS . The other input of the power limit comparator 146 receives the power limit signal _VLMT . The other input of the PWM comparator 148 receives the feedback signal V _FB .

When the current signal V _{CS is} greater than the power limit signal V _LMT , the output of the power limit comparator 146 will output a low level over current signal OC. In addition, when the current signal V _{CS is} greater than the feedback signal V _FB , the output of the PWM comparator 148 will generate a low level feedback control signal CNTR. The two input ends of the logic circuit 144 are respectively coupled to the outputs of the power limit comparator 146 and the PWM comparator 148. Therefore, the output of the logic circuit 144 will generate a low-level clear signal CLR according to the over-current signal OC and/or the feedback control signal CNTR to turn off the switching signal V _PWM . In other words, the reset circuit 14 determines the logic level of the clear signal CLR according to the logic level of the feedback control signal CNTR or the logic level of the over current signal OC.

The signal generating circuit 10 includes a logic circuit 101, a flip-flop 103, and a logic circuit 105. The logic circuit 101 is an inverter, and its input terminal is coupled to the oscillator 12 to receive the clock signal PLS output by the oscillator 12. The output end of the logic circuit 101 is coupled to the clock input terminal CK of the flip-flop 103 to drive the flip-flop 103. The input terminal D of the flip-flop 103 is coupled to the output of the delay circuit 18. The output terminal Q of the flip-flop 103 is coupled to one input of the logic circuit 105, and the other input of the logic circuit 105 receives the clock signal PLS via the logic circuit 101. The output of the logic circuit 105 produces a switching signal _VPWM . The logic circuit 105 is an AND gate. The reset input terminal R of the flip-flop 103 is coupled to the output of the reset circuit 14 to receive the clear signal CLR. The signal generating circuit 10 is coupled to the output of the oscillator 12 and the reset circuit 14. The signal generating circuit 10 generates the switching signal V _PWM according to the clock signal PLS output from the oscillator 12. The driving circuit 20 receives the switching signal V _PWM to generate the driving signal V _G . The drive signal V _{G is} used to control the switching of the power switch Q ₁ to adjust the output voltage V _O . Since the switching signal V _PWM is supplied to the driving circuit 20 to generate the driving signal V _G , the switching signal V _{PWM is} also used to control the switching of the power switch Q ₁ . The signal generating circuit 10 periodically adjusts the pulse width of the switching signal V _PWM according to the clear signal CLR outputted by the reset circuit 14, so that the output voltage V _{O of} the power supply is stably adjusted, and the output power is limited.

Referring to FIG. 1 , the two input terminals of the feedback detection circuit 16 respectively receive the feedback signal V _FB and the threshold signal V _LIMT to generate a pull-high signal S _PH . When the power supply is operating normally, the feedback signal V _{FB is} lower than the critical signal V _LIMT . At this time, the output of the feedback detection circuit 16 generates a low-level pull-up signal S _PH . The delay circuit 18 does not count after receiving the low-level pull-up signal S _PH , and directly outputs the high-level cutoff signal S _OFF to the signal generating circuit 10. The signal generating circuit 10 receives the high-level cutoff signal S _OFF and does not latch the switching signal V _PWM .

However, when an open loop state occurs at the output of the power supply, the level of the feedback signal V _FB is pulled up to the supply voltage V _CC by pulling the high resistance R _PH . When the level of the feedback signal V _FB is pulled higher than the threshold signal V _LIMT , the output of the feedback detection circuit 16 generates a high-level pull-up signal S _PH . The delay circuit 18 counts the pull-up signal S _PH according to the high level and generates a low-level cutoff signal S _OFF after counting a delay time. The signal generating circuit 10 latches the switching signal V _PWM according to the low-level cutoff signal S _OFF , that is, the latch driving signal V _G . Therefore, when the feedback detection circuit 16 and the delay circuit 18 are pulled high when the level of the feedback signal V _FB is pulled high, the signal generation circuit 10 is driven to latch the switching signal V _PWM for open loop protection.

In addition, when the power supply is short-circuited, the level of the feedback signal V _FB is also pulled up to the supply voltage V _CC through the pull-up resistor R _PH . The feedback detection circuit 16 generates a high-level pull-up signal S _PH . I.e., the delay circuit 18 will be counted, and generates a low level OFF signal S _OFF delay time after a count. The signal generating circuit 10 latches the switching signal V _PWM according to the low-level cutoff signal S _OFF to protect the application circuit of the power supply and the load terminal. The delay time of the short circuit protection is the same as the delay time of the open circuit protection. However, when the power supply is short-circuited, the application circuit of the power supply or load terminal may be damaged in a short time. Therefore, in order to improve the safety of the power supply, the signal generating circuit 10 should short-circuit the switching signal V _PWM as soon as possible when the power supply is short-circuited. Therefore, how to make the power supply correctly distinguish the power supply from open circuit or short circuit and short-circuit protection as soon as the power supply is short-circuited is an important issue in the design of power supply today.

It is an object of the present invention to provide a power supply with open loop protection and short circuit protection. When the feedback signal is pulled high, the power supply of the present invention uses a conduction detection circuit to detect the on-time of the power switch, and distinguishes the power supply from an open circuit or a short circuit to determine the delay time of the delay circuit. In this way, when the power supply is short-circuited, the power supply can be short-circuit protected in a short time.

The power supply device with open loop protection and short circuit protection includes: a transformer, a power switch, a signal generating circuit, a conduction detecting circuit and a delay circuit. The transformer receives an input voltage for generating an output voltage. The power switch is coupled to the transformer and switches the transformer to adjust the output voltage. The signal generating circuit generates a switching signal to control the switching of the power switch. The conduction detection circuit detects an on-time of the power switch to generate a short-circuit signal. The delay circuit generates a cutoff signal according to the short circuit signal and one of the power supply feedback signals. The cutoff signal control signal generation circuit locks the switching signal. The conduction detection circuit detects the lead time of the power switch, and determines whether the power supply is short-circuited or open circuit to generate a short-circuit signal. The delay circuit determines to count the first delay time or the second delay time according to the short circuit signal. In this way, after the delay circuit counts different delay times in different conditions (short circuit or open circuit), a cutoff signal is generated to control the signal generating circuit to lock the switching signal, so that the power supply can be properly protected as soon as possible.

In order to give the reviewer a better understanding and understanding of the technical features of the present invention and the efficacies achieved, the following is a description of the preferred embodiment and a detailed description.

Please refer to FIG. 2, which is a circuit diagram of a first embodiment of a power supply with open circuit protection and short circuit protection according to the present invention. In addition to the prior art shown in FIG. 1, the present invention adds a conduction detecting circuit 30, a confirmation circuit 40, and a frequency divider 50. The turn-on detection circuit 30 receives the drive signal V _G or the switching signal V _PWM to detect the on-time of the power switch Q ₁ and generates a short-circuit signal S _OL . In addition, the continuity detecting circuit 30 further receives the clock signal PLS output from the oscillator 12. The short circuit signal S _{OL is} supplied to the confirmation circuit 40. The confirmation circuit 40 generates the selection signal S _SEL according to the short circuit signal S _OL and the reference signal. The reference signal may be the switching signal V _PWM or the driving signal V _G or the clock signal PLS related to the switching signal V _PWM . The clock signal PLS is derived from the oscillator 12 and is generated in synchronization with the drive signal V _G .

When the power supply is short-circuited, the output current will rise and the output voltage V _O will decrease. Since the output voltage V _{O is} proportional to the input voltage V _IN , the turns ratio of the primary side winding N _P to the secondary side winding N _S , the on time of the power switch Q ₁ , and the input voltage V _IN and the turns ratio are fixed values. . Therefore, the output voltage V _O decreases, which means that the lead time of the power switch Q ₁ is shortened. In other words, when the level of the feedback signal V _FB is greater than the threshold signal V _LIMT and the feedback detection circuit 16 generates the high level S _PH signal, and the conduction detection circuit 30 detects the power switch Q ₁ The lead time is shorter than the preset time threshold, indicating a short circuit in the power supply. In addition, when the feedback detection circuit 16 generates the high-level pull-up signal S _PH , if the lead time of the power switch Q ₁ continues to be higher than the preset time threshold, it indicates that the power supply is open circuit. The present invention utilizes conduction detection circuit 30 detects the power switch on-time Q _1, and confirm the short-circuit state occurs. Further, the confirmation circuit 40 confirms that the above-described open circuit state has occurred. The confirmation circuit 40 is coupled to the conduction detection circuit 30 and receives the short-circuit signal S _OL and the reference signal to confirm that the on-time of the power switch Q ₁ continues to be higher than a preset time threshold, and generates the selection signal S _SEL .

The delay circuit 19 is coupled to the feedback detection circuit 16 and the confirmation circuit 40, and receives the pull-up signal S _PH and the selection signal S _SEL . The delay circuit 19 generates the cutoff signal S _OFF according to the high level pull signal S _PH and the selection signal S _SEL after the preset first delay time or the second delay time. Signal generation circuit protection circuit 10 is turned off according to the latch signal S _OFF switching signal V _PWM, for open or short circuit protection. Since the level of the pull-up signal S _PH is determined by the level of the feedback signal V _FB , the delay circuit 19 starts counting according to the feedback signal V _FB to drive the signal generating circuit 10 to perform short-circuit protection or open loop protection. Wherein, the first delay time is shorter than the second delay time; the first delay time corresponds to short circuit protection, and the second delay time corresponds to open circuit protection. Since the confirmation circuit 40 generates the selection signal S _SEL according to the short-circuit signal S _OL to determine that the delay circuit 19 counts to the preset first delay time or the second delay time to generate the cut-off signal S _OFF , the delay circuit 19 is based on the short-circuit signal. S _OL decides to perform open loop protection or short circuit protection after counting to the first delay time or the second delay time.

The frequency divider 50 is coupled to the oscillator 12 and receives the basic pulse signal CLK generated by the oscillator 12. The frequency divider 30 divides the basic pulse signal CLK to generate the first pulse signal F _CLK and the second pulse signal S _CLK . The frequency of the first pulse signal F _CLK is higher than the frequency of the second pulse signal S _CLK , that is, the period of the first pulse signal F _CLK is shorter than the period of the second pulse signal S _CLK . The first pulse signal F _CLK and the second pulse signal S _CLK are transmitted to the delay circuit 19, and the delay circuit 19 selects the first pulse signal F _CLK or the second pulse signal S _CLK as a time reference according to the selection signal S _SEL ( Time base) is to count the first delay time or the second delay time.

Please refer to FIG. 3, which is an embodiment of a circuit diagram of the continuity detecting circuit of the present invention. As shown, the conduction detection circuit 30 includes a sawtooth signal generation circuit, a comparator 305, and a counter circuit. The sawtooth signal generating circuit includes an inverter 301, a current source 302, a transistor 303, and a capacitor 304. The sawtooth signal generating circuit generates a sawtooth signal V _SAW according to the on time of the power switch Q ₁ . The input terminal of the inverter 301 receives the driving signal V _G or the switching signal V _PWM . The output of the inverter 301 is coupled to the gate of the transistor 303 to control the transistor 303 to be turned on and off. The source of the transistor 303 is coupled to the ground. The current source 302 is coupled between the supply voltage V _CC and one end of the capacitor 304 for charging the capacitor 304. The other end of the capacitor 304 is coupled to the ground. The drain of the transistor 303 is coupled to the capacitor 304 for discharging the capacitor 304.

When the drive signal V _G or the switching signal V _{PWM is} enabled, the inverter 301 turns off the transistor 303, and the current source 302 charges the capacitor 304. When the driving signal V _G or the switching signal V _{PWM is} disabled, the inverter 301 conducts the crystal 303 and the capacitor 304 is discharged. Thus, the sawtooth signal V _SAW is generated from the capacitor 304. Since the driving signal V _G switching signal V _PWM or actuation time of the energy with respect to the power switch Q is turned _an appropriate time, in other words, is a sawtooth signal generation circuit according to the power switch on-time Q ₁ produces a sawtooth signal V _SAW. The negative input terminal and the positive input terminal of the comparator 305 receive the sawtooth signal V _SAW and the threshold signal V _{TH respectively} to compare the sawtooth signal V _SAW with the threshold signal V _{TH .} The output of comparator 305 produces a periodic signal S _DUTY .

As shown in FIG. 6A, when the sawtooth signal V _{SAW is} smaller than the threshold signal V _TH , the level of the periodic signal S _DUTY is at a high level. When the sawtooth signal V _{SAW is} greater than the threshold signal V _TH , the level of the periodic signal S _DUTY is a low level. In other words, when the lead time of the power switch Q ₁ is short, the sawtooth signal V _SAW is lower than the threshold signal V _TH , and the level of the periodic signal S _DUTY is at a high level. When the conduction time of the power switch Q ₁ is long, the sawtooth signal V _SAW is higher than the threshold signal V _TH , and the level of the periodic signal S _DUTY is a low level. The threshold of the threshold signal V _{TH is} the time threshold. The level of the periodic signal S _DUTY is a high level, which means that the on-time of the power switch Q ₁ is lower than the time threshold. The level of the periodic signal S _DUTY is a low level, which means that the lead time of the power switch Q ₁ is higher than the time threshold.

The counting circuit includes flip-flops 306 and 307. The counting circuit is used to confirm that the on-time of the power switch Q ₁ is not a malfunction of the power supply and is temporarily lower than the time threshold. The clock terminals CK of the flip-flops 306 and 307 receive the trigger signal for counting. The trigger signal is the drive signal V _G , the switching signal V _PWM or the clock signal PLS. The input D of the flip flop 306 receives the supply voltage V _CC . The input terminal D of the flip-flop 307 is coupled to the output terminal Q of the flip-flop 306. The inverting output /Q of the flip-flop 307 generates a short-circuit signal S _OL . In addition, the reset terminals R of the flip-flops 306 and 307 are coupled to the output of the comparator 305 for receiving the periodic signal S _DUTY .

Therefore, when the on-time of the power switch Q ₁ is less than the time threshold and the period signal S _DUTY is at the high level, the flip-flops 306 and 307 are not reset. The counting circuit counts according to the driving signal V _G , the switching signal V _PWM or the clock signal PLS. After the counting circuit counts for a predetermined time, a short-level short-circuit signal S _OL is generated. When the power switch Q ₁ is higher than the on-time and time period threshold S _DUTY signal is at low level, and the flip-flop 306 will be reset 307, a short-circuit signal S _OL level of a high level. If the feedback signal V _{FB is} higher than the critical signal V _LIMT (see Figure 2) and the level of the short-circuit signal S _OL is low, it indicates that the power supply is short-circuited. If the feedback signal V _{FB is} higher than the critical signal V _LIMT and the level of the short circuit signal S _OL is at a high level, it means that the power supply is open circuit.

Please refer to FIG. 4, which is an embodiment of a circuit diagram of the verification circuit of the present invention. As shown, the validation circuit 40 includes flip-flops 401 and 402. Validation circuit 40 for confirming the conduction time of the power switch Q ₁ is higher than the duration time threshold, rather than a malfunction of the power supply and short time above threshold based on the short-circuit signal S _OL. The clock terminal CK of the flip-flops 401 and 402 receives the driving signal V _G , the switching signal V _PWM or the clock signal PLS to count according to the driving signal V _G , the switching signal V _PWM or the clock signal PLS. The input terminal D of the flip-flop 401 receives the supply voltage V _CC . The input terminal D of the flip-flop 402 is coupled to the output terminal Q of the flip-flop 401. The output Q of the flip-flop 402 generates a selection signal S _SEL . In addition, the reset terminals R of the flip-flops 401 and 402 receive the short-circuit signal S _OL .

When the conduction time of the power switch Q ₁ is less than the time threshold and the level of the short circuit signal S _OL is at the low level, the flip-flops 401 and 402 will be reset, and the level of the selection signal S _SEL is at the low level. When the conduction time of the power switch Q ₁ is greater than the time threshold and the level of the short circuit signal S _OL is at the high level, the flip-flops 401 and 402 are not reset, and according to the driving signal V _G , the switching signal V _PWM or the time The pulse signal PLS is counted. If the lead time of the power switch Q ₁ is greater than the time threshold during the period of the preset driving signal V _G , the switching signal V _PWM or the clock signal PLS, it is confirmed that the conduction time of the power switch Q ₁ continues to be longer than the time threshold. The flip-flop 402 generates a high-level selection signal S _SEL .

Fig. 5 is an embodiment of a circuit diagram of the delay circuit 19 of the present invention. The delay circuit 19 includes flip-flops 192, 194, ... 195, an inverter 196, or a gate 197, a first switch 198, and a second switch 199. The first switch 198 and the second switch 199 are both coupled to the frequency divider 50 (as shown in FIG. 2) to receive the first pulse signal F _CLK and the second pulse signal S _{CLK , respectively} . The other ends of the first switch 198 and the second switch 199 are respectively coupled to the two input terminals of the gate 197. The first switch 198 transmits the first pulse signal F _CLK to the OR gate 197 via the inverter 196 controlled by the selection signal S _SEL . The second switch 199 is directly controlled by the selection signal S _SEL to transmit the second pulse signal S _CLK to the OR gate 197. Or the output of the gate 197 produces an output signal S _PCK . In other words, the output signal S _PCK is the first pulse signal F _CLK or the second pulse signal S _CLK .

The clock terminal CK of the flip-flop 192 is connected to the output of the OR gate 197 to receive the output signal S _PCK (the first pulse signal F _CLK or the second pulse signal S _CLK ). The input terminal D of the flip-flops 192, 194, ... 195 receives the supply voltage V _CC . The clock terminals CK of the flip-flops 194 and 195 are coupled to the output terminal Q of the upper-stage flip-flop. For example, the clock terminal CK of the flip flop 194 is coupled to the output terminal Q of the flip flop 192. The inverting output /Q of the flip-flop 195 generates a cutoff signal _SOFF . In addition, the reset terminals R of the flip-flops 192, 194, . . . 195 are coupled to the output of the feedback detection circuit 16 (see FIG. 2) for receiving the pull-up signal S _PH . The delay circuit 19 counts according to the first pulse signal F _CLK , that is, counts the first delay time. The delay circuit 19 counts according to the second pulse signal S _CLK , that is, counts the second delay time. In other words, the delay circuit 19 controls the first switch 198 or the second switch 199 according to the selection signal S _SEL to control the flip-flop 192 to start operating according to the first pulse signal F _CLK or the second pulse signal S _CLK . Therefore, the delay circuit 19 counts the first delay time or the second delay time in accordance with the selection signal S _SEL . When the period of the first pulse signal F _CLK is shorter than the period of the second pulse signal S _CLK , the first delay time is shorter than the second delay time.

Please refer to Figure 2. When the power supply is operating normally, the feedback signal V _FB will be lower than the critical signal V _LIMT . At this time, the output of the feedback detection circuit 16 generates a low-level pull-up signal S _PH . After the delay circuit 19 receives the low level pull signal S _PH , the flip flops 192, 194, ... 195 (see Fig. 5) will be reset. Therefore, the delay circuit 19 does not count, and the inverted output terminal /Q of the flip-flop 195 of the last stage of the delay circuit 19 directly outputs the high-level cutoff signal S _OFF . In other words, when the power supply is operating normally, the off signal S _OFF at a high level, the signal generation circuit 10 will not be switching signal V _PWM latch.

In addition, when the power supply is in the open circuit state or the short circuit state, the level of the feedback signal V _FB is pulled up to the supply voltage V _CC (higher than the critical signal V _LIMT ). Therefore, the feedback detection circuit 16 generates a high-level pull-up signal S _PH . The conduction detecting circuit 30 detects whether the lead time of the power switch Q ₁ is greater than a preset time threshold, and determines whether the power supply is open circuit or short circuited. When the lead time of the power switch Q ₁ is greater than the time threshold, the level of the short circuit signal S _OL is at a high level, indicating that the power supply is an open circuit. At this time, through the validation circuit 40 asserts the power switch Q ₁ 'on-time duration greater than the time threshold. The acknowledgment circuit 40 will generate a high level select signal S _SEL . The delay circuit 19 counts the second delay time according to the high level selection signal S _SEL (the delay circuit 19 counts according to the second pulse signal S _CLK ), and generates the inverted output terminal /Q of the flip-flop 195 of the last stage. The low-level cutoff signal S _{OFF is applied} to the signal generating circuit 10, and the switching signal V _PWM is latched. In this way, the power supply is protected by open circuit.

Conversely, when the conduction time of the power switch Q ₁ is less than the time threshold, the level of the short circuit signal S _OL is a low level, indicating that the power supply is short-circuited. At this time, the confirmation circuit 40 generates a low level selection signal S _SEL . The delay circuit 19 counts the first delay time according to the low level selection signal S _SEL (the delay circuit 19 counts according to the first pulse signal F _CLK ) to generate the low level cutoff signal S _OFF . The signal generating circuit 10 latches the switching signal V _PWM according to the low-level cutoff signal S _OFF . In this way, the power supply is short-circuit protected.

Please refer to FIGS. 6A and 6B for waveform diagrams of the power supply of the present invention. Please refer to Figures 2, 3 and 4 together. As shown in Figure 6A, when the power supply is operating normally, the feedback signal V _FB will be lower than the critical signal V _LIMT , and the level of the pull-up signal S _PH is Low level. The delay circuit 19 will be reset by the low level pull-up signal S _PH . Therefore, the delay circuit 19 does not count, but directly outputs the high-level cutoff signal S _OFF to the signal generating circuit 10. The switching signal V _{PWM is} not latched, and the driving signal V _G is not latched, so the power supply remains in normal operation.

As shown in Fig. 64, when the driving signal V _G starts to be enabled (the power switch Q _{1 is} turned on), the level of the sawtooth signal V _SAW gradually increases. When the driving signal V _{G is} disabled, the level of the sawtooth signal V _SAW is at a low level. Thus, the sawtooth signal V _SAW is related to the on-time of the power switch Q ₁ . When the level of the sawtooth signal V _SAW is higher than the threshold signal V _TH , the level of the periodic signal S _DUTY is changed from the high level to the low level, and the level of the short circuit signal S _OL is changed from the low level to the high level. . When the level of the short circuit signal S _OL is turned to the high level, it means that the on time of the power switch Q ₁ is greater than the time threshold.

Subsequently, the validation circuit 40 asserts the ON time of the power switch Q ₁ is higher than the time duration of the high level threshold based on the short-circuit signal S _OL (i.e., level of short-circuit signal S _OL Switch to high level after a period of time)), i.e., the output The high level selection signal S _SEL . The delay circuit 19 changes the output signal S _PCK according to the high level selection signal S _SEL , from the first pulse signal F _CLK to the second pulse signal S _CLK , and counts according to the second pulse signal S _CLK . In other words, the delay circuit 19 selects the second pulse signal S _CLK according to the short-circuit signal S _OL and counts it. After a second delay circuit 19 counts the delay time T _DL, generates a low level to the off signal S _OFF signal generation circuit 10, for latching the switching signal V _PWM (i.e., the drive signal for latching V _G), for Open circuit protection.

In addition, as shown in FIG. 6B, when the enable time of the driving signal V _G is short (the conduction time of the power switch Q ₁ is short), the level of the sawtooth signal V _SAW will be lower than the threshold signal V _TH . At this time, the level of the periodic signal S _DUTY is a high level, that is, the on time of the power switch Q ₁ is less than the time threshold. The short circuit signal S _OL is converted from the high level to the low level after counting for a period of time according to the periodic signal S _DUTY via the counting circuit (including the flip-flops 306 and 307) shown in FIG. The confirmation circuit 40 outputs a low level selection signal S _SEL according to the low level short signal S _OL . When the feedback signal V _{FB is} higher than the critical signal V _LIMT and the on-time of the power switch Q ₁ is less than the time threshold, it indicates that the power supply is short-circuited.

The delay circuit 19 changes the output signal S _PCK according to the low level selection signal S _{SEL , and} converts the second pulse signal S _OLK into the first pulse signal F _CLK (the period of the first pulse signal F _CLK is shorter than the second period) The period of the pulse signal S _CLK ). The delay circuit 19 counts based on the first pulse signal F _CLK . In other words, the delay circuit 19 counts the first pulse signal F _CLK according to the short-circuit signal S _OL . After the delay circuit 19 counts the first delay time T _DS , a low-level cutoff signal S _{OFF is} generated to the signal generating circuit 10 to latch the switching signal V _PWM (ie, the driving signal V _G is latched) to Short circuit protection. Since the period of the first pulse signal F _CLK is short, the first delay time T _{DS is} short, so that short-circuit protection can be quickly performed when the power supply is short-circuited to avoid damage to the application circuit of the power supply and the load end.

Figure 7 is a circuit diagram of a power supply of another embodiment of the present invention. As shown in the figure, the difference between this embodiment and the first embodiment is that the embodiment does not have the confirmation circuit 40 (as shown in FIG. 2), and the conduction detection circuit 30 is directly connected to the delay circuit 19. Referring to FIG. 7, the short circuit signal S _OL outputted by the conduction detecting circuit 30 is transmitted to the delay circuit 19 to control the first switch 198 and the second switch 199 of the delay circuit 19 (as shown in FIG. 5). Therefore, the short circuit signal S _{OL of} this embodiment is used as the selection signal S _{SEL of the} second figure to select the first pulse signal F _CLK or the second pulse signal S _CLK . When the level of the sawtooth signal V _SAW is higher than the threshold signal V _TH (as shown in FIG. 6A ), the periodic signal S _DUTY is at a low level and the short circuit signal S _OL is at a high level, indicating the on time of the power switch Q ₁ . Greater than the time threshold. The high-level short-circuit signal S _OL turns on the second switch 199 (refer to FIG. 5) to transmit the second pulse signal S _CLK to the flip-flop 192 for open-loop protection.

In addition, when the level of the sawtooth signal V _SAW is lower than the threshold signal V _TH , the periodic signal S _DUTY is at a high level, and the short circuit signal S _OL is at a low level, indicating that the on time of the power switch Q ₁ is less than the time threshold. The low-level short-circuit signal S _OL turns on the first switch 198 via the inverter 196 (shown in FIG. 5) to transmit the first pulse signal F _CLK to the flip-flop 192 for short-circuit protection.

Therefore, the present invention is a novelty, progressive and available for industrial use. It should be in accordance with the requirements of patent applications for patent law in China. It is undoubtedly to file an invention patent application according to law, and the Prayer Council will grant patents as soon as possible.

However, the above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, so that the shapes, structures, features, and spirits described in the claims of the present invention are equally changed. Modifications are intended to be included in the scope of the patent application of the present invention.

10. . . Signal generation circuit

101. . . Logic circuit

103. . . Positive and negative

105. . . Logic circuit

12. . . Oscillator

14. . . Reset circuit

144. . . Logic circuit

146. . . Power limit comparator

148. . . PWM comparator

16. . . Feedback detection circuit

18. . . Delay circuit

19. . . Delay circuit

192. . . Positive and negative

194. . . Positive and negative

195. . . Positive and negative

196. . . inverter

197. . . Gate

198. . . First switch

199. . . Second switch

20. . . Drive circuit

30. . . Continuity detection circuit

301. . . inverter

302. . . Battery

303. . . Transistor

304. . . capacitance

305. . . Comparators

306. . . Positive and negative

307. . . Positive and negative

40. . . Confirmation circuit

401. . . Positive and negative

402. . . Positive and negative

50. . . Frequency divider

C _O . . . Output capacitor

CLK. . . Basic pulse signal

CLR. . . Clear signal

CNTR. . . Feedback control signal

D _O . . . Output rectifier

F _CLK . . . First pulse signal

I _P . . . Primary side switching current

N _P . . . Primary winding

N _S . . . Secondary winding

PLS. . . Clock signal

Q ₁ . . . Power switch

R _PH . . . Pull high resistance

R _S . . . Current sense resistor

S _CLK . . . Second pulse signal

S _DUTY . . . Periodic signal

S _OFF . . . Cutoff signal

S _OL . . . Short circuit signal

S _PCK . . . Output signal

S _PH . . . Pull high signal

S _SEL . . . Select signal

T ₁ . . . transformer

T _DL . . . Second delay time

T _DS . . . First delay time

V _CC . . . Supply voltage

V _CS . . . Current signal

V _FB . . . Feedback signal

V _G . . . Drive signal

V _IN . . . Input voltage

V _LIMT . . . Critical signal

V _LMT . . . Power limit signal

V _O . . . The output voltage

V _PWM . . . Switching signal

V _SAW . . . Sawtooth signal

V _TH . . . Threshold signal

Figure 1 is a circuit diagram of a conventional power supply with open circuit protection;

2 is a circuit diagram of a power supply device having open circuit protection and short circuit protection according to a first embodiment of the present invention;

Figure 3 is an embodiment of a circuit diagram of the continuity detecting circuit of the present invention;

Figure 4 is an embodiment of a circuit diagram of the confirmation circuit of the present invention;

Figure 5 is an embodiment of a circuit diagram of a delay circuit of the present invention;

6A and 6B are waveform diagrams of the power supply of the present invention having open circuit protection and short circuit protection;

Figure 7 is a circuit diagram of a power supply having open circuit protection and short circuit protection in a second embodiment of the present invention.

10. . . Signal generation circuit

101. . . Logic circuit

103. . . Positive and negative

105. . . Logic circuit

12. . . Oscillator

14. . . Reset circuit

144. . . Logic circuit

146. . . Power limit comparator

148. . . PWM comparator

16. . . Feedback detection circuit

19. . . Delay circuit

20. . . Drive circuit

30. . . Continuity detection circuit

40. . . Confirmation circuit

50. . . Frequency divider

C _O . . . Output capacitor

CLK. . . Basic pulse signal

CLR. . . Clear signal

CNTR. . . Feedback control signal

D _O . . . Output rectifier

F _CLK . . . First pulse signal

I _P . . . Primary side switching current

N _P . . . Primary winding

N _S . . . Secondary winding

PLS. . . Clock signal

Q ₁ . . . Power switch

R _PH . . . Pull high resistance

R _S . . . Current sense resistor

S _CLK . . . Second pulse signal

S _OFF . . . Cutoff signal

S _OL . . . Short circuit signal

S _PH . . . Pull high signal

S _SEL . . . Select signal

T ₁ . . . transformer

V _CC . . . Supply voltage

V _CS . . . Current signal

V _FB . . . Feedback signal

V _G . . . Drive signal

V _IN . . . Input voltage

V _LIMT . . . Critical signal

V _LMT . . . Power limit signal

V _O . . . The output voltage

V _PWM . . . Switching signal

Claims (10)

A power supply with open circuit protection and short circuit protection, comprising: a transformer, the transformer receives an input voltage to generate an output voltage; a power switch coupled to the transformer and switches the transformer to adjust the An output voltage; a signal generating circuit, the signal generating circuit generates a switching signal to control switching of the power switch; and a conduction detecting circuit, the conduction detecting circuit detects an on-time of the power switch to generate a short-circuit signal And a delay circuit, wherein the delay circuit counts a first delay time or a second delay time according to the feedback signal of the power supply and the short circuit signal to generate a cutoff signal to the signal generating circuit, and The switching signal is locked; wherein the delay circuit determines to count the first delay time or the second delay time according to the short circuit signal. The power supply device with open loop protection and short circuit protection as described in claim 1 further includes: a confirmation circuit, the confirmation circuit confirms the guide of the power switch according to a reference signal and the short circuit signal The appropriate time continues to be higher than a time threshold and generates a selection signal, wherein the delay circuit determines to count the first delay time or the second delay time according to the selection signal. The power supply with open circuit protection and short circuit protection as described in claim 2, wherein the reference signal is related to the switching signal. The power supply device with open circuit protection and short circuit protection as described in claim 1, wherein the conduction detection circuit detects the conduction time of the power switch, the conduction time is less than a time threshold and the feedback is The signal is higher than a critical signal to indicate that the power supply is shorted, and the delay circuit counts the first delay time according to the short circuit signal; the lead time is greater than the time threshold and the feedback signal is higher than the threshold signal to indicate the power supply The circuit is opened, and the delay circuit counts the second delay time according to the short circuit signal, and the first delay time is shorter than the second delay time. The power supply device with open circuit protection and short circuit protection according to claim 1, wherein the conduction detection circuit comprises: a sawtooth signal generation circuit, wherein the sawtooth signal generation circuit generates the conduction time according to the power switch. a sawtooth signal; a comparator, the comparator compares the sawtooth signal with a threshold signal to generate a periodic signal; and a counting circuit that counts according to a trigger signal and the periodic signal, and generates the short circuit signal. The power supply device with open loop protection and short circuit protection as described in claim 1 further includes: an oscillator that generates a basic pulse signal; and a frequency divider, the frequency divider Receiving the basic pulse wave signal and dividing the basic pulse wave signal to generate a first pulse wave signal and a second pulse wave signal; wherein the delay circuit selects the first pulse wave signal or the first according to the short circuit signal The second pulse signal is configured to count the first delay time or the second delay time according to the first pulse signal or the second pulse signal. The power supply device with open circuit protection and short circuit protection as described in claim 1 further includes: an oscillator, the oscillator generates a clock signal, and the signal generating circuit generates the switching according to the clock signal. Signal. The power supply device with open loop protection and short circuit protection as described in claim 1 further includes: a feedback detection circuit, wherein the feedback detection circuit generates the feedback signal according to the power supply A pull-up signal, the delay circuit counts the first delay time or the second delay time according to the pull-up signal and the short-circuit signal. The power supply device with open loop protection and short circuit protection according to claim 8 , wherein the feedback detection circuit generates the pull-up signal according to the feedback signal and a threshold signal. The power supply device with open loop protection and short circuit protection as described in claim 1 further includes: a reset circuit, wherein the reset circuit is based on a current signal, a power limit signal, and the power supply The feedback signal generates a clear signal to end the switching signal.