TWI453894B - Low voltage bandgap reference (bgr) circuit - Google Patents

Description

Low voltage energy level reference level circuit

The present invention relates to a bandgap reference (BGR) circuit, and more particularly to an energy level reference level circuit having a low voltage and correlated double sampling (CDS).

A voltage reference is used to generate a fixed voltage that is unaffected by the load. The energy level circuit is a type of reference voltage circuit that produces a fixed reference voltage value that is approximately equivalent to the electronic energy level of 矽 (about 1.2 volts), and the resulting reference voltage is hardly affected by temperature.

The first B diagram shows a conventional energy level reference level (BGR) circuit. The energy level reference level circuit 1 includes two transistors Q ₁ , Q ₂ connected in series to the current source I ₁ and the current source I ₂ , respectively. The terminal voltage of the transistor Q ₁ is V _EB , which has a negative temperature coefficient of about -1.5 mV / K, as shown in the first B picture, and the voltage difference ΔV _{EB of the} two transistors Q ₁ , Q ₂ has + The positive temperature coefficient of 0.087mV/K, the two voltage values are multiplied by the corresponding coefficients and then added to generate a temperature independent reference level voltage, which is the resistance ratio of the resistor R ₂ /R ₁ and the transistor Q ₁ , the area ratio of Q ₂ is determined. The current source I ₁ and the current source I _{2 are} controlled by a signal source circuit (SSC), as shown in FIG.

The trend of low voltage operating system technology, especially in mobile battery operated products, requires a particularly low reference voltage. However, when the power supply voltage is less than 1.5V, it is difficult to operate stably in the common bandgap reference circuit. The main reason is that in low-voltage operation, only low-gain amplifiers can be used, which results in a more severe offset and an inaccurate energy-level reference level.

Therefore, it is urgent to propose a novel energy level reference level circuit, which can correct the gain error of the low gain amplifier under low voltage operation to produce a more accurate energy level reference level voltage.

In view of the above, one of the objects of embodiments of the present invention is to provide an energy level reference level circuit capable of correcting a gain error of a low gain amplifier under low voltage operation to generate a more accurate energy level reference level voltage, thereby Improve the overall efficiency of the energy level reference level circuit.

The present invention discloses a low voltage energy level reference bitgap reference circuit including a first current source, a first transistor, a second current source, a second transistor, and an operational amplifier. a first capacitor group, a second capacitor group, a compensation capacitor, and a plurality of switches. The common collector of the first transistor is electrically connected in series to the first current source, and the common collector of the second transistor is electrically connected in series to the second current source. The first capacitor set is used to store a first reference voltage of the first transistor in a predictive phase. The second capacitor group is coupled to the negative input terminal of the operational amplifier during the prediction phase, and is used to generate an offset voltage of the operational amplifier, wherein the offset voltage has an offset. The compensation capacitor is coupled to the operational amplifier Negative input used to store this offset during the prediction phase. A plurality of open relationships are used to switch between the prediction phase and an amplification phase. The compensation capacitor is coupled between the negative input terminal of the operational amplifier and the first capacitor group to offset the offset, so that the operational amplifier can output a precise one-level reference level voltage.

The present invention further discloses a low voltage energy level reference bitgap reference circuit including a current source, a first transistor, a second transistor, an operational amplifier, a first capacitor group, and a first prediction. A capacitor, a second predictive capacitor, a compensation capacitor, and a plurality of switches. The common set of the first transistor is electrically connected in series to the current source, and the common collector of the second transistor is electrically connected in series to the current source. The first capacitor set is used to store a first reference voltage of the first transistor in a predictive phase. The first prediction capacitor is coupled between the negative input terminal and the output terminal of the operational amplifier during the prediction phase, and is configured to store an energy level reference level voltage output by the operational amplifier during an amplification phase, and generate an operational amplifier An offset voltage, wherein the offset voltage has an offset. The second predicted capacitance is reset by being coupled to a predetermined potential during the prediction phase. The compensation capacitor is coupled to the negative input of the operational amplifier for storing the offset during the prediction phase. A plurality of open relationships are used to switch between the prediction phase and the amplification phase. The second transistor is not connected to the current source during the prediction phase, and the compensation capacitor is coupled between the negative input terminal of the operational amplifier and the first capacitor group and the second prediction capacitor to offset the offset during the amplification phase. The amount, which in turn enables the op amp to output a precise energy level reference level voltage.

Conventional knowledge

M ₁ ‧‧‧First MOS

M ₂ ‧‧‧Second MOS

Q ₁ ‧‧‧First transistor

Q ₂ ‧‧‧Second transistor

Terminal voltage of V _EB ‧‧‧Q1

ΔV _EB ‧‧‧Q1, Q2 voltage difference

this invention

M ₁ ‧‧‧First MOS

M ₂ ‧‧‧Second MOS

Q ₁ ‧‧‧First transistor

Q ₂ ‧‧‧Second transistor

21‧‧‧First Capacitor Group

C _f ‧‧‧first processing capacitor

C _s ‧‧‧second processing capacitor

C _d ‧‧‧third processing capacitor

23‧‧‧Second capacitor group

C _{s_p ‧‧‧first} predicted capacitance

C _{f_p} ‧‧‧second predictive capacitance

C _{d_p} ‧‧‧third predictive capacitance

25‧‧‧Operational Amplifier

V _OS ‧‧‧ offset voltage

C ₁ ‧‧‧Compensation capacitor

V _bg ‧‧‧ energy level reference level voltage

C _Load ‧‧‧Support Capacitor

C _{d_1} ‧‧‧first predicted capacitance

C _{d_2} ‧‧‧second predictive capacitance

The first A picture and the first B picture are conventional energy level reference level circuits.

The second figure is a circuit diagram of an energy level reference level circuit according to an embodiment of the present invention.

The third A diagram is a circuit diagram of the energy level reference level circuit of an embodiment of the present invention at the prediction stage.

The third B diagram is a circuit diagram of the energy level reference level circuit of an embodiment of the present invention in the amplification stage.

The fourth A diagram is a circuit diagram of the energy level reference level circuit of another embodiment of the present invention at the prediction stage.

The fourth B diagram is a circuit diagram of the energy level reference level circuit of another embodiment of the present invention in the amplification stage.

The fifth A-five D diagram is a circuit diagram of an energy level reference level circuit according to still another embodiment of the present invention.

First, please refer to the second figure, which is a circuit diagram of a bandgap reference (BGR) circuit 2 according to an embodiment of the present invention. As shown in the second figure, the energy level reference level circuit 2 includes a first current source I ₁ (which may be composed of a first resistor R ₁ and a first MOS (M ₁ )), and a first transistor Q _{1 .} a second current source I ₂ (which may be composed of a second resistor R ₂ and a second MOS (M ₂ )), a second transistor Q ₂ , an operational amplifier 25, and a first capacitor Group 21 and a second capacitor group 23. The first transistor Q ₁ is electrically connected in series to the first current source I ₁ , and the second transistor Q ₂ is electrically connected in series to the second current source I ₂ . In a specific embodiment, the first transistor Q ₁ and the second transistor Q ₂ are diode-connected, and the first transistor Q ₁ and the second transistor Q ₂ have 1 : Area ratio of M, where the M value is greater than one.

In order to correct the gain error of the low gain operational amplifier 25, the present invention uses a correlated double sampling (CDS) technique that uses two sets of capacitor banks 21, 23 to predict the voltage offset, and then The two sets of capacitor groups 21, 23 are controlled to perform prediction and signal processing at different times to cancel the gain error of the operational amplifier 25. In a specific embodiment, the energy level reference level circuit 2 has at least two clock phases, such as a prediction phase and an amplification phase, and is switched by a switch (not shown) in the circuit.

The third A diagram is a circuit diagram of the energy level reference level circuit 2 of an embodiment of the present invention at the prediction stage. As shown in the third A diagram, the first current source I ₁ and the first current source I ₂ are represented by the current flowing through. The first capacitor group 21 is actually used to process the signal source to generate the energy reference circuit, which includes a first processing capacitor C _f , a second processing capacitor C _s and a third processing capacitor C _d ; and the second capacitor group 23 system is used to predict the operational amplifier offset (offset) 25 to compensate, comprising a first prediction capacitor _C s_p, predicted a second and a third capacitor _C f_p predicted capacitor _C d_p.

Specifically, when entering the prediction phase, the first processing capacitor C _f and the second processing capacitor C _s are electrically connected in parallel and coupled to a common collector of the first transistor Q ₁ to store the first The terminal voltage of the common collector of the transistor Q _{1 is} the first reference voltage VQ ₁ . The third processing capacitor C _d is coupled to a predetermined potential and is reset. Specifically, the preset potential may be a ground terminal (in a single ended circuit) or a common potential (in a double ended differential circuit), but not The exposer is limited.

When the prediction stage, the first capacitor _C s_p prediction system coupled between the second transistor Q ₂ and the common collector terminal of the third prediction capacitance _C d_p, second and third prediction in the prediction based capacitance _C f_p electrically connected in parallel Capacitor C _{d_p} . One end of the compensation capacitor C ₁ is coupled to the negative input line of the operational amplifier 25 and the first prediction of the capacitor _C s_p, the capacitance between the second predicted _C f_p, third prediction capacitance _C d_p, compensation capacitor C and the other _end coupled Connected to the preset potential. The second capacitor group 23 for generating an operational amplifier 25 based offset voltage (offset voltage) having an offset (offset) of V _OS, is stored by the compensation capacitor C ₁ of this offset. For details, please refer to the Taiwan Patent Application No. 100115437, which will not be repeated here.

The third B diagram is a circuit diagram of the energy level reference level circuit 2 of an embodiment of the present invention in the amplification stage. As shown in the third B diagram, when entering the amplification phase, the first capacitor group 21 and the second capacitor group 23 are symmetrically switched. Specifically, in the amplification phase, the control compensation capacitor C _{1 is} coupled between the negative input terminal of the operational amplifier 25 and the first processing capacitor C _f , the second processing capacitor C _{s ,} and the third processing capacitor C _d to be used. The offset stored in the prediction phase compensates for the offset voltage V _OS , thereby avoiding the gain error of the operational amplifier 25. In this way, the operational amplifier 25 can output a precise energy level reference level voltage V _bg which does not drift due to the change of the voltage source VDD.

In addition, during the amplification phase, the second processing capacitor C _s is controlled to be coupled between the common collector terminal of the second transistor Q ₂ and the first processing capacitor C _f . Since the prediction stage, the second process stored capacitance C _s second transistor Q common collector terminal voltage electrode _1, so at the time of amplification phase, a second capacitor C _s will process the stored first transistor Q ₁ Total The voltage difference between the terminal voltage of the collector (the first reference voltage) and the terminal voltage of the common collector of the second transistor Q ₂ , that is, ΔVQ (second reference voltage). The operational amplifier 25 has an output terminal, and in the amplification phase, the first processing capacitor C _f is connected in series between the second processing capacitor C _s and the output terminal of the operational amplifier 25 . Since the amount of charge stored by the first processing capacitor C _f is C _f *VQ ₁ during the prediction phase, the amount of charge stored by the first processing capacitor C _f at this time becomes C _f *VQ ₁ +C _s *ΔVQ, wherein The capacitance value of the first processing capacitor C _f can be regarded as the negative temperature coefficient of the first reference voltage VQ ₁ , and the capacitance value of the second processing capacitor C _s can be regarded as the positive temperature coefficient of the second reference voltage ΔVQ . The amount of charge on the first processing capacitor _Cf is temperature independent and therefore produces a temperature independent energy level reference level voltage _Vbg .

It is worth mentioning that the current energy level reference level voltage V _bg is independent of temperature, but its value is still slightly larger. In order to comply with low voltage environment operation, the third processing capacitor C has been reset during the amplification phase. _d is controlled to be electrically connected in parallel to the first processing capacitor C _f for equally dividing the amount of charge on the first processing capacitor C _f to reduce the energy level reference level voltage V _bg . By adjusting the capacitance value of the third processing capacitor C _d , different energy level reference level voltages V _bg can be generated according to requirements, thereby increasing the flexibility of the circuit application.

When amplification stage, a second capacitor group 23 operating system 21 symmetrically with the first capacitor bank, which means control the first prediction of the second capacitor _C s_p predicted capacitor _C f_p and electrically connected in parallel and coupled to the first transistor Q ₁ and controlling the third prediction capacitor C _{d_p to be} coupled to the preset potential and being reset.

Next, please refer to FIG. 4A and FIG. 4B, which are circuit diagrams of the energy level reference level circuit 2 of another embodiment of the present invention in the prediction and amplification stages, respectively. In the above embodiment, the energy level reference level voltage V _bg generated by the two stages is different and is not suitable for continuous operation. Therefore, in this embodiment, a sustain capacitor C _{Load is added} , as shown in the figure. Connected to the output of the operational amplifier 25, used to stabilize the output of the energy level reference level voltage V _bg . Specifically, during the prediction phase, the sustain capacitor C _Load disconnects the output of the operational amplifier 25 to maintain the energy level reference level voltage V _bg maintained at the sustain capacitor C _Load ; while in the amplification phase, the capacitor C _Load is maintained. The storage voltage is started so that the output of the operational amplifier 25 is not disturbed by the switching phase, thereby maintaining a relatively stable output.

Finally, please refer to the fifth A-figure D diagram, which is a circuit diagram of an energy level reference level circuit according to still another embodiment of the present invention. Although similar to the circuit mechanism of the third A-B diagram, this embodiment only needs one current source I and two prediction capacitors (the first prediction capacitor C _{d_1} and the second prediction capacitor C _{d_2} ), respectively in the prediction phase and amplification. The two predictive capacitors are switched in stages to store the energy level reference level voltage V _bg . Specifically, in the prediction phase, the first prediction capacitor C _{d_1 is} coupled between the negative input terminal and the output terminal of the operational amplifier 25, and is stored in the amplification phase (fifth A picture), and the output of the operational amplifier 25 is output. The energy level reference level voltage V _bg .

As shown in FIG. 5B, during the prediction phase, the second transistor Q _{2 is} not connected to the current source I. Similarly, the first processing capacitor C _f and the second processing capacitor C _s are electrically connected in parallel and coupled. a first transistor connected to _a common collector terminal of Q, to store a first transistor Q ₁ common collector terminal voltage, and the compensation capacitor C ₁ stores the operational amplifier offset voltage V _OS 25 of.

Then, when entering the amplification phase, as shown in FIG. 5C, the second processing capacitor C _s is controlled to be coupled between the common collector terminal of the second transistor Q ₂ and the first processing capacitor C _f , and first The predicted capacitance C _{d_1} and the second predicted capacitance C _{d_2 are} also switched symmetrically. Specifically, in the amplification phase, the reset second prediction capacitor C _{d_2} is electrically connected in parallel to the first processing capacitor C _f for equally dividing the amount of charge on the first processing capacitor C _f to reduce the energy level. Reference level voltage V _bg . At this time, the second prediction capacitor C _{d_2} stores the energy level reference level voltage V _bg outputted from the operational amplifier 25 as shown in the fifth D diagram. By cyclically switching the first prediction capacitor C _{d_1} and the second prediction capacitor C _{d_2} , a temperature-independent and offset-free energy level reference level voltage V _bg can be obtained.

According to the above embodiment, the low voltage energy level reference level circuit proposed by the present invention uses the correlation double sampling technique to predict and compensate the voltage offset at different times by using two sets of capacitor groups to operate at a low voltage. Then, the gain error of the low gain amplifier is corrected, so that the generated energy level reference level voltage is not only independent of temperature, but also drifts without being changed by the voltage source, thereby improving the overall efficiency of the energy level reference level circuit.

The above description is only the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention; all other equivalent changes or modifications which are not departing from the spirit of the invention should be included in the following Within the scope of the patent application.

Q ₁ ‧‧‧First transistor

Q ₂ ‧‧‧Second transistor

21‧‧‧First Capacitor Group

C _f ‧‧‧first processing capacitor

C _s ‧‧‧second processing capacitor

C _d ‧‧‧third processing capacitor

23‧‧‧Second capacitor group

C _{s_p ‧‧‧first} predicted capacitance

C _{f_p} ‧‧‧second predictive capacitance

C _{d_p} ‧‧‧third predictive capacitance

25‧‧‧Operational Amplifier

V _OS ‧‧‧ offset voltage

C ₁ ‧‧‧Compensation capacitor

V _bg ‧‧‧ energy level reference level voltage

Claims (19)

A low voltage energy level reference bitgap reference circuit, comprising: a first current source; a first transistor, wherein a common collector of the first transistor is electrically connected in series to the first current source; a second current source; a second transistor, wherein the second transistor is electrically connected in series to the second current source; an operational amplifier; a first capacitor group for a predictive phase stores a first reference voltage of the first transistor; a second capacitor group coupled to the negative input terminal of the operational amplifier during the prediction phase to generate a bias of the operational amplifier An offset voltage, wherein the offset voltage has an offset; a compensation capacitor coupled to the negative input of the operational amplifier for storing the offset during the prediction phase; and a plurality of a switch for switching between the prediction phase and an amplification phase; wherein, during the amplification phase, the compensation capacitor is coupled between the negative input terminal of the operational amplifier and the first capacitor group to cancel the offset ,and then The operational amplifier can output a precision bandgap voltage reference level. The low voltage energy level reference level circuit of claim 1, wherein the first capacitor group comprises: a first processing capacitor; and a second processing capacitor; wherein, in the prediction phase, the a processing capacitor and the second processing capacitor are electrically connected in parallel, And coupled to the common collector terminal of the first transistor to store the first reference voltage of the first transistor, and in the amplification phase, the second processing capacitor is coupled to the second transistor A common reference voltage and a first reference voltage are used to store a second reference voltage, wherein the second reference voltage is a voltage difference between the first reference voltage and a terminal voltage of the second transistor common collector. The low voltage energy level reference level circuit of claim 2, wherein the operational amplifier has an output, and in the amplification phase, the first processing capacitor is serially connected to the second processing capacitor and Between the outputs of the operational amplifier, the energy level reference level voltage is generated independently of temperature. The low voltage level reference level circuit of claim 3, wherein the first capacitor group further comprises: a third processing capacitor; wherein, in the prediction phase, the third processing capacitor is coupled The first processing capacitor is electrically connected in parallel to the first processing capacitor for reducing the energy level reference level voltage during the amplification phase. The low voltage energy level reference level circuit of claim 4 further includes a sustain capacitor coupled to the output terminal for stabilizing the output of the energy level reference level voltage. The low voltage energy level reference level circuit of claim 4, wherein, in the amplification phase, the capacitance of the first processing capacitor is a negative temperature coefficient of the first reference voltage, and the second processing The capacitance of the capacitor is the positive temperature coefficient of the second reference voltage. The low voltage energy level reference level circuit of claim 4, wherein the first capacitor group and the second capacitor group are symmetrically switched during the prediction phase and the amplification phase. The low voltage energy level reference level circuit of claim 7, wherein the second capacitor group comprises: a first prediction capacitor; a second prediction capacitor; and a third prediction capacitor; wherein, in the amplification phase, the first prediction capacitor and the second prediction capacitor are electrically connected in parallel and coupled to the first The third prediction capacitor is coupled to the predetermined potential and is reset, and the first prediction capacitor is coupled between the second transistor and the third prediction capacitor during the prediction phase. The second prediction capacitor is electrically connected in parallel to the third prediction capacitor. The low voltage energy level reference level circuit of claim 8, wherein one of the compensation capacitors is coupled to the negative input terminal of the operational amplifier and the first prediction capacitor, Between the second prediction capacitor and the negative terminal of the third prediction capacitor, and the other end of the compensation capacitor is coupled to the predetermined potential, and in the amplification phase, the compensation capacitor is coupled to the negative input of the operational amplifier And between the first processing capacitor, the second processing capacitor, and the negative terminal of the third processing capacitor. The low voltage energy level reference level circuit of claim 1, wherein the first transistor and the second transistor system have an area ratio of 1:M, wherein the M value is greater than 1. A low voltage energy level reference bitgap reference circuit comprising: a current source; a first transistor, wherein a common set of the first transistor is electrically connected in series to the current source; and a second transistor The common collector of the second transistor is electrically connected in series to the current source; an operational amplifier; a first capacitor group for storing the first transistor in a predictive phase a first reference voltage; a first prediction capacitor coupled between the negative input terminal and the output terminal of the operational amplifier during the prediction phase, for storing an energy level reference level voltage output by the operational amplifier during an amplification phase, And generating an offset voltage of the operational amplifier, wherein the offset voltage has an offset; a second prediction capacitor is coupled to a predetermined potential during the prediction phase and is a compensation capacitor coupled to the negative input of the operational amplifier for storing the offset during the prediction phase; and a plurality of switches for switching the prediction phase and the amplification phase; wherein the second The transistor is not connected to the current source during the prediction phase, and during the amplification phase, the compensation capacitor is coupled between the negative input terminal of the operational amplifier and the first capacitor group and the second prediction capacitor to The offset is offset, thereby enabling the operational amplifier to output a precise reference level reference voltage. The low voltage energy level reference level circuit of claim 11, wherein the first capacitor group comprises: a first processing capacitor; and a second processing capacitor; wherein, in the prediction phase, the a processing capacitor and the second processing capacitor are electrically connected in parallel and coupled to the common collector terminal of the first transistor to store the first reference voltage of the first transistor, and in the amplification phase, the The second processing capacitor is coupled between the common collector terminal of the second transistor and the first processing capacitor for storing a second reference voltage, wherein the second reference voltage is the first reference voltage and the first The voltage difference of the terminal voltage of the common collector of the two transistors. The low voltage energy level reference level circuit of claim 12, wherein the first processing capacitor is serially connected to the second processing capacitor and the operational amplifier when the amplification phase is Between the outputs, the temperature-independent reference level voltage is generated independently. The low voltage energy level reference level circuit of claim 13, wherein the second prediction capacitor is electrically connected in parallel to the first processing capacitor during the amplification phase to reduce the energy level reference bit. Quasi-voltage. The low voltage energy level reference level circuit of claim 14 further includes a sustain capacitor coupled to the output terminal for stabilizing the output of the energy level reference level voltage. The low voltage energy level reference level circuit according to claim 14, wherein in the amplification phase, the capacitance of the first processing capacitor is a negative temperature coefficient of the first reference voltage, and the second processing The capacitance of the capacitor is the positive temperature coefficient of the second reference voltage. The low voltage energy level reference level circuit of claim 14, wherein the first capacitor group is symmetrically switched during the prediction phase and the amplification phase, and the first prediction capacitor and the second prediction capacitor are Also switch symmetrically. The low voltage energy level reference level circuit of claim 17, wherein one of the compensation capacitors is coupled to the negative input terminal of the operational amplifier and the negative of the first prediction capacitor. And the other end of the compensation capacitor is coupled to the predetermined potential, and in the amplification phase, the compensation capacitor is coupled to the negative input terminal of the operational amplifier and the first processing capacitor, the second processing capacitor, Between the negative ends of the second prediction capacitor. The low voltage energy level reference level circuit of claim 11, wherein the first transistor and the second transistor system have an area ratio of 1:M, wherein the M value is greater than 1.