TWI452689B - Nonvolatile memory device and array thereof - Google Patents

Description

Non-volatile memory components and arrays thereof

This invention relates to an electronic component and its array, and more particularly to a non-volatile memory component and array thereof.

Recently, Resistive Random Access Memory (RRAM) has been widely used in the field of non-volatile memory technology due to its simple crossbar array architecture and low temperature process. The architecture of this crossbar array is based on the concept of resistive-switching elements, which theoretically achieves a minimum cell size of 4F ² , where F represents the feature size. ). Thus, an interleaved non-volatile memory array can have a relatively high integration density.

FIG. 1 is a conceptual diagram showing the size of the unit cell. In FIG. 1, the non-volatile memory array is composed of a plurality of bit lines BL and word lines WL, and the cross-point of the two is where the memory cells are located. The cell size of each memory cell (i.e., the area it occupies) is about 4F ² . Therefore, if the bulk density of 1 terabyte per square centimeter (1 terabyte/cm ² ) is to be achieved, the condition of F = 5 nm must be satisfied. In the prior art, if each memory cell includes a transistor structure, it is difficult to achieve such a high integrated density.

However, the above-described interleaved non-volatile memory array still has partial defects such as sneak currents. 2A is a schematic diagram showing the read state of a portion of memory cells in a theoretically non-volatile memory array. FIG. 2B is a schematic diagram showing the read state of the memory cell of FIG. 2A, which has the problem of snorkeling current. Referring to FIG. 2A and FIG. 2B, with respect to the read state of the partial memory cells illustrated in FIG. 2A, a specific read voltage is applied between the selected word line and the bit line to read the bit. value. In this example, the selected word line WL2 is applied with the read voltage Vread, and the selected bit line BL2 has a voltage value of zero. Since the selected memory cell in the lower right is in the off state, the theoretically expected read resistance should be a large resistance value, that is, a corresponding smaller read current value. However, due to the influence of the adjacent unselected memory cells being in the on state, there is actually a snorkeling current path _PSC at the time of reading. The existence of this path will cause the snorkeling current to flow along the adjacent memory cell through the word line WL2 and the bit line BL2, at which time the read current value will increase abnormally, thereby significantly reducing the read margin (read Margin), resulting in reading the wrong bit state.

The present invention provides a non-volatile memory component and an array thereof that reduces the snorkeling current therein to avoid reading an erroneous bit state.

The present invention provides a non-volatile memory device including a first electrode, a resistive structure, a diode structure, and a second electrode. The resistor structure is disposed on the first electrode and includes a first oxide layer. The first oxide layer is disposed on the first electrode. The diode structure is disposed on the resistor structure and includes a first metal layer and a second oxide layer. The first metal layer is disposed on the first oxide layer. The second oxide layer is disposed on the first metal layer. The second electrode is disposed on the diode structure. The first metal layer and the second electrode are made of different materials.

The present invention provides a non-volatile memory array comprising a memory cell array, a plurality of bit lines, and a plurality of word lines. The memory cell array includes a plurality of non-volatile memory elements. Each non-volatile memory component has a first end and a second end. Each non-volatile memory component includes a resistive structure and a diode structure, and the two are coupled in series to the first end and the second end of each non-volatile memory component in a layered manner. between. Each of the bit lines is coupled as a first electrode to a first end of the corresponding non-volatile memory element. Each word line is coupled as a second electrode to a second end of the corresponding non-volatile memory element. The non-volatile memory component is disposed at the intersection of the bit line and the word line. For each non-volatile memory component, the resistive structure includes a first oxide layer. The first oxide layer is disposed on the corresponding first electrode. The diode structure includes a first metal layer and a second oxide layer. The first metal layer is disposed on the first oxide layer. The second oxide layer is disposed on the first metal layer. A corresponding second electrode is disposed on the second oxide layer. The first metal layer and the second electrode are made of different materials.

Based on the above, in an exemplary embodiment of the present invention, the non-volatile memory component belongs to a diode-resistor (1D1R) structure, which is connected in series to the memory array in a layered manner. The intersection of the word line and the bit line to reduce the leakage current inside it.

The above described features and advantages of the present invention will be more apparent from the following description.

An exemplary embodiment of the present invention solves the problem of snorkeling current by adding a non-linear element to the memory cell and in series with its internal resistive element. The non-linear element is, for example, a unipolar diode connected in series with a unipolar resistive element to increase the degree of non-linearity of the low-resistance resistance value, the architecture of which is in an exemplary embodiment of the invention. The structure of 1D1R is taken as an illustration. In addition, in order to maintain the minimum cell size of 4F ² , the resistive element and the diode element can be vertically stacked to achieve the purpose of serial connection. Therefore, it is advantageous for application to high density non-volatile memory.

The invention is described in detail below by way of an exemplary embodiment and drawings. 3 is a schematic perspective view of a three-dimensional structure of a non-volatile memory array according to an embodiment of the invention. 4A is a schematic view showing the stack structure of the non-volatile memory element of FIG. 3. 4B is an equivalent circuit diagram of the non-volatile memory element of FIG. 4A. Referring to FIGS. 3 through 4B, the non-volatile memory array 300 includes a memory cell array, a plurality of bit lines BL1-BL3, and a plurality of word lines WL1-WL3. The memory cell array includes a plurality of non-volatile memory elements respectively disposed at the intersection of each of the bit lines and the respective word lines.

For example, the non-volatile memory element 310 located at the intersection of the bit line BL1 and the word line WL1 has a first end N1 and a second end N2 as shown in FIG. 4B. The first end N1 is an end point of the non-volatile memory element 310 connected to the bit line BL1, the bit line BL1 is the first electrode of the non-volatile memory element 310; the second end N2 is the non-volatile memory element 310 and The end of the word line WL1 is connected, and the word line WL1 serves as the second electrode of the non-volatile memory element 310. The coupling relationship between other non-volatile memory components and their bit lines and word lines can be deduced by analogy and will not be described here. Therefore, in this embodiment, the bit lines BL1-BL3 and the word lines WL1-WL3 are respectively coupled to the first end N1 and the second end N2 of the corresponding non-volatile memory element. In FIG. 3, the number of bit lines BL1-BL3, word lines WL1-WL3, and non-volatile memory elements 310 of the non-volatile memory array 300 is for illustrative purposes only, and the present invention is not limited thereto.

On the other hand, in FIG. 4A, the non-volatile memory element 310 includes a resistive structure R and a diode structure D, which are coupled in series to the non-volatile memory element 310 in a layered manner. Between the first end N1 and the second end N2. In the present embodiment, the resistor structure R includes a first oxide layer 312. The first oxide layer 312 is disposed on the bit line BL1 as the first electrode. The material of the first electrode is, for example, a metal Pt; the material of the first oxide layer 312 is, for example, one selected from the group consisting of NiO, TiO ₂ , HfO, HfO ₂ , ZrO, ZrO ₂ , Ta ₂ O ₅ , ZnO, WO ₃ , CoO and Nb ₂ O ₅ .

From another point of view, the first electrode and the resistive structure act as a resistive switching element of the non-volatile memory element 310. The first oxide layer 312 is a data storage layer of the non-volatile memory component 310.

In the present embodiment, the diode structure D is stacked on the resistor structure R, and includes a first metal layer 316 and a second oxide layer 318. The first metal layer 316 is disposed on the first oxide layer 312. The second oxide layer 318 is disposed on the first metal layer 316. The word line WL1 as the second electrode is disposed on the second oxide layer 318. It is worth mentioning that the first metal layer 316 and the second electrode are made of different materials. The material of the first metal layer 316 is, for example, metal Ti; the material of the second electrode is, for example, metal Pt; and the material of the second oxide layer 318 is, for example, one of the following oxides: NiO, HfO, HfO ₂ , ZrO ZrO ₂ , Ta ₂ O ₅ , ZnO, WO ₃ , CoO and Nb ₂ O ₅ . In addition, the resistor structure R of the embodiment further selectively includes a second metal layer 314. The second metal layer 314 is disposed on the first oxide layer 312, and the material thereof is, for example, metal Ni. The first metal layer 316 is disposed on the second metal layer 314.

From another point of view, the second electrode, the second oxide layer 318 and the first metal layer 316 form a metal-insulator-metal (MIM) diode of the non-volatile memory element 310. body. Both the second oxide layer 318 and the first metal layer 316 serve as a p-n junction of the diode for suppressing the snorkel current inside the non-volatile memory array 300, which will be described later.

The following describes how the non-volatile memory elements of the exemplary embodiments of the present invention avoid the generation of sneak currents within their arrays.

FIG. 5 is a schematic diagram showing a read state of a portion of a memory cell in a non-volatile memory array according to an embodiment of the invention. Referring to FIG. 5, the non-volatile memory array 500 of the present embodiment has a layered stack structure of memory elements as shown in FIG. 4A. In FIG. 5, each of the non-volatile memory elements located at the intersection of the word line and the bit line includes a MIM diode, which is coupled with the resistance switching element and coupled in series between the word line and the bit line. . The anodes of the diodes are coupled to respective word lines and the cathodes are coupled to respective bit lines.

In the present embodiment, the selected word line WL2 is applied with the read voltage Vread, and the selected bit line BL2 has a voltage value of zero. In the actual reading, the MIM two-pole system of the non-volatile memory element in the upper left is a unipolar diode, which can block the sneak current path existing during reading, so that the snorkel current cannot be along A memory cell adjacent to the non-volatile memory element 510 flows through the word line WL2 and the bit line BL2. Therefore, compared with the prior art, the read current value is not affected by the snorkel current, thereby preventing the erroneous bit state from being read. It should be noted that the read state of the memory cell illustrated in FIG. 5 is for illustrative purposes only, and the present invention is not limited thereto. In other read states of the non-volatile memory array, since each memory element includes a unipolar MIM diode, the principle of blocking the sneak current path can be deduced by analogy. .

In summary, in an exemplary embodiment of the present invention, the non-volatile memory array includes a memory element structure of the 1D1R, which is serially stacked in a layered manner on the word line and the bit line of the memory array. Interlaced to reduce the leakage current inside it. In addition, the resistive element and the diode element are stacked vertically, and a small cell size can be maintained.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

300. . . Non-volatile memory array

310, 510. . . Non-volatile memory component

312. . . First oxide layer

314. . . Second metal layer

316. . . First metal layer

318. . . Second oxide layer

BL, BL1, BL2, BL3. . . Bit line

WL, WL1, WL2, WL3. . . Word line

F. . . Feature size

Vread. . . Read voltage

P _SC . . . Latent current path

N1. . . First end of a non-volatile memory component

N2. . . Second end of the non-volatile memory component

R. . . Resistance structure

D. . . Dipolar structure

Figure 1 is a conceptual diagram showing the cell size of a non-volatile memory array.

2A is a schematic diagram showing the read state of a portion of memory cells in a theoretically non-volatile memory array.

2B is a schematic view showing the read state of the memory cell of FIG. 2A.

3 is a schematic perspective view of a three-dimensional structure of a non-volatile memory array according to an embodiment of the invention.

4A is a schematic view showing the stack structure of the non-volatile memory element of FIG. 3.

4B is an equivalent circuit diagram of the non-volatile memory element of FIG. 4A.

FIG. 5 is a schematic diagram showing a read state of a portion of a memory cell in a non-volatile memory array according to an embodiment of the invention.

310. . . Non-volatile memory component

312. . . First oxide layer

314. . . Second metal layer

316. . . First metal layer

318. . . Second oxide layer

BL1. . . Bit line

WL1. . . Word line

R. . . Resistance structure

D. . . Dipolar structure

Claims (8)

A non-volatile memory device includes: a first electrode; a resistor structure disposed on the first electrode, comprising: a first oxide layer disposed on the first electrode; a diode structure, configured The resistor structure includes: a first metal layer disposed on the first oxide layer; and a second oxide layer disposed on the first metal layer; and a second electrode disposed on the second electrode And the second metal layer is disposed on the first oxide layer, wherein the diode structure is The first metal layer is directly disposed on the second metal layer of the resistor structure. The non-volatile memory component of claim 1, wherein the first metal layer and the second metal layer are made of different materials. The non-volatile memory component of claim 1, wherein the first metal layer and the second metal layer are made of the same material. The non-volatile memory component of claim 1, wherein the first oxide layer serves as a data storage layer of the non-volatile memory component, and the material thereof is selected from one of the following oxides: NiO, TiO. ₂ , HfO, HfO ₂ , ZrO, ZrO ₂ , Ta ₂ O ₅ , ZnO, WO ₃ , CoO and Nb ₂ O ₅ , the material of the second oxide layer is selected from one of the following oxides: NiO, TiO ₂ , HfO, HfO ₂ , ZrO, ZrO ₂ , Ta ₂ O ₅ , ZnO, WO ₃ , CoO and Nb ₂ O ₅ . A non-volatile memory array includes: a memory cell array comprising a plurality of non-volatile memory elements, each of the non-volatile memory elements having a first end and a second end, each of the non-volatile memory The device includes a resistor structure and a diode structure, and the two are coupled in series between the first end and the second end of each non-volatile memory component in a layered manner; the plurality of bits a line, each of the bit lines being coupled as a first electrode to the first ends of the corresponding non-volatile memory elements; and a plurality of word lines, each of the word lines being a second electrode The second ends of the non-volatile memory elements are coupled to the non-volatile memory elements, wherein the non-volatile memory elements are disposed at the intersection of the bit lines and the word lines, wherein each In the non-volatile memory device, the resistor structure includes a first oxide layer disposed on the corresponding first electrode; and the diode structure includes a first metal layer and a second An oxide layer, the first metal layer is disposed on On the first oxide layer, the second oxide layer is disposed on the first metal layer, and the corresponding second electrode is disposed on the second oxide layer, wherein the first metal layer and the second electrode layer are made of different materials. In the non-volatile memory device, the resistor structure further includes a second metal layer disposed on the first oxide layer, and the first metal layer of the diode structure is directly disposed on the resistor structure. On the second metal layer. Non-volatile memory array as described in claim 5 The column, wherein for each of the non-volatile memory elements, the first metal layer and the second metal layer are made of different materials. The non-volatile memory array of claim 5, wherein for each of the non-volatile memory elements, the first metal layer and the second metal layer are made of the same material. The non-volatile memory array according to claim 5, wherein for each of the non-volatile memory elements, the first oxide layer serves as a data storage layer of the non-volatile memory element, and the material selection thereof From one of the following oxides: NiO, TiO ₂ , HfO, HfO ₂ , ZrO, ZrO ₂ , Ta ₂ O ₅ , ZnO, WO ₃ , CoO and Nb ₂ O ₅ , the material of the second oxide layer is selected from One of the following oxides: NiO, TiO ₂ , HfO, HfO ₂ , ZrO, ZrO ₂ , Ta ₂ O ₅ , ZnO, WO ₃ , CoO and Nb ₂ O ₅ .