TWI451696B - Multiplexer - Google Patents

Description

Multiplexer

The present invention relates to a multiplexer, and more particularly to a multiplexer that can respond to high speed signal multiplex switching.

The multiplexer is used to switch one of the plurality of input signals to select one of the signals as the output signal. The multiplexer is very versatile; for example, in modern electronic systems, multiple parallel signals are converted into a series of signals to reduce the hardware cost of signal transmission. When converting a plurality of parallel signals into a serial signal, the multiplexer periodically selects each of the parallel signals one by one, so that each of the data in the parallel signals is sequentially serialized in the serial output of the multiplexer. In the signal.

As the operating hours of modern electronic systems increase, so does the speed, timing, and frequency of electronic signals (such as the number of bits per unit of time). The design of the multiplexer must also be multiplexed in response to high-speed electronic signals. For example, if the multiplexer converts N parallel input signals of frequency f (ie, the duration of each metadata in each input data is 1/f) into a serial output signal, the frequency of the output signal will The multiple is increased to N*f. In other words, the multiplexer must have a good response speed to handle the increased frequency requirements.

One of the objects of the present invention is to provide a multiplexer that provides an output signal based on N input signals. In one embodiment, the multiplexer is a differential multiplexer that switches between N pairs of differential input signals D(0)/Db(0) to D(N-1)/Db(N-1) To provide a pair of differential output signals Dout / Doutb. The multiplexer is provided with N switching circuits, N differential switching circuits, an output terminal, a differential output terminal and two complementary driving units.

Each of the switching circuits dx(n) is provided with a channel unit M(n) and two switches sa(n) and sb(n). The channel unit M(n) has a first channel end and a second channel end, and can be connected to the second channel end in a channel conduction period; the first channel end is coupled to the output end. The switches sa(n) and sb(n) correspond to the input signals D(n) and D(n+1) respectively; for n=(N-1), the input signal D(n+1) is the input signal D(0). ). The switches sa(n) and sb(n) each have two transmission ends, and respectively turn on the respective two transmission ends in different switch conduction periods. A transmission end of the switch sa(n) and sb(n) is coupled to the second channel end of the channel unit M(n), and the other transmission ends of the switches sa(n) and sb(n) are respectively coupled to the corresponding input signals. D(n) and D(n+1). The switch conduction period of the switch sa(n) partially overlaps with the channel conduction period of the channel unit M(n), and the switch conduction period of the switch sb(n) is also related to the channel conduction period of the channel unit M(n). Overlap, but the switch-on period of the switch sa(n) does not overlap with the switch-on period of the switch sb(n).

After the multiplexer operation of the multiplexer, the output signal has a plurality of output data of one bit, and each output data corresponds to one bit period. In one embodiment, the channel conduction period of the channel unit M(n) and the switching duration of each of the switches sa(n) and sb(n) are equivalent to twice the period of the bit period, and the switch conduction period and the channel are turned on. The time when the time period partially overlaps is equivalent to the bit time period. Each one-bit input data in each input signal corresponds to N bit periods.

In one embodiment, the channel unit M(n) further has a controlled terminal that receives a channel clock; the channel clock periodically alternates between the first level and the second level, and the channel clock is maintained at the first The time period of the level corresponds to the channel conduction period. Each of the switches sa(n) and sb(n) further has a switching terminal for receiving a corresponding switching clock. The switching clock periodically alternates between the third level and the fourth level (the third and fourth levels can be equal to the first and second levels, respectively); when the switch corresponding to each switch is maintained at the third level The level, that is, the switch on period of each switch.

The switching clock of the switch sa(n), the channel clock of the channel unit M(n) and the switching clock of the switch sb(n) can be the clocks CK(n-1), CK(n) and CK(n, respectively. +1). For example, the period of the clock CK(n) is N bit periods, starting at the 0th bit period and ending at the (N-1)th bit period, and at the pth of each period The first level is maintained in the qth bit period; where p and q are the remainder of n and (n+1) divided by N, respectively. That is to say, the clocks CK(n-1), CK(n) and CK(n+1) have the same period but different phases. For n=0, the clock CK(n-1) is the clock CK(N-1); for n=(N-1), the clock CK(n+1) is the clock CK(0).

Through the above clock arrangement, for the switching circuit dx(n), the channel unit M(n) turns on the switch sa(n) to the output according to the clock CK(n), and the switch sa(n) depends on the clock. CK(n-1) turns on the input signal D(n) to the channel unit M(n). For the switching circuit dx(n-1), the channel unit M(n-1) turns on the switch sb(n-1) to the output according to the clock CK(n-1), and the switch sb(n-1) The input signal D(n) is turned on to the channel unit M(n-1) according to the clock CK(n). That is, the channel conduction period of the switching circuit dx(n-1) corresponds to the switching conduction period of the switch sa(n) in the switching circuit dx(n), and the channel conduction period of the switching circuit dx(n) is equivalent to the switching circuit The switch on period of the switch sb(n-1) in dx(n-1). For n=0, the switching circuit dx(n-1) is the switching circuit dx(N-1).

Therefore, in a one-bit period in which the clock CK(n-1) and the clock CK(n) partially overlap, the input signal D(n) is transmitted to the output via two paths, one of which is the switch sb ( N-1) to the channel unit M(n-1), and the other path is the switch sa(n) to the channel unit M(n). The equivalent impedances (resistances) of the two paths are parallel to each other to a low impedance to reduce the transmission delay and improve the response speed of the multiplexer of the present invention. Furthermore, before the one-dimensional period in which the clock CK(n-1) and the clock CK(n) partially overlap, one of the switches sa(n) and sb(n-1) first inputs the signal. D(n) is transmitted to the corresponding channel unit, and the corresponding channel unit is pre-charged, so that the path of the switch and the corresponding channel unit can respond to the content of the input signal D(n) in advance, and the multiplexer high-speed signal of the invention is also enhanced. Performance of multiplex switching. In addition, the channel conduction period in which each channel unit M(n) is turned on is twice the bit period, and the channel conduction period is not required to be compressed into a single bit period.

Based on the symmetric configuration of the differential configuration, each switching circuit dx(n) corresponds to a differential switching circuit dxb(n). The differential switching circuit dxb(n) is provided with a channel unit Mb(n) and two switches sc(n) and sd(n). The channel unit Mb(n) has two channel ends, one of which is coupled to the differential output, the other is coupled to the switches sc(n) and sd(n); the channel unit Mb(n) is based on the clock CK(n) ) and turn on the two channel ends. The switch sc(n) turns on the inverted signal Db(n) of the input signal D(n) to the channel unit Mb(n) according to the clock CK(n-1), and the switch sd(n) is based on the clock CK(n). +1) turns on the inverted signal Db(n+1) of the input signal D(n+1) to the channel unit Mb(n).

In one embodiment, each channel unit M(n), Mb(n) of the multiplexer can be implemented by a transistor of the same channel type, such as a gold oxide half field effect transistor. The two complementary drive units can be implemented with complementary channel type gold oxide half field effect transistors. The controlled end of each channel unit M(n), Mb(n) may be the gate of the transistor, and the two ends are the source and the drain, respectively. Each of the complementary driving units has a controlled end (such as a gate) and a channel end (such as a drain); wherein the controlled end and the channel end of a complementary driving unit are respectively coupled to the output end and the differential output end, and the other complements The controlled end and the channel end of the driving unit are respectively coupled to the differential output end and the output end. The other channel end (such as the source) of each complementary driving unit is coupled to the operating voltage. Since the multiplexer of the present invention adopts a complementary transistor pair structure, the power consumption can be reduced, and the swing range of the output signal is also wide, which can be consistent with the swing range of the input signal without being reduced.

The above and other objects, features and advantages of the present invention will become more <RTIgt;

Please refer to FIG. 1 and FIG. 2, FIG. 1 illustrates a multiplexer 10, and FIG. 2 illustrates the waveform timing of each associated signal clock in the multiplexer 10. The multiplexer 10 is a differential multiplexer that provides a pair of differentials at nodes Np and Npb according to 10 pairs of differential input signals Di(0)/Dib(0) to Di(9)/Dib(9), respectively. The output signal Do/Dob; each pair of differential input signals Di(n) and Dib(n) are mutually inverted (n=0 to 9), and the output signals Do and Dob are also mutually inverted.

Based on the differential symmetric architecture, the multiplexer 10 is provided with two matching resistors RL and RLb, and gates A(0) to A(9), Ab(0) to Ab(9), and a transistor (such as an n-channel). Gold oxide half field effect transistors) Mi(0) to Mi(9), Mib(0) to Mib(9), and a current source IMUX for supplying current. For n=0 to 9, each gate A(n) receives the input signal Di(n) and two clocks to determine whether the input signal Di(n) can be transmitted to the transistor Mi according to the two clocks ( The gate of n); the drain and source of the transistor Mi(n) are coupled to the nodes Npb and Np1, respectively. Corresponding to the configuration of the gate A(n), the gate Ab(n) also determines whether the inverted signal Dib(n) of the input signal Di(n) can be transmitted to the transistor Mib(n) according to the two clocks. The gate; and the gate Ab(n) and the gate A(n) are based on the same two clocks. The drain and source of the transistor Mib(n) are coupled to the nodes Np and Np1, respectively. The resistor RLb is a load of the transistor Mi(n) coupled between the operating voltage Vdd and the node Npb. The resistor RL is a load of the transistor Mib(n) coupled between the operating voltage Vdd and the node Np.

Each of the gates A(0) to A(9) and Ab(0) to Ab(9) can be respectively according to the clocks CLK(0) to CLK(4) in FIG. 2 and the inverted clock CLKb (0). ) to CLKb (4) to determine whether the corresponding input signals Di(0) to Di(9), Dib(n) to Dib(9) are supplied to the corresponding transistors Mi(0) to Mi(9), Mib(0) to Mib(9); each clock CLK(m) and CLKb(m) (m=0 to 4) are mutually inverted, and the period Ti_p corresponds to a single bit in the input data Di(n) Meta input data Di(n)_k. For example, the gate A(0) is clocked by the clocks CLK(0) and CLKb(1) and the input signal Di(0); the clocks CLK(0) and CLKb(1) are both logic highs. On time, the gate A(0) will transmit the input signal Di(0) to the gate of the transistor Mi(0).

The operation of the multiplexer 10 can be described as follows. At the same time, CLK(0) and CLKb(1) are both high level 1 of logic 1, and gates A(0) and Ab(0) respectively transmit input signals Di(0) and Di(0) to transistor Mi(0). And the gate of Mib(0); if the input data Di(0)_k of the input signal Di(0) is logic 1, the transistor Mi(0) conducts current and causes the voltage of the node Npb to drop, and the output of the node Npb The signal Dob outputs a logic 0; the transistor Mib(0) is turned off, and the voltage of the node Np is maintained at the operating voltage Vdd to provide a logic 1 in the output signal Do of the node Np. Similarly, when the CLK(1) and CLKb(2) are both high level 1 of logic 1, and the gates A(1), Ab(1) and the transistors Mi(1) and Mib(1) will input signals. The input data Di(1)_k of Di(1) is serially connected to the output signal Do. As shown in Fig. 2, in a period of Ti_p, the input data Di(0)_k to Di(9)_k in the input signals Di(0) to Di(9) are sequentially ordered according to the timing of each clock. It is switched to the output signal Do. In the output signal Do, each input data Di(n)_k is maintained for one bit period Tp, and the bit period Tp is one tenth of the period Ti_p.

It can be seen from the above discussion that in each period Ti_p, each gate A(n) will conduct the corresponding input data Di(n) to the corresponding transistor Mi(n) in one bit period Tp, in the remaining The input data Di(n) is blocked in the 9-bit period Tp. That is to say, the transistor Mi(n) must quickly decide whether to turn on the node Npb to the current source IMUX according to the input data Di(n) at the beginning of the one-bit period Tp, and quickly at the end of the 1-bit period Tp. The gate is divided by the input data Di(n). Since the on-response of the transistor Mi(n) is compressed into one bit period, the response speed of the transistor Mi(n) becomes one of the operational bottlenecks of the multiplexer 10; the multiplexer 10 is due to the transistor Mi ( The conduction response of n) is not fast enough to function properly.

In addition, since the multiplexer 10 is a current-driven architecture, the amplitude of the signal swing of the output signal Do/Dob is reduced, and cannot be consistent with the degree of swing of each input signal Di(n)/Dib(n). The input signal Di(n)/Dib(n) can be represented as a logic 0 by the operating voltage Vss; in contrast, since the multiplexer 10 uses the current source IMUX, the output signal Do/Dob cannot present a logic 0 with the voltage Vss. The low voltage, in conjunction with the noise margin of the multiplexer 10. Moreover, since the multiplexer 10 uses the current to establish a voltage across the resistor RL/RLb to present a logic 0, the power is continuously consumed, so that the operating power required by the multiplexer 10 cannot be effectively reduced.

Please refer to FIG. 3 and FIG. 4; FIG. 3 illustrates a multiplexer 20 according to an embodiment of the present invention, and FIG. 4 illustrates waveform timings of associated signals and clocks in the multiplexer 20. The multiplexer of the present invention may be a N-to-1 differential multiplexer, based on N pairs of differential input signals D(0)/Db(0) to D(N-1)/Db(N-1). The two outputs of nodes N2 and N2p provide a pair of differential output signals Dout/Doutb; and FIGS. 3 and 4 illustrate a embodiment of the present invention with a 4 to 1 multiplexer 20, ie, N=4 . The multiplexer 20 is provided with N switching circuits dx(0) to dx(N-1), N differential switching circuits dxb(0) to dxb(N-1), and two complementary driving units Mu1 and Mu2.

Each of the switching circuits dx(n) is provided with a channel unit M(n) and two switches sa(n) and sb(n). The channel unit M(n) can be realized by an n-channel gold oxide half field effect transistor, and the gate, the drain and the source can be regarded as a controlled end and two channel ends respectively; the controlled end receives the clock CK ( n) As its channel clock, one of the two channel ends is coupled to node N2, and the other channel end is coupled to node na(n). As shown in Fig. 2, each clock CK(n) periodically alternates between levels H and L according to the period Ti; when the clock CK(n) is maintained at the level H, the channel unit M(n) will The node na(n) is turned on to the node N2. When the current pulse CK(n) is the level L, the channel unit M(n) stops conduction between the node na(n) and the node N2. That is to say, the period in which the clock CK(n) is the level H is the channel conduction period of the channel unit M(n).

In the switching circuit dx(n) of this embodiment, the switches sa(n) and sb(n) correspond to the input signals D(n) and D(n+1), respectively. The switch sa(n) has a switching end and two transmitting ends, and the switching end receives the clock CK(n-1), and the two transmitting ends are respectively coupled with the input signal D(n) and the node na(n). When the current pulse CK(n-1) is the level H, the switch sa(n) turns on/transmits the input signal D(n) to the node na(n); when the current pulse CK(n-1) is the level L, The switch sa(n) stops turning on the input signal D(n) to the node na(n). The switch sb(n) also has a switching end and two transmitting ends, and the switching end receives the clock CK(n+1), and the two transmitting ends are respectively coupled with the input signal D(n+1) and the node na(n). When the current pulse CK(n+1) is the level H, the switch sb(n) turns on the input signal D(n+1) to the node na(n); relatively, the current pulse CK(n+1) is the level When L, the switch sb(n) no longer turns on the input signal D(n+1) to the node na(n). That is to say, the period when the clock CK(n-1) is the level H is the switch conduction period of the switch sa(n), and the period when the clock CK(n+1) is the level H is the switch sb(n). Switch on period. For n=(N-1), the input signal D(n+1) is the input signal D(0), the clock CK(n+1) is the clock CK(0); for n=0, the input signal D (n-1) is the input signal D(N-1), and the clock CK(n-1) is the clock CK(N-1).

As shown in FIG. 4, in a period Ti between time points t0 and t4, the input signals D(0) to D(3) are synchronously corresponding to the input data D(0)_k to D of one bit, respectively. (3) _k. The second period Ti at the time point t4 corresponds to the second input data D(0)_(k+1) to D(3)_(k+1) of the input signals D(0) to D(3). Correspondingly, each clock CK(n) has a period Ti, and each period Ti has N bit periods Tb; for example, each period Ti of each clock CK(n) starts at the 0th bit period Tb Ending at the (N-1)th bit period Tb, and maintaining the level H in the pth and qth bit periods of each period Ti, and the remaining time being the level L; wherein, p And q are the remainder of n and (n+1) divided by N, respectively. For example, the clock CK(0) is maintained at the level H in the 0th and 1st bit period Tb of the time point t0 to t2, and the time CK(1) is the first time at the time point t1 to t3. The second bit period Tb is the level H, and the period of the clock CK(0) at the level H and the period of the clock CK(2) at the level H do not overlap each other. In this example, the two The high and low levels are complementary, that is, CK(0) is maintained at the level H, while CK(2) is maintained at level L. By analogy, the clock CK(N-1) (the clock CK(3) in Fig. 4) will be at the (N-1)th bit period Tb and the time point t0 to t1 at the time point t3 to t4. The level H in the 0 bit period Tb is the level H.

That is to say, the period length (frequency) of each clock CK(n) is the same but the phase is different; the period of the clock CK(n-1) and the clock CK(n) maintained at the level H partially overlaps. The partially overlapping period is 1 bit period Tb. The periods of the level CK(n-1) and the level CK of CK(n+1) do not overlap each other.

Based on the symmetric configuration of the differential configuration, each switching circuit dx(n) corresponds to the differential switching circuit dxb(n). The differential switching circuit dxb(n) is provided with a channel unit Mb(n) and two switches sc(n) and sd(n). The channel unit Mb(n) is matched with the channel unit M(n), and can be realized by an n-type channel MOS field effect transistor; the source of the channel unit Mb(n) and the 汲 are two channel ends, one of which is coupled The differential output of node N2b, and the other node nb(n) are coupled to switches sc(n) and sd(n). The channel unit Mb(n) controls conduction between the nodes nb(n) and N2b according to the clock CK(n) received by the gate. Similar to the timing of the switch sa(n), the switch sc(n) turns on the inverted signal Db(n) of the input signal D(n) to the channel unit Mb of the node nb(n) according to the clock CK(n-1). (n). Similarly, similar to the timing of the switch sb(n), the switch sd(n) turns on the inverted signal Db(n+1) of the input signal D(n+1) to the node nb according to the clock CK(n+1). (n).

Corresponding to the channel elements M(n) and Mb(n) realized by the n-channel gold oxide half field effect transistor, the two complementary driving units Mu1 and Mu2 can be realized by the p-channel gold oxide half field effect transistor of the complementary channel type. . The gate (controlled end), the drain and the source (two-channel end) of the complementary driving unit Mu1 are respectively coupled to the nodes N2b, N2 and the operating voltage Vdd (such as the voltage of the level H); the gate of the complementary driving unit Mu2 The drain and the source are coupled to the nodes N2 and N2b and the operating voltage Vdd, respectively.

The operation of the multiplexer 20 can be illustrated by taking FIG. 5 and FIG. 6 as an example; please refer to FIG. 4 together. At time t0 to t1, the clocks CK(0) and CK(3) are level H, so the operation of the multiplexer 20 is as shown in Fig. 5: the channel unit M (0 in the switching circuit dx(0) ) is turned on with the switch sa(0), so that the input signal D(0) is transmitted to the node N2. At the same time, the channel unit M(3) of the switching circuit dx(3) and the switch sb(3) are also turned on, and the input signal D(0) can also be transmitted to the node N2. That is to say, the input signal D(0) will be transmitted to the output of the node N2 by two parallel paths, one path from the switch sa(0) to the channel unit M(0), and the other path from the switch sb(3) to Channel unit M (3). The channel units M(1) and M(2) in the other switching circuits dx(1) and dx(2) are not turned on, and the input signals D(1) to D(3) are isolated from the node N2. outer.

In the symmetric case of the differential configuration, the input signal Db(0), which is inverted from the input signal D(0), is Db(0)= It will also be transmitted to the differential output of node N2b via two paths. One of the paths is from the switch sc(0) to the channel unit Mb(0) in the switching circuit dxb(0), and the other path is the switch sd(3) to the channel unit Mb(3) in the switching circuit dxb(3) .

Between the time points t0 and t1, assuming that the input signal D(0) is a high level logic 1, the differential input signal Db(0) will be a low level logic zero. The input signal Db(0), which is turned on to the node N2b, turns on the complementary driving unit Mu1, and raises the node N2 to a high level logic 1 (that is, the level of the operating voltage Vdd), so that the output signal Dout of the node N2 follows the input. Signal D (0) becomes logic 1. The complementary driving unit Mu2 is not turned on, so that the differential output signal Doutb of the node N2b is logic 0 like the input signal Db(0). That is to say, in the interval t0 to t1, the input data D(0)_k of the input signal D(0) is serially outputted to the output signal Dout to form a one-bit output data corresponding to one bit period. Tb.

Next, between time points t1 and t2, the clocks CK(0) and CK(1) are simultaneously level H, and the operation of the multiplexer 20 is as shown in FIG. 6: in the switching circuit dx(0) The switch sb(0) is turned on to form a path with the channel unit M(0), and the input signal D(1) is transmitted to the node N2. At the same time, the switch sa(1) and the channel unit M(1) in the switching circuit dx(1) are also turned on to form another path, and the metadata of the input signal D(1) can also be transmitted to the node N2. That is to say, the signal D(1) is also transmitted to the node N2 via the dual path. Symmetrically, the signal Db is input via the switch sd(0) and the channel unit Mb(0) in the switching circuit dxb(0), and the switch sc(1) and the channel unit Mb(1) in the switching circuit dxb(1). (1) Also transmitted to the node N2b by the dual path. Thus, during the time interval t1 to t2, the differential input signals D(1) and Db(1) are respectively corresponding to the differential output signals Dout and Doutb, so that the next output data in the output signal Dout is reflected. Enter the one-bit input data D(1)_k in signal D(1).

Similar to the operation of FIG. 5 and FIG. 6, between time points t2 and t3, the input signal D(2) is also transmitted to the node N2 by the dual path, which is respectively switched by the switch in the switching circuit dx(1). Sb(1) to channel unit M(1), switch sa(2) in switching circuit dx(2) to channel unit M(2); symmetrically, differential input signal Db(2) is also switched sd (1) The dual path to the channel unit Mb(1), the switch sc(2) to the channel unit Mb(2) is transmitted to the node N2b. Similarly, between time t3 and t4, the dual path from switch sb(2) to channel unit M(2), switch sa(3) to channel unit M(3) will transmit input signal D(3) to the node. N2; the dual path of the switch sd(2) to the channel unit Mb(2), the switch sc(3) to the channel unit Mb(3) transmits the differential input signal Db(3) to the node N2b.

As shown in Fig. 4, in the period Ti between the time points t0 and t4, the input bit data D(0)_k to D(3)_k in the input signals D(0) to D(3) are always available. The timing changes of the pulses CK(0) to CK(3) are sequentially serialized as four output data in the output signal Dout. In the next cycle Ti after the time point t4, the input signals D(0) to D(3) are synchronously transferred to the next input data D(0)_(k+1) to D(3)_(k+1). The clocks CK(0) to CK(3) repeat the timing in the previous period Ti, so that the multiplexer 20 can input the data D(0)_(k+1) to D(3)_ for each pen. (k+1) is serialized as the next 4 output data in the output signal Dout.

Through the dual path design in the multiplexer 20 of the present invention, the impedance (resistance) encountered when the input signal is transmitted in the switching mechanism is reduced by the parallel connection of the dual paths, so that the response speed of the multiplexer 20 of the present invention can be doubled. The multiplexer 20 is sufficient to cope with the speed requirements of high speed signal multiplexing. Figure 6 also shows the equivalent circuit of the dual path; the input signal D (1) is transmitted via the dual path of the channel unit M (0) to the switch sb (0), the channel unit M (1) to the switch sa (1) To node N2, the on-resistance of channel elements M(0), M(1) is equivalent to resistance Rm, the on-resistance of switches sb(0) and sa(1) is equivalent to resistance Rs, and the output load of node N2 is Equivalent to the capacitor Cout. If the input signal D(0) can only be transmitted from a single path to node N2, the time constant of a single transmission path will be Cout*(Rs+Rm). However, in the dual path arrangement of the multiplexer of the present invention, since the resistance of each path becomes (Rs+Rm)/2 in parallel, the response time constant of the input signal D(1) transmitted to the node N2 is halved. Cout*(Rs+Rm)/2 represents the multiplication speed of the multiplexer 20.

Furthermore, one of the paths of the aforementioned dual path is precharged to further speed up the response of the multiplexer 20. Taking Fig. 6 as an example, in the example of Fig. 6, signal D(1) will pass through switch sb(0) to channel unit M(0), switch sa between time points t1 to t2 (Fig. 4). (1) The dual path to the channel unit M(1) is transmitted to the node N2. However, before the time point t1, the switch sa(1) controlled by the clock CK(0) has turned on the input signal D(1) to the node na of the channel unit M(1) at the time point t0 to t1 ( 1), that is, pre-charging the node na(1) according to the data of the input signal D(1) in the time point t0 to t1 before the time point t1 to t2, so that the input signal D(1) can be at the time point t0 to The t1 is pre-reacted to the node na(1). When the time point t1 is reached, the channel unit M(1) starts to conduct the node na(1) to the node N2, and the input signal D(1) which has been previously reacted to the node na(1) can be quickly responded to the output of the node N2. Signal Dout. Similarly, the switch sc(1) also pre-charges the node nb(1) according to the input data Db(1).

Further, in the multiplexer 20 of the present invention, since the channel conduction period of each channel unit M(n) and Mb(n) in each period Ti is 2 bit periods Tb (immediate pulse CK(n) When the level H is maintained, the conduction response of the channel elements M(n), Mb(n) does not have to be compressed to one bit period as in the transistors Mi(n) and Mib(n) in FIG. Within Tb. This also makes it easier for the multiplexer of the present invention to meet the needs of high speed signal multiplexing.

In addition, since the multiplexer of the present invention uses the architecture of the complementary transistor pair in the configuration of each channel unit M(n), Mb(n) and the two complementary driving units Mu1 and Mu2, the work of the multiplexer of the present invention can be reduced. Consumption. Because the architecture of the complementary transistor pair consumes only transient power when switching the output data, it only consumes very low static power while maintaining the steady state level of the output data. Moreover, under the structure of the complementary transistor pair, the amplitude of the signal swing of the output signals Dout and Doutb can also be consistent with the amplitude of the swing of each of the input signals D(n) and Db(n).

The multiplexer 20 of the present invention can be generalized to the multiplexer 30 in FIG. 7; the multiplexer 30 is an N-to-1 differential multiplexer having N switching circuits dx(0) to dx(N-1) ), N differential switching circuits dxb(0) to dxb(N-1), and two complementary driving units Mu1 and Mu2; multiplexer 30 according to N pairs of differential input signals D(0)/Db(0 ) to D(N-1)/Db(N-1) and provide a pair of differential output signals Dout/Doutb at the two outputs of nodes N2 and N2b. The waveform timing of the relevant signal clock when the multiplexer 30 is operating is shown in FIG. 8; wherein each bit input data D(n)_k (n=0 to N-) in each input signal D(n) 1) Corresponds to a period of Ti. The multiplexer 30 operates according to the clocks CK(0) to CK(N-1), and divides N bit periods Tb in each period Ti to be in the N bit period Tb of the output signal Dout. The sequence input data D(0)_k to D(N-1)_k.

Each of the clocks CK(0) to CK(N-1) has a period Ti. In one embodiment, each clock CK(n) starts at the 0th bit period Tb in each period Ti, ends at the (N-1)th bit period Tb, and is in each period Ti The level H is maintained in the pth and qth bit periods; wherein p and q are the remainder of n and (n+1) divided by N, respectively, n=0 to (N-1).

The complementary driving units Mu1 and Mu2 respectively have two channel ends and one controlled terminal; the controlled end and the two channel ends of the complementary driving unit Mu1 are respectively coupled to the nodes N2b, N0 and N2, and the controlled end and the two channels of the complementary driving unit Mu2 The ends are respectively coupled to nodes N2, N0 and N2b. The node N0 is coupled to the operating voltage Vdd (such as the voltage of the level H).

For n=0 to (N-1), each switching circuit dx(n) is provided with a channel unit M(n) and two switches sa(n) and sb(n); the channel unit M(n) is coupled to the node. Between na(n) and node N2. Based on the symmetric configuration of the differential configuration, each of the differential switching circuits dxb(n) is provided with a channel unit Mb(n) and two switches sc(n) and sd(n); the channel unit Mb(n) is coupled to the node. Between nb(n) and node N2b. When the current pulse CK(n) is the level H, the channel unit M(n) turns on the node na(n) to the node N2, and the channel unit Mb(n) turns on the node nb(n) to the node N2b. When the clock CK(n) is the level L, the channel unit M(n) stops turning on the node na(n) to the node N2, and the channel unit Mb(n) also stops the node nb(n) from being turned on to the node N2b.

For n=0, the switches sa(0) and sb(0) of the switching circuit dx(0) respectively input the signal D(0 according to the period of the level H of the clocks CK(N-1) and CK(1), respectively. And D(1) is turned on to node na(0). For n=1 to (N-2), the switches sa(n) and sb(n) of the switching circuit dx(n) input the signal D according to the clocks CK(n-1) and CK(n+1), respectively. (n) and D(n+1) are transmitted to the node na(n). For n=(N-1), the switches sa(N-1) and sb(N-1) of the switching circuit dx(N-1) are input according to the clocks CK(N-2) and CK(0), respectively. Signals D(N-1) and D(0) are transmitted to node na(N-1). Symmetrically, the switches sc(0) and sd(0) of the switching circuit dxb(0) conduct the input signals Db(0) and Db(1) according to the clocks CK(N-1) and CK(1), respectively. Node nb(0); switches sc(N-1) and sd(N-1) of switching circuit dxb(N-1) input signal Db according to clocks CK(N-2) and CK(0), respectively (N-1) and Db(0) are transmitted to the node nb(N-1). For n=1 to (N-2), the switches sc(n) and sd(n) of the switching circuit dxb(n) input the input signal Db according to the clocks CK(n-1) and CK(n+1), respectively. (n) and Db(n+1) are transmitted to the node nb(n).

Through the clock arrangement described above, each input signal D(0) to D(N-1), Db(0) to Db(N-1) are respectively transmitted to the node in a dual path in the corresponding bit period Tb. N2 and N2b. When the current pulse CK(0) and CK(N-1) are both level H, the switch sa(0) to the channel unit M(0), the switch sb(N-1) to the channel unit M(N-1) will The input signal D(0) is transmitted to the node N2 in a dual path; the inverting input signal Db(0) is transmitted to the channel unit Mb via the switch sc(0) to the channel unit Mb(0) and the switch sd(N-1) ( The double path of N-1) is turned on to the node N2b. For n=1 to (N-1), when the clocks CK(n-1) and CK(n) are both level H, the switch sa(n) to the channel unit M(n), the switch sb(n-1) The dual path to the channel unit M(n-1) transmits the input signal D(n) to the node N2; the switch sc(n) to the channel unit Mb(n), the switch sd(n-1) to the channel unit Mb The dual path of (n-1) transmits the input signal Db(n) to node N2b.

The equivalent impedance (resistance) of the dual path is paralleled to each other as a low impedance path to reduce the transmission delay and improve the response speed of the multiplexer of the present invention. As shown in FIG. 7, when the multiplexer 30 inputs the signal D by the dual path of the switch sb(n-1) to the channel unit M(n-1), the switch sa(n) to the channel unit M(n) ( n) When transmitting to the equivalent load capacitance Cout of node N2, the equivalent resistance Rm+Rs of a single path (the on-resistance of the channel unit and the switch, respectively) will be paralleled to (Rm+Rs)/2 in the dual path configuration. The input signal D(n) can be turned on to the node N2 via a transmission path halved by the total resistance. Furthermore, before the clock CK(n-1) and the clock CK(n) are both level H, the switch sa(n) first transmits the input signal D(n) to the corresponding channel unit M(n). And pre-charging it further enhances the performance of the multiplexer 30 in high-speed signal multiplexing switching.

For comparison with the dual path design of the multiplexer 30, please refer to the multiplexer 40 in FIG. 9; the multiplexer 40 is also an N-to-1 differential multiplexer, based on the N-pair differential input signal D ( 0) / Db (0) to D (N-1) / Db (N-1) and a pair of differential output signals Dout / Doutb are provided at nodes N2 and N2b. The multiplexer 40 includes N switching circuits sx(0) to sx(N-1), N differential switching circuits sxb(0) to sxb(N-1), and two complementary driving units Mu1 and Mu2. The associated signal and clock of the multiplexer 40 are the same as those shown in FIG. 8. The multiplexer 40 also operates according to the clocks CK(0) to CK(N-1) to N bits in the period Ti. In the meta-period, the input data D(0)_k to D(N-1)_k are sequentially serialized to the output signal Dout.

A channel unit M(n) and a switch sa(n) are provided in each switching circuit sx(n) of the multiplexer 40; the channel unit M(n) controls the conduction of the switch sa(n) to the node N2, and the switch sa (n) Controlling the conduction of the input signal D(n) to the channel unit M(n). Symmetrically, the differential switching circuit sxb(n) has a channel unit Mb(n) and a switch sb(n) corresponding to the input signal Db(n). For n=1 to (N-1), each channel unit M(n) and Mb(n) are turned on when the clock CK(n) is at level H, and the switches sa(n) and sb(n) are at the clock. When CK(n-1) is at level H, it is turned on. For n=0, the channel elements M(0) and Mb(0) are turned on when the clock CK(0) is at the level H, and the switches sa(0) and sb(0) are at the clock CK(N-1). Conducted at level H.

Under the above clock arrangement, when the current pulse CK(n-1) and the clock CK(n) are both level H, the input signal D(n) will pass through the channel unit M(n) to the switch sa(n). A single path is turned on to node N2. That is to say, the input signal D(n) is transmitted to the equivalent load capacitance Cout of the node N2 via the on-resistance (Rm+Rs) of the channel unit M(n) and the switch sa(n), so the input signal D(n) The delay available to the node N2 is represented by a time constant (Rm + Rs) * Cout. In contrast, the dual path design of the multiplexer 30 of FIG. 7 can halve the time constant to (Rm+Rs)*Cout/2, making the multiplexer 30 faster and more suitable for high speed signal multiplexing. Switch application.

Comparing the multiplexer 40 of FIG. 9 with the multiplexer 30 of FIG. 7, it can be seen that in the same period Ti, since the channel unit M(n) only needs to transmit the input signal D(n) in one bit period Tb, The multiplexer 30 can utilize the channel unit M(n) to transmit another input signal D(n+1) in another bit period Tb. In this way, each input signal D(n) can be allocated to two channel units M(n-1) and M(n) to form a dual path, which improves the speed and performance of the multiplexer 30. If the layout area of the channel unit M(n) is Am, and the layout area of each switch sa(n) or sb(n) is As, the required layout area of each single path in the multiplexer 40 is Am+2As (≒2Am) ). In contrast, the single path total layout area of the multiplexer 30 is Am+2As (≒3Am), but its time constant (delay) is half of a single path, considering that the multiplexer 30 has twice the output rate (unit time) In the case of the number of bits that can be transmitted in the middle, the total layout area of the multiplexer 30 is 3 Am*N, and the total layout area of the multiplexer 40 is 2 Am*N. In other words, in the case where the output rate is the same, the layout area used by the multiplexer 30 only needs to be half of 3Am*N, which is smaller than the area 2Am*N of the multiplexer 40; that is, the multiplexer 30 can perform better than multiplexer 40 in each unit area.

In the multiplexer 30 of Fig. 7, each channel unit M(n), Mb(n) can be realized by an n-channel gold oxide half field effect transistor, and the complementary driving units Mu1, Mu2 can use a p-type channel gold oxygen half field. The utility model realizes that each switch sa(n), sb(n), sc(n) to sd(n) can be realized by an n-type channel MOS half-field effect transistor, and a complementary MOS half-field effect transistor pair can also be used (such as Transfer gate) to achieve.

Based on the complementary duality, the multiplexer 30 can derive another embodiment. Please refer to FIG. 10 and FIG. 11; FIG. 10 illustrates a multiplexer 50 according to another embodiment of the present invention, and FIG. 11 is a diagram showing timings of related data and clocks when the multiplexer 50 operates. The multiplexer 50 is an N-to-1 differential multiplexer, based on N differential input signals D(0)/Db(0) to D(N-1)/Db(N-1) at node N2 and The two outputs of N2b provide a pair of differential output signals Dout/Doutb. The input signals D(0) to D(N-1) are synchronized with each other, and one bit input data D(0)_k to D(N-1)_k in each input signal corresponds to one period Ti. The multiplexer 50 sequentially inputs the input data D(0)_k to D(N-1) in the N bit periods Tb of the period Ti according to the clocks CKb(0) to CKb(N-1). _k is serialized into the output data Dout. Each of the clocks CKb(0) to CKb(N-1) has a period Ti; in one embodiment, the clock CK(n) starts at the 0th bit period Tb and ends at the (N-1)th bit The period Tb, and maintains the level L in the pth and qth bit periods in each period Ti, and the remaining periods are the level H; wherein p and q are respectively n and (n+1) divided by The remainder of N, n=0 to (N-1).

The multiplexer 50 is provided with complementary drive units Md1 and Md2, N switching circuits px(0) to px(N-1), and N differential switching circuits pxb(0) to pxb(N-1). The complementary driving units Md1 and Md2 (for example, implemented by an n-channel gold oxide half field effect transistor) have a controlled terminal (such as a gate) and two channel ends (such as a source and a drain), respectively. The controlled end and the two-channel end of the complementary driving unit Md1 are respectively coupled to the nodes N2b, N0 and N2, and the controlled end and the two-channel end of the complementary driving unit Md2 are respectively coupled to the nodes N2, N0 and N2b. The node N0 is coupled to the operating voltage Vss (such as the voltage of the level L).

For n=0 to (N-1), each switching circuit px(n) is provided with a channel unit P(n) and two switches xa(n) and xb(n); the channel unit P(n) is coupled to the node. Between na(n) and node N2. Based on the symmetric configuration of the differential configuration, each of the differential switching circuits pxb(n) is provided with a channel unit Pb(n) and two switches xc(n) and xd(n); the channel unit Pb(n) is coupled to the node. Between nb(n) and node N2b. When the current clock CKb(n) is the level L, the channel unit P(n) turns on the node na(n) to the node N2, and the channel unit Pb(n) turns on the node nb(n) to the node N2b.

For n=0, the switches xa(0) and xb(0) of the switching circuit px(0) will input the signal D(0 according to the period of the level L in the clocks CKb(N-1) and CKb(1), respectively. And D(1) is turned on to node na(0). For n=1 to (N-2), the switches xa(n) and xb(n) of the switching circuit px(n) input the signal D according to the clocks CKb(n-1) and CKb(n+1), respectively. (n) and D(n+1) are transmitted to the node na(n). For n=(N-1), the switches xa(N-1) and xb(N-1) of the switching circuit px(N-1) are input according to the clocks CKb(N-2) and CKb(0), respectively. Signals D(N-1) and D(0) are transmitted to node na(N-1). Symmetrically, the switches xc(0) and xd(0) of the switching circuit pxb(0) conduct the input signals Db(0) and Db(1) according to the clocks CKb(N-1) and CKb(1), respectively. Node nb(0); switch xc(N-1) and xd(N-1) of switching circuit pxb(N-1) input signal Db according to clocks CKb(N-2) and CKb(0), respectively (N-1) and Db(0) are transmitted to the node nb(N-1). For n=1 to (N-2), the switches xc(n) and xd(n) of the switching circuit pxb(n) input the input signal Db according to the clocks CKb(n-1) and CKb(n+1), respectively. (n) and Db(n+1) are transmitted to the node nb(n).

The multiplexer 50 also implements dual paths in the switching mechanism of the input signals. When the current CKb(0) and CKb(N-1) are both level L, the switch xa(0) to the channel unit P(0) and the switch xb(N-1) to the channel unit P(N-1) will The input signal D(0) is transmitted to the node N2 in a dual path; the inverting input signal Db(0) is transmitted to the channel unit Pb via the switch xc(0) to the channel unit Pb(0), the switch xd(N-1) ( The double path of N-1) is turned on to the node N2b. For n=1 to (N-1), when the clocks CKb(n-1) and CKb(n) are both level L, the switch xa(n) to the channel unit P(n), the switch xb(n-1) The dual path to channel unit P(n-1) transmits input signal D(n) to node N2; switch xc(n) to channel unit Pb(n), switch xd(n-1) to channel unit Pb The dual path of (n-1) transmits the input signal Db(n) to node N2b.

As mentioned before, the complementary driving units Md1, Md2 can be realized by an n-channel gold oxide half field effect transistor; correspondingly, each channel unit P(n) and Pb(n) can be p-channel gold oxide half field effect Implemented by a transistor. Each switch xa(n), xb(n), xc(n) to xd(n) can be implemented with a p-type channel MOS field effect transistor, or with a complementary MOS half field effect transistor pair (such as a transfer gate). .

In summary, the multiplexer of the present invention has a dual-path design, and the input signal is transmitted to the output through the dual path in the switching mechanism, which can function as a pre-charge and reduce the path impedance (resistance) and delay of the switching mechanism. The response speed of the multiplexer. For each channel unit and switch implementing the switching mechanism, since the period of conduction is two bit periods Tb, the conduction response does not need to be compressed into one bit period Tb, which also enables the multiplexer of the present invention to It is easier to meet the needs of high-speed signal multiplexing. In addition, the multiplexer of the present invention uses a complementary transistor pair structure in the configuration of each channel unit and the complementary driving unit, so that the power consumption of the multiplexer can be reduced; the amplitude of the signal swing of the output signal can also be compared with the amplitude of each input signal. Consistent.

In the above, although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention, and various modifications and refinements can be made without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

10, 20, 30, 40, 50. . . Multiplexer

Vdd, Vss. . . Operating Voltage

Np0-Np1, Np/Npb, N2/N2b, na(.)-nd(.), N0. . . node

A (.), Ab (.). . . Gate

Mi (.), Mib (.). . . Transistor

RL, RLb, Rm, Rs. . . resistance

Cout. . . capacitance

CLK(.), CLKb(.), CK(.), CKb(.). . . Clock

Di(.), Dib(.), D(.), Db(.). . . Input signal

Do, Dob, Dout, Doutb. . . Output signal

Di(.)_k, D(.)_k. . . Input data

Tp, Tb. . . Bit time period

Ti_p, Ti. . . cycle

IMUX. . . Battery

Dx(.), sx(.), px(.). . . Switching circuit

Dxb(.), sxb(.), pxb(.). . . Differential switching circuit

Mu1-Mu2, Md1-Md2. . . Complementary drive unit

Sa(.)-sd(.), xa(.)-xd(.). . . switch

M(.), Mb(.), P(.), Pb(.). . . Channel unit

H, L. . . Level

T0-t4. . . Time

Figure 1 illustrates an embodiment of a multiplexer.

Figure 2 shows the correlation signal and clock of the multiplexer in Figure 1 in waveform sequence.

Figure 3 illustrates a multiplexer in accordance with an embodiment of the present invention.

Figure 4 shows the correlation signal and clock of the multiplexer in Figure 4 in waveform timing.

Figures 5 and 6 illustrate the operation of the multiplexer in Figure 4.

Figure 7 illustrates a multiplexer in accordance with an embodiment of the present invention.

Figure 8 shows the correlation signal and clock of the multiplexer in Figure 7 in waveform timing.

Figure 9 illustrates an embodiment of another multiplexer.

Figure 10 illustrates a multiplexer in accordance with yet another embodiment of the present invention.

Figure 11 shows the correlation signal and clock of the multiplexer in Figure 10 in waveform timing.

30. . . Multiplexer

Vdd. . . Operating Voltage

N2/N2b, na(.)-nd(.), N0. . . node

Rm, Rs. . . resistance

Cout. . . capacitance

CK(.). . . Clock

D(.), Db(.). . . Input signal

Dout, Doutb. . . Output signal

Dx(.). . . Switching circuit

Dxb(.). . . Differential switching circuit

Mu1-Mu2. . . Complementary drive unit

Sa(.)-sd(.). . . switch

M(.), Mb(.). . . Channel unit

Claims (13)

A multiplexer includes: an output terminal for providing the output signal; and a plurality of switching circuits for receiving a plurality of input signals, each switching circuit includes: a channel unit coupled to the output terminal, the channel unit a channel is turned on; and a plurality of switches, each of which corresponds to one of the input signals, coupled to the channel unit and one of the input signals; the switches are respectively turned on by a plurality of corresponding switch conduction periods Wherein the corresponding switch-on periods in the respective switching circuits are partially overlapped with the channel-on periods, and the switch-on periods of the switches in the respective switching circuits do not overlap each other; and the switching circuits are Two of the channel conduction periods overlap partially and some do not overlap. The multiplexer of claim 1, wherein each of the channel units has a first channel end and a second channel end, the first channel end is coupled to the output end; each of the switches has two transmissions The second channel end and the input signal are respectively coupled to each other; each switch corresponds to one of the switch conduction periods, so that the two transmission ends are turned on in the corresponding switch conduction period. The multiplexer of claim 1, wherein in each switching circuit, the switches respectively correspond to different input signals of the input signals. For example, in the multiplexer of claim 1, wherein the output signal has a plurality of output data, each output data corresponds to a one-dimensional time period, and the channel conduction period and each switch conduction period are equivalent to the bit period Twice, and the time during which each of the switch conduction period partially overlaps with the channel conduction period is equivalent to the bit period. The multiplexer of claim 4, wherein each of the input signals has a plurality of input data, and each input data corresponds to a plurality of the bit periods. The multiplexer of claim 1, wherein each of the switching circuits has a first switch and a second switch; the switching circuit has a first switching circuit and a second switching circuit; and the first switching circuit The channel conduction period is equivalent to the switch conduction period of the first switch in the second switching circuit, and the channel conduction period in the second switching circuit is equivalent to the switch of the second switch in the first switching circuit On time period. The multiplexer of claim 6, wherein the plurality of input signals include a first input signal, a second input signal, and a third input signal, the first switch of the first switching circuit The second open relationship receives the first input signal and the second input signal respectively, and the first switch and the second switch of the second switching circuit respectively receive the second input signal and the third input signal. The multiplexer of claim 6, wherein the switch on period corresponding to the first switch in the first switching circuit and the switch on period corresponding to the second switch do not overlap each other. The multiplexer of claim 1, wherein each of the channel units further receives a channel clock; the channel clock alternates between a first level and a second level, and the channel is turned on. Corresponding to the time period of the channel is the first level period; and each switch further receives a corresponding switch clock; the switch clock alternates between a third level and a fourth level, and each The switch conduction period corresponding to the switch corresponds to a period in which the switch clock is the third level. The multiplexer of claim 9, wherein each of the channel clock cycles periodically alternates between the first level and the second level, and each of the switch clock systems is based on each of the channels The same period length of the pulse alternates periodically between the third level and the fourth level, and in each of the switching circuits, the channel clock is different from the phase of each of the switching clocks. The multiplexer of claim 1 further includes: a differential output; the multiplexer is based on the plurality of input signals at the differential output The terminal provides a differential output signal; and a plurality of differential switching circuits, each of the differential switching circuits includes: a channel unit having a first channel end and a second channel end, the first channel end coupling The differential output terminal; the channel unit turns on the first channel end to the second channel end in a channel conduction period; and a preset number of switches, each of the switches corresponding to one of the input signals, And having two transmitting ends respectively coupled to the second channel end and the inverted signal of the corresponding input signal; each of the switches corresponds to a switch conducting period, so that the two transmitting ends are turned on during the switch conducting period. The multiplexer of claim 11, wherein each of the differential switching circuits corresponds to one of the switching circuits, and each of the switching circuits has the same conduction period as the corresponding differential switching circuit. The preset number of switches in each of the switching circuits and the preset number of switches in the corresponding differential switching circuit respectively have the same switch-on period. The multiplexer of claim 11, further comprising: a first complementary driving unit having a controlled end and a channel end coupled to the output end and the differential output end respectively; and a second complementary The driving unit has a controlled end and a channel end coupled to the differential output end and the output end respectively.