TWI450645B - Topology structure of multiple loads - Google Patents

Description

Multiple load topology

The present invention is directed to a multiple load topology architecture.

The development of electronic technology has made IC (integrated circuit) work faster and faster, and the working frequency is getting higher and higher. The load on the design is more and more, so the designer often needs to design one. The signal control terminal is connected to two or even more wafers for providing signals to the wafers.

Please refer to FIG. 1 , which is a multi-load topology diagram of a prior art, including a signal control terminal 10 and six receiving terminals 20 , 30 , 40 , 50 , 60 , 70 , wherein the signal control terminal 10 and the like The receiving ends 20, 30, 40, 50, 60, 70 are connected by a daisy chain topology, and the receiving ends 20, 30, 40, 50, 60, 70 may be various wafers.

In this architecture, the driving signal is sent from the signal control terminal 10 to the receiving terminals 20, 30, 40, 50, 60, 70 along the transmission line, and the driving signal is shunted to the respective receiving terminals 20, 30, 40 during the transmission process. 50, 60, 70, as long as the transmission path is discontinuous, it will cause impedance mismatch. When the drive signal is transmitted along the transmission path, the impedance mismatch will produce different rebound signals. The various clutter signals are superimposed on each receiving. The terminals 20, 30, 40, 50, 60, 70 cause the voltage to be too large or too small, and even cause non-monotonic phenomena to occur, thereby affecting the signal integrity, and more serious will lead to errors in timing and digital operations.

Please continue to refer to FIG. 2 , which is a waveform diagram for verifying the signals received by the six receiving ends 20 , 30 , 40 , 50 , 60 , 70 of FIG . 1 , and the six signal curves in the figure respectively correspond to the receiving. The signal simulation curves of the terminals 20, 30, 40, 50, 60, 70. As can be seen from the figure, some of the signal simulation curves have a serious non-monotonic phenomenon in the 90ns-100ns time period, which may affect The integrity of the signal is more likely to cause timing and digital operation errors. In addition, the normal operating voltage range is 0-3.3V, but the bounce voltage due to impedance mismatch is superimposed on each receiving end to make the operating voltage range become -0.8-4V, which may cause wafer damage for long-term use.

In view of the above, it is necessary to provide a multi-load topology structure for reducing the non-monotonic phenomenon of the bounce signal caused by the impedance mismatch and the signal received by the receiving end, so as to improve the stability of the system operation.

A multi-load topology includes a signal control terminal for transmitting a driving signal, a plurality of receiving terminals for receiving the driving signal, and a plurality of transmission lines. The signal control terminal sequentially connects the receiving terminals through the transmission lines, and the signal control terminal and the signal control terminal thereof The width of the transmission line between the adjacent receiving ends and the width of the transmission line between the two adjacent receiving ends farthest from the signal control end are greater than the widths of the other partial transmission lines.

In the multi-load topology rack, by widening the width of the two transmission lines at the beginning and the end of the receiving end, the impedance values of the two transmission lines can be minimized, so that the rebound signal caused by the impedance mismatch is greatly weakened, thereby improving The stability of the system work.

Referring to FIG. 3, a preferred embodiment of the multiple load topology architecture of the present invention includes a signal control terminal 100, six receiving terminals 200, 300, 400, 500, 600, 700, two resistors RS1, RS2, and a plurality of transmission lines, wherein the signal The control terminal 100 is connected to the receiving ends 200, 300, 400, 500, 600, and 700 in a daisy-chain topology, and the signal control terminal 100 sequentially connects the receiving ends 200, 300, and 400 through the transmission lines. 500, 600, 700.

Among the transmission lines between the signal control terminal 100 and the receiving terminals 200, 300, 400, 500, 600, 700, the transmission line between the head and the tail, that is, the transmission line between the signal control terminal 100 and the receiving terminal 200 And the transmission line between the receiving end 600 and the receiving end 700 is set as a widened transmission line, that is, a transmission line between the signal control terminal 100 and the receiving end 200, and a transmission line between the receiving end 600 and the receiving end 700. The width is greater than the width of the other part of the transmission line. Since the transmission lines of the two parts of the head and the tail are widened, the impedance values of the two parts of the transmission line are the smallest, so that the rebound signal caused by the impedance mismatch is weakened, and the stability of the system operation is improved.

The resistor RS1 is disposed on a transmission line between the receiving terminals 300 and 400, and the resistor RS2 is disposed on a transmission line between the receiving terminals 400 and 500. In this embodiment, the signals received by the receiving ends 300 and 400 are prone to non-monotonic phenomenon, so that the back ends of the two terminals RS1 and RS2 are connected, and the receiving ends 300 and the RS2 are weakened by connecting the two resistors RS1 and RS2. The non-monotonic phenomenon of the received signals of 400, here the resistance of the two resistors RS1 and RS2 can be set to 47 ohms. In other embodiments, the corresponding resistor may be connected after the receiving end that actually generates the non-monotonic phenomenon, and is not limited to be disposed after the two receiving ends 300 and 400 in the embodiment, if each receiving end does not generate Non-monotonic phenomenon does not need to set the resistance. If the resistance is set, the determination of the resistance value can be obtained through multiple tests to obtain the optimum value.

In the above daisy chain topology, the two positions of the transmission line can be set as the most important components (such as function chips), that is, the two receiving ends 200 and 700 are set as the most important components, and the intermediate position setting is relatively unimportant. Components (such as test components or connector components), because the signal interference between the head and the tail is relatively weaker than the signal interference at other locations, so the most important components are placed at the head and tail to improve the stability of the system. Sex. If the components of the receiving ends 200, 300, 400, 500, 600, 700 are equally important, the placement positions of the components can be arbitrarily set.

Please continue to refer to FIG. 4 , which is a waveform diagram for verifying the signals received by the six receiving ends 200 , 300 , 400 , 500 , 600 , and 700 in FIG . 3 , and the six signal curves in the figure respectively correspond to the receiving. The signal simulation curves of the terminals 200, 300, 400, 500, 600, and 700. As can be seen from the figure, the non-monotonic phenomenon of all the signal simulation curves is basically eliminated, and the voltage range is also basically within the normal operating voltage range. Between (0-3.3V), the stability of the system has been greatly improved.

In summary, the present invention complies with the requirements of the invention patent and submits a patent application according to law. The above description is only the preferred embodiment of the present invention, and equivalent modifications or variations made by those skilled in the art will be included in the following claims.

100‧‧‧ Signal Control Terminal
RS1, RS2‧‧‧ resistance
200, 300, 400, 500, 600, 700‧‧‧ receiving end

FIG. 1 is a schematic diagram of a conventional multi-load topology.

FIG. 2 is a waveform diagram of simulation verification of signals received by multiple loads in FIG. 1.

3 is a schematic structural diagram of a preferred embodiment of a multiple load topology architecture of the present invention.

FIG. 4 is a waveform diagram of simulation verification of signals received by multiple loads in FIG. 3.

100‧‧‧ Signal Control Terminal

RS1, RS2‧‧‧ resistance

200, 300, 400, 500, 600, 700‧‧‧ receiving end

Claims (6)

A multi-load topology includes a signal control terminal for transmitting a driving signal, a plurality of receiving terminals for receiving the driving signal, and a plurality of transmission lines. The signal control terminal sequentially connects the receiving terminals through the transmission lines, and the improvement is: The width of the transmission line between the signal control end and its adjacent receiving end and the width of the transmission line between the two adjacent receiving ends farthest from the signal control end are greater than the width of the other partial transmission lines. The multiple load topology architecture of claim 1, wherein the back end of at least one of the receiving ends is connected to a resistor to attenuate the non-monotonic phenomenon of the signal received by the at least one receiving end. The multi-load topology as described in claim 2, wherein the receiving ends are six, and a resistor is disposed adjacent to the signal control end at the second near and third near receiving ends. The multiple load topology architecture of claim 3, wherein the resistance values of the two resistors are both 47 ohms. The multi-load topology as described in claim 1, wherein the component of the receiving end that is closest to the farthest and farthest from the signal control end is the most important two of the receiving ends, and the receiving end of the other location can be set. It is a non-important component. The multiple load topology as described in claim 5, wherein the important component is a functional wafer, and the non-critical component is a test component or a connector component.