TWI450493B - Receiver and method for dynamically adjusting sensitivity of receiver - Google Patents

Description

Receiver and method for dynamically adjusting receiver sensitivity

The present invention relates to a receiver, and more particularly to a receiver that dynamically adjusts sensitivity and a method of dynamically adjusting receiver sensitivity.

The receiver provides an interface that allows the signals of the pre-stage circuits to be correctly transmitted to the next stage of the circuit. When the front end signal of the receiver is abnormal input or noise, it is possible to make the operation of the wafer abnormal. For example, in a display, a video scaler (Scaler) transmits a signal group containing a clock signal and a data signal to a timing controller with a low voltage differential signaling (LVDS). The receiver in the timing controller receives this signal group and transmits this signal group to the internal circuitry of the timing controller. When the input signal of the receiver is abnormal input or noise, it may cause the timing controller to work abnormally, causing the display to display an abnormal screen. In order to prevent noise from causing abnormal work, the conventional technique uses logic gates to judge noise. However, the so-called noise is an unpredictable messy signal, which is often not completely prevented by logical methods.

The invention provides a receiver and a method for dynamically adjusting the sensitivity of the receiver, dynamically adjusting the receiving sensitivity of the receiver, so that the noise can be filtered without degrading the performance of the receiver.

The embodiment of the invention provides a receiver, including a detecting unit and a receiving unit. The detecting unit detects an input signal group and outputs the detection result. The receiving unit receives the input signal group with a sensitivity. The receiving unit dynamically adjusts the sensitivity of receiving the input signal group according to the detection result of the detecting unit.

The embodiment of the invention provides a method for dynamically adjusting the sensitivity of a receiver, comprising: detecting a phase of an input signal group, and outputting a detection result; receiving the input signal group by a sensitivity; and dynamically adjusting the signal according to the detection result Sensitivity.

Based on the above, the present invention detects an input signal group by the detecting unit, and then dynamically adjusts the receiving sensitivity of the receiving unit according to the detection result. When the receiving unit receives the noise, the receiving unit's receiving sensitivity will be lowered, so the noise can be filtered and the noise will not be output to the next level circuit. When the receiving unit receives the normal signal, the receiving sensitivity of the receiving unit is adjusted to be high, so that the performance of the receiver is not lowered.

The above described features and advantages of the present invention will be more apparent from the following description.

The energy (or amplitude) of general noise is lower than the normal signal. In order to filter out the noise, the embodiment can design the receiver input to be low in sensitivity so that the noise cannot pass through the receiver, and the normal signal of large energy can pass through the receiver. However, this method can effectively prevent noise with less energy, but it also reduces the efficiency of the receiver input. That is to say, a part of the normal signal with less energy may not be able to input a receiver with low sensitivity. Using a low sensitivity receiver will reduce the ability to tolerate normal signal errors.

FIG. 1 is a schematic diagram of functional modules of a receiver 100 capable of dynamically adjusting sensitivity according to an embodiment of the invention. The receiver 100 includes a detecting unit 110 and a receiving unit 120. The detecting unit 110 detects the input signal group IN and outputs the detection result DR to the receiving unit 120. The receiving unit 120 receives the input signal group IN with a sensitivity and provides an output signal OUT to a next-stage circuit (not shown). The receiving unit 120 dynamically adjusts the sensitivity according to the detection result DR of the detecting unit 110. When the detecting unit 110 detects that the input signal group IN is noise, the receiving sensitivity of the receiving unit 120 is dynamically lowered, so that the noise can be filtered, and the noise is not output to the next level circuit. When the detecting unit 110 detects the normal signal of the input signal group IN, the receiving sensitivity of the receiving unit 120 is dynamically adjusted, so that the performance of the receiver 100 is not lowered.

FIG. 2 is a schematic diagram of functional modules of the receiving unit 120 of FIG. 1 according to an embodiment of the invention. Here, the input signal group IN contains input signal pairs INp and INn. The receiving unit 120 includes an amplifier AMP, a first switch SW1, a second switch SW2, a first resistor R1, and a second resistor R2. The first input and the second input of the amplifier AMP receive input signal pairs INp and Inn, respectively. The first switch SW1 and the second switch SW2 are determined to be turned on or off according to the detection result DR of the detecting unit 110. The first resistor R1 is connected in series with the first switch SW1 between the first input of the amplifier AMP and a first voltage (eg, the system voltage VDD). The second resistor R2 and the second switch SW2 are connected between the second input terminal of the amplifier AMP and a second voltage (for example, a ground voltage).

In general, normal signals are regular, while noise is not regular. Therefore, if the phase of the input signal group IN can be locked, it means that the input signal group IN is a normal signal. When the detection result DR shows that the detecting unit 110 has not locked the phase of the input signal group IN, the first switch SW1 and the second switch SW2 are turned on. At this time, the first resistor R1 is a pull-up resistor to pull up the common mode voltage of the first input terminal of the amplifier AMP, and the second resistor R2 is a pull-down resistor to pull down the common mode voltage of the second input terminal of the amplifier AMP. Since the common mode voltage of the first input terminal and the second input terminal of the amplifier AMP has been pulled apart, the receiving sensitivity of the amplifier AMP is dynamically lowered, so that noise can be filtered.

When the detection result DR shows that the detecting unit 110 has locked the phase of the input signal group IN, the first switch SW1 and the second switch SW2 are turned off. At this time, the first resistor R1 and the second resistor R2 do not pull off the common mode voltage of both the first input terminal and the second input terminal of the amplifier AMP. Therefore, the amplifier AMP is dynamically adjusted back to high sensitivity.

FIG. 3 is a schematic diagram of functional modules of the receiving unit 120 of FIG. 1 according to another embodiment of the present invention. The receiving unit 120 includes an amplifier AMP, a first current source CS1, and a second current source CS2. The input of the amplifier AMP receives the input signal group IN, and the output provides the output signal OUT. The first current source CS1 determines the current amount of the first current I1 according to the detection result DR of the detecting unit 110, and supplies the first current I1 to the first power terminal of the amplifier AMP. The second current source CS2 determines the amount of current of the second current I2 according to the detection result DR, and supplies the second current I2 to the second power terminal of the amplifier AMP. The aforementioned first current I1 and second current I2 can provide the operating power required by the amplifier AMP.

When the detection result DR shows that the detecting unit 110 has not locked the phase of the input signal group IN, the current of the power supply terminal of the amplifier AMP (ie, the first current I1 and the second current I2) is turned down. By reducing the current at the power supply terminal, the gain of the amplifier AMP can be adjusted to be smaller, and the sensitivity of the amplifier AMP is dynamically lowered. When the detection result DR shows that the detecting unit 110 has locked the phase of the input signal group IN, the current of the power supply terminal of the amplifier AMP is adjusted. As the current at the power supply terminal of the amplifier AMP becomes larger, the gain also becomes larger, and the sensitivity of the amplifier AMP is also dynamically adjusted.

In some embodiments, the set of input signals may include a clock signal CLKin and a data signal Din (eg, input signal pairs INp and INn). The detecting unit 110 can detect the clock signal CLKin and output the detection result DR. The receiving unit 120 adjusts the sensitivity correspondingly according to the detection result DR, and receives the data signal Din with the adjusted sensitivity. The implementation of the detecting unit 110 will be described below by taking the example of "detecting the phase of the clock signal CLKin" as an example.

FIG. 4 is a schematic diagram of functional modules of the detecting unit 110 of FIG. 1 according to an embodiment of the invention. The detecting unit 110 includes a delay locked loop (DLL), and the lock delay circuit includes a phase detector (PD) 410, a charge pump (CP) 420, and a low pass filter (low). -pass filter, LPF) 430 and voltage controlled delay line (VCDL) 440. The phase detector 410 receives and compares the phases of the clock signals CLKin and CLKout. The charge pump 420 charges or discharges the low pass filter 430 according to the comparison result of the phase detector 410. Therefore, the low pass filter 430 can provide the delay control voltage Vctrl to the voltage controlled delay line 440. The voltage-controlled delay line 440 correspondingly delays the clock signal CLKin according to the control of the delay control voltage Vctrl, and outputs the delayed clock signal as the clock signal CLKout. The lock delay circuit described above is a well-known technique, and details are not described herein. When the lock delay circuit locks the clock signal CLKin, the delay control voltage Vctrl approaches a certain preset voltage, and the phase of the clock signal CLKout also approaches a certain preset phase. Therefore, in some embodiments, the detecting unit 110 may output the delay control voltage Vctrl or the clock signal CLKout of the voltage controlled delay line 440 as the detection result DR.

FIG. 5 is a schematic diagram of functional modules of the detecting unit 110 of FIG. 1 according to another embodiment of the present invention. The detecting unit 110 includes a phase locked loop (PLL), and the phase locked loop includes a phase frequency detector (PFD) 510, a charge pump 520, a low pass filter 530, and a voltage controlled oscillator. (Voltage-controlled Oscillator, VCO) 540 and a divider 550. The phase frequency detector 510 receives and compares the phase and frequency of the clock signal CLKin and the feedback clock CLKfb. The charge pump 520 charges or discharges the low pass filter 530 according to the comparison result of the phase frequency detector 510. Therefore, the low pass filter 530 can provide the frequency control voltage Vctrl to the voltage controlled oscillator 540. The voltage controlled oscillator 540 generates a clock signal CLKout correspondingly according to the control of the frequency control voltage Vctrl. After the frequency divider 550 divides the clock signal CLKout, the frequency-divided clock signal is output to the phase frequency detector 510 as the feedback clock CLKfb. The above-mentioned phase-locked loops are well known in the art, and thus the details thereof will not be described again. The frequency of the phase-locked loop output varies with the magnitude of the voltage Vctrl. When the phase locked loop locks the clock signal CLKin, the frequency control voltage Vctrl approaches a certain preset voltage, and the frequency of the clock signal CLKout also approaches a certain preset frequency. Therefore, in some embodiments, the detecting unit 110 may output the frequency control voltage Vctrl or the clock signal CLKout of the voltage controlled oscillator 540 as the detection result DR.

FIG. 6 is a schematic diagram of functional modules of the detecting unit 110 of FIG. 1 according to another embodiment of the present invention. The detecting unit 110 includes a phase locked loop 610 and a frequency comparator 620. The phase locked loop 610 can be referred to FIG. 5 and related description. Frequency comparator 620 is coupled to the output of phase locked loop 610. If the phase of the clock signal CLKin can be locked, it indicates that the input signal group IN is a normal signal. When the phase locked loop 610 is locked, the clock frequency of the output clock signal CLKout of the phase locked loop 610 is fixed. Therefore, the frequency comparator 620 compares the frequency of the output signal CLKout with the reference frequency Fref. The frequency comparator 620 transmits the comparison result to the receiving unit 120 as the detection result DR.

FIG. 7 is a schematic diagram of functional modules of the detecting unit 110 of FIG. 1 according to a further embodiment of the present invention. The detecting unit 110 includes a phase locked loop (or lock delay loop) 710 and a voltage comparator 720. If 710 is a phase-locked loop, the phase-locked loop 710 can be implemented with reference to FIG. 5 and the related description, and the frequency control voltage Vctrl of the voltage-controlled oscillator 540 is output to the voltage comparator 720. If 710 is a lock-up loop, the lock-up loop 710 can be implemented with reference to FIG. 4 and the related description, and the delay control voltage Vctrl of the voltage-controlled delay line 440 is output to the voltage comparator 720.

FIG. 8 is a timing diagram illustrating the internal control voltage Vctrl and the reference voltage Vref of the phase locked loop (or lock delay loop) according to an embodiment of the invention. During the locking process of the phase-locked loop (or lock-delay loop), the control voltage Vctrl will slowly drop from VDD. When it is locked, the control voltage Vctrl will be fixed at a certain voltage value. Therefore, the present embodiment compares the frequency control voltage (or delay control voltage) Vctrl with the reference voltage Vref using the voltage comparator 720. When the value of the control voltage Vctrl is less than the reference voltage Vref, the detecting unit 110 may determine that the phase locked loop (or the lock delay loop) is locked, and transmit the comparison result to the receiving unit 120 as the detection result DR.

FIG. 9 is a schematic diagram showing functional blocks of the receiving unit 120 of FIG. 1 according to still another embodiment of the present invention. In this embodiment, the detecting unit 110 may be a phase locked loop or a lock delay loop. The detection result DR may be the frequency control voltage Vctrl of the internal voltage controlled oscillator 540 of the phase locked loop (as shown in FIG. 5), or may be the delay control voltage Vctrl of the internal voltage controlled delay line 440 of the lock delay loop (as shown in FIG. 4). Show).

The receiving unit 120 includes an amplifier AMP, a first transistor M1, and a second transistor M2. The transistors M1 and M2 may be NMOS transistors or other types of transistors. The first input and the second input of the amplifier AMP receive the input signal pair INp and INn of the input signal group IN. The control terminals of the transistors M1 and M2 receive the detection result DR (here, the control voltage Vctrl). A first end of the first transistor M1 is coupled to a first input of the amplifier AMP, and a second end of the first transistor M1 is coupled to a first voltage (eg, system voltage VDD). The first end of the second transistor M2 is coupled to the second input of the amplifier AMP, and the second end of the second transistor M2 is coupled to a second voltage (eg, a ground voltage). When the control voltage Vctrl is larger, the resistance of the NMOS transistors M1 and M2 is smaller, so that the sensitivity of the amplifier AMP is worse. When the control voltage Vctrl is smaller, the resistance of the NMOS transistors M1 and M2 is larger, and the sensitivity of the amplifier AMP is better.

FIG. 10 is a schematic diagram showing functional blocks of the receiving unit 120 of FIG. 1 according to a further embodiment of the present invention. FIG. 11 is a timing diagram illustrating the internal control voltage Vctrl and the reference voltage of the phase-locked loop (or lock-up loop) of FIG. In this embodiment, the detecting unit 110 may be a phase locked loop or a lock delay loop. The detection result DR may be the frequency control voltage Vctrl of the internal voltage controlled oscillator 540 of the phase locked loop (as shown in FIG. 5), or may be the delay control voltage Vctrl of the internal voltage controlled delay line 440 of the lock delay loop (as shown in FIG. 4). Show). The receiving unit 120 includes a voltage comparator 1010, an amplifier AMP, at least one first switch, at least one first resistor, at least one second switch, and at least one second resistor. The voltage comparator 1010 is connected to the detecting unit 110 to receive the detection result DR (here, the control voltage Vctrl). The voltage comparator 1010 compares the voltage value of the detection result DR with at least one reference voltage value, and outputs a comparison result.

The above reference voltage value, the number of the first switch, the first resistor, the second switch, and the second resistor may be determined according to design requirements. In this embodiment, four first switches (ie, SW1-1, SW1-2, SW1-3, and SW1-4) and four first resistors (ie, R1-1, R1-2, R1-3, and R1-) are used. 4), 4 second switches (ie SW2-1, SW2-2, SW2-3, SW2-4) and 4 second resistors (ie R2-1, R2-2, R2-3, R2-4) . In addition, this embodiment will use four different levels of reference voltage values V1, V2, V3 and V4, as shown in FIG.

The first input and the second input of the amplifier AMP receive the input signal pair INp and INn of the input signal group IN. The first resistor and the first switch are connected in series between the first input end of the amplifier AMP and the first voltage (for example, the system voltage VDD), for example, the first resistor R1-1 and the first switch SW1-1 are connected in series with the amplifier AMP. Between the first input terminal and the system voltage VDD, and so on, the remaining first resistors R1-2 R R1-4 and the remaining first switches SW1-2 SWSW1-4. The second switch and the second resistor are connected in series between the second input end of the amplifier AMP and the second voltage (for example, a ground voltage), for example, the second resistor R2-1 and the second switch SW2-1 are connected in series with the amplifier AMP. Between one input terminal and the ground voltage, and so on, the remaining second resistors R2-2 to R2-4 and the remaining second switches SW2-2 to SW2-4.

The voltage comparator 1010 compares the control voltage Vctrl with the reference voltages V1 to V4, and outputs comparison results S1, S2, S3, and S4. The first switch SW1-1 and the second switch SW2-1 are determined to be turned on or off according to the comparison result S1. The first switch SW1-2 and the second switch SW2-2 are determined to be turned on or off according to the comparison result S2. The first switch SW1-3 and the second switch SW2-3 are determined to be turned on or off according to the comparison result S3. The first switch SW1-4 and the second switch SW2-4 are determined to be turned on or off according to the comparison result S4. When the control voltage Vctrl is greater than the reference voltage V1, the voltage comparator 1010 will all the first switches SW1-1~SW1-4 and all the second switches SW2-1~SW2 by outputting the comparison results S1, S2, S3 and S4. -4 turn on. At this time, the resistance of the pull-up resistor and the pull-down resistor are the smallest, that is, the common mode voltage of the first input terminal of the amplifier AMP and the common mode voltage of the second input terminal are the largest, so the sensitivity is the worst.

When the control voltage Vctrl is between the reference voltage V1 and the reference voltage V2 (ie, V1 > Vctrl > V2), the voltage comparator 1010 will turn the first switch SW1-4 by outputting the comparison results S1, S2, S3, and S4. Turning off with the second switch SW2-4, and turning on the remaining first switches SW1-1~SW1-3 and the remaining second switches SW2-1~SW2-3. When the control voltage Vctrl is between the reference voltage V2 and the reference voltage V3 (ie, V2 > Vctrl > V3), the voltage comparator 1010 will turn the first switch SW1-3 by outputting the comparison results S1, S2, S3, and S4. The ~SW1-4 and the second switches SW2-3 to SW2-4 are turned off, and the first switches SW1-1 to SW1-2 and the second switches SW2-1 to SW2-2 are turned on. When the control voltage Vctrl is between the reference voltage V3 and the reference voltage V4 (ie, V3>Vctrl>V4), the voltage comparator 1010 will turn the first switch SW1-2 by outputting the comparison results S1, S2, S3, and S4. The ~SW1-4 and the second switches SW2-2 to SW2-4 are turned off, and the first switch SW1-1 and the second switch SW2-1 are turned on.

When the control voltage Vctrl is smaller than the reference voltage V4, all of the first switches SW1-1 to SW1-4 and all of the second switches SW2-1 to SW2-4 are turned off. At this time, the pull-up resistor and the pull-down resistor have the largest resistance value, that is, the common mode voltage of the first input terminal of the amplifier AMP and the common mode voltage of the second input terminal have the smallest difference, so the sensitivity is the best. Therefore, the embodiment shown in Fig. 10 can gradually increase the sensitivity of the amplifier AMP depending on the degree of signal locking.

Take the low voltage differential signal (LVDS) as an example. Figure 12 is a schematic diagram showing the functional blocks for applying the receiver of Figure 1 to a low voltage differential signal (LVDS). The receiver 1200 includes a detecting unit 110, and four receiving units (ie, 120-1, 120-2, 120-3, 120-4) and four latchers (ie, L1, L2, L3, L4). The input signal group IN includes first data signal pairs D1p and D1n, second data signal pairs D2p and D2n, third data signal pairs D3p and D3n, fourth data signal pairs D4p and D4n, and clock signal pairs CLKp and CLKn.

The receiving units 120-1 to 120-4 each receive a corresponding data signal pair [D1p, D1n]~[D4p, D4n]. The detection result DR output by the detecting unit 110 can adjust the sensitivity of the receiving units 120-1~120-4. For the implementation of the receiving units 120-1 to 120-4, reference may be made to the receiving unit 120 described in the foregoing embodiments. The input terminals of the latchers L1~L4 respectively receive the outputs of the corresponding receiving units 120-1~120-4, and latch the outputs of the receiving units 120-1~120-4 according to the clock signals output by the detecting unit 110. .

The detection unit 110 includes an amplifier 1210 and a lock-up loop (or phase-locked loop) 1220. The sensitivity of the receiver of the amplifier 1210 is also determined by the detection result DR. For the implementation of the amplifier 1210, reference may be made to the receiving unit 120 described in the foregoing embodiments. The amplifier 1210 receives the clock signals CLKp and CLKn, and then outputs the clock signal CLKin to the lock-up loop (or phase-locked loop) 1220. For the implementation of the lock-up loop (or phase-locked loop) 1220, reference may be made to the detecting unit 110 described in the foregoing embodiments. The input of the lock delay loop (or phase locked loop) 1220 is connected to the output of the amplifier 1210. The lock delay loop (or phase lock loop) 1220 phase locks the clock signal CLKin, and supplies the detection result DR to the receiving units 120-1~120-4 and the amplifier 1210 to dynamically adjust the receiving units 120-1~120. -4 with the sensitivity of the amplifier 1210.

Here, the method of dynamically adjusting the receiver sensitivity by the above embodiments is organized. The method includes: detecting a phase of the input signal group IN, and outputting the detection result DR; receiving the input signal group IN with a sensitivity; and dynamically adjusting the sensitivity according to the detection result DR. In the application example in which the input signal group IN includes a clock signal and a data signal, the step of "detecting the phase of the input signal group IN" may be to detect the phase of the clock signal and output the detection result DR. The step of "receiving the input signal group IN with a sensitivity" may receive the data signal with the sensitivity.

In summary, when the input end of the receiving unit 120 has no input signal or is not connected (ie, floating), the input end of the receiving unit 120 may receive various kinds of noise. At this time, the detection unit 110 (for example, the phase locked loop or the lock delay loop) cannot be locked because the input signal group IN is noise. Therefore, the receiving unit 120 is dynamically adjusted to a condition of low sensitivity. Because the sensitivity of the receiving unit 120 is reduced, most of the noise can be filtered out. Taking Figure 12 as an example, there are two conditions for locking the phase-locked loop (or lock-delay loop) 1220: 1. The input clock signal must have a large amount of energy, and can pass the low-sensitivity amplifier 1210; 2. is the input The clock signal must be maintained at a fixed frequency to lock the phase-locked loop (or lock-up loop) 1220. Once the frequency of the input clock signal changes, the phase-locked loop (or lock-delay loop) 1220 will return to the unlocked state. Therefore, when the normal clock signal starts to input, because the energy of the clock signal is large and the frequency is fixed, it can be input to the phase-locked loop (or lock-up loop) 1220 via the amplifier 1210, so that the phase-locked loop (or lock) Late circuit) 1220 locked. At this time, the amplifier 1210 and the receiving units 120-1 to 120-4 are adjusted to a high sensitivity state, and the input data IN is not attenuated due to insufficient performance of the amplifier.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100, 1200. . . receiver

110. . . Detection unit

120, 120-1~120-4. . . Receiving unit

410. . . Phase detector

420, 520. . . Charge pump

430, 530. . . Low pass filter

440. . . Voltage controlled delay line

510. . . Phase frequency detector

540. . . Voltage controlled oscillator

550. . . Frequency divider

610. . . Phase-locked loop

620. . . Frequency comparator

710, 1220. . . Phase-locked loop or lock-up loop

720, 1010. . . Voltage comparator

1210, AMP. . . Amplifier

CLKin, CLKout, CLKfb, CLKp, CLKn. . . Clock signal

CS1, CS2. . . Battery

DR. . . Detection result

Fref. . . Reference frequency

I1, I2. . . Current

IN. . . Input signal group

INp, INn. . . input signal

D1p, D1n, D2p, D2n, D3p, D3n, D4p, D4n. . . Data signal

L1~L4. . . Shackle

M1, M2. . . Transistor

OUT. . . output signal

R1~R2, R1-1~R1-4, R2-1~R2-4. . . resistance

S1~S4. . . Comparing results

SW1~SW2, SW1-1~SW1-4, SW2-1~SW2-4. . . switch

Vctrl. . . Control voltage

Vref, V1~V4. . . Reference voltage

FIG. 1 is a schematic diagram of functional modules of a receiver capable of dynamically adjusting sensitivity according to an embodiment of the invention.

FIG. 2 is a schematic diagram of functional modules of the receiving unit of FIG. 1 according to an embodiment of the invention.

FIG. 3 is a schematic diagram showing functional blocks of the receiving unit of FIG. 1 according to another embodiment of the present invention.

FIG. 4 is a schematic diagram showing functional modules of the detecting unit of FIG. 1 according to an embodiment of the invention.

FIG. 5 is a schematic diagram of functional modules of the detecting unit of FIG. 1 according to another embodiment of the present invention.

FIG. 6 is a schematic diagram of functional modules of the detecting unit of FIG. 1 according to another embodiment of the present invention.

FIG. 7 is a schematic diagram of functional modules of the detecting unit of FIG. 1 according to a further embodiment of the present invention.

FIG. 8 is a timing diagram illustrating the internal control voltage Vctrl and the reference voltage Vref of the phase locked loop (or lock delay loop) according to an embodiment of the invention.

FIG. 9 is a schematic diagram showing functional blocks of the receiving unit of FIG. 1 according to still another embodiment of the present invention.

FIG. 10 is a schematic diagram showing functional blocks of the receiving unit of FIG. 1 according to a further embodiment of the present invention.

FIG. 11 is a timing diagram illustrating the internal control voltage and the reference voltage of the phase locked loop (or lock delay loop) of FIG.

Figure 12 is a schematic diagram showing the functional blocks for applying the receiver of Figure 1 to a low voltage differential signal (LVDS).

100. . . receiver

110. . . Detection unit

120. . . Receiving unit

DR. . . Detection result

IN. . . Input signal group

OUT. . . output signal

Claims (21)

A receiver includes: a detecting unit that detects whether an input signal group is a noise and outputs a detection result; and a receiving unit that receives the input signal group with a sensitivity, wherein the sensitivity determines to pass the Detecting a signal quantity of the input signal group of the unit, wherein the receiving unit dynamically adjusts the sensitivity according to the detection result. The receiver of claim 1, wherein the receiving unit comprises: an amplifier, a first input end and a second input end receive the input signal group; and a first switch, according to the detection result Determining that the first switch is turned on or off; a first resistor, the first switch and the first resistor are connected in series between the first input end of the amplifier and a first voltage; and a second switch is And detecting a result that the second switch is turned on or off; and a second resistor, the second switch and the second resistor are connected in series between the second input end of the amplifier and a second voltage. The receiver of claim 1, wherein the receiving unit comprises: an amplifier, the input end of which receives the input signal group; a first current source, determining a current amount of the first current according to the detection result, and supplying the first current to a first power terminal of the amplifier; and a second current source according to the detection result And determining a current amount of the second current, and supplying the second current to a second power terminal of the amplifier. The receiver of claim 1, wherein the receiving unit comprises: an amplifier, a first input end and a second input end receiving the input signal group; a first transistor, the control end receiving The detection result is that the first end of the first transistor is connected to the first input end of the amplifier, the second end of the first transistor is connected to a first voltage, and a second transistor is controlled at the control end thereof. Receiving the detection result, the first end of the second transistor is connected to the second input end of the amplifier, and the second end of the second transistor is connected to a second voltage. The receiver of claim 1, wherein the receiving unit comprises: a voltage comparator connected to the detecting unit to receive the detection result, and the voltage comparator compares the voltage value of the detection result with At least one reference voltage value, and outputting a comparison result; an amplifier, a first input end and a second input end receive the input signal group; at least one first switch, determining, according to the comparison result, the first switch is turned on Or deadline; At least one first resistor, the first switch and the first resistor are connected in series between the first input end of the amplifier and a first voltage; and the at least one second switch determines, according to the comparison result, the second switch is Turning on or off; and at least one second resistor, the second switch and the second resistor are connected in series between the second input end of the amplifier and a second voltage. The receiver of claim 1, wherein the input signal group includes a clock signal and a data signal, the detecting unit detects the clock signal and outputs the detection result, and the receiving unit uses the sensitivity Receive the data signal. The receiver of claim 6, wherein the detecting unit comprises a lock delay circuit, and the lock delay circuit receives the clock signal. The receiver of claim 7, wherein the detection result is a delay control voltage of a voltage controlled delay line in the lock-up loop. The receiver of claim 7, wherein the detecting unit further comprises: a voltage comparator connected to the lock-up loop to receive a delay control voltage of a voltage-controlled delay line in the lock-up loop, The voltage comparator compares the delay control voltage with a reference voltage, and transmits the comparison result to the receiving unit as the detection result. The receiver of claim 6, wherein the detecting unit comprises a phase locked loop, and the phase locked loop receives the clock signal. The receiver of claim 10, wherein the detection result is a frequency control voltage of a voltage controlled oscillator in the phase locked loop. The receiver of claim 10, wherein the detecting unit further comprises: a frequency comparator connected to the output end of the phase locked loop, the frequency comparator comparing the frequency of the output signal of the phase locked loop with A reference frequency is transmitted to the receiving unit as a result of the comparison. The receiver of claim 10, wherein the detecting unit further comprises: a voltage comparator connected to the phase locked loop to receive a frequency control voltage of a voltage controlled oscillator in the phase locked loop, The voltage comparator compares the frequency control voltage with a reference voltage, and transmits the comparison result to the receiving unit as the detection result. The receiver of claim 1, wherein the input signal group includes a clock signal and a data signal, the receiving unit receives the data signal with the sensitivity, and the detecting unit comprises: an amplifier, Sensitivity receiving the clock signal; and a lock delay loop, the input end of the lock delay loop is connected to the output end of the amplifier; wherein the lock delay loop provides the detection result to the receiving unit and the amplifier to dynamically adjust the Sensitivity. The receiver of claim 1, wherein the input signal group includes a clock signal and a data signal, the receiving unit receives the data signal with the sensitivity, and the detecting unit comprises: an amplifier, Sensitivity receiving the clock signal; a phase locked loop, the input end of the phase locked loop is connected to the output end of the amplifier; wherein the phase locked loop provides the detection result to the receiving unit and the amplifier to dynamically adjust the sensitivity. The receiver of claim 1, wherein when the input signal group is the noise, the receiving unit dynamically lowers the sensitivity, and when the input signal group is a normal signal, the receiving unit This sensitivity will be dynamically increased. A method for dynamically adjusting receiver sensitivity includes: detecting a phase of an input signal group to determine whether the input signal group is a noise, and outputting a detection result; receiving the input signal group with a sensitivity, wherein the sensitivity Determining a signal amount of the input signal group passing the detection unit; and dynamically adjusting the sensitivity according to the detection result. The method for dynamically adjusting receiver sensitivity as described in claim 17, wherein the step of adjusting the sensitivity comprises: when the phase of the input signal group is not locked, the first input end and the second input end of an amplifier are The common mode voltage is pulled apart; and when the phase of the input signal group is locked, the common mode voltage of both the first input and the second input of the amplifier is not pulled. A method for dynamically adjusting receiver sensitivity as described in claim 17, wherein the step of adjusting the sensitivity comprises: reducing a current of a power supply terminal of an amplifier when the phase of the input signal group is not locked; When the phase of the input signal group has been locked, the current at the power supply terminal of the amplifier is increased. The method for dynamically adjusting receiver sensitivity according to claim 17, wherein the input signal group includes a clock signal and a data signal, and the step of detecting a phase of the input signal group is to detect the clock signal. The detection result is outputted by the phase, and the step of receiving the input signal group with a sensitivity is to receive the data signal with the sensitivity. The method for dynamically adjusting receiver sensitivity as described in claim 17 further includes: dynamically reducing the sensitivity when the input signal group is the noise; and dynamically when the input signal group is a normal signal. Increase the sensitivity.