TW201138297A - Receiver and method for dynamically adjusting sensitivity of receiver - Google Patents

Abstract

A receiver and a method for dynamically adjusting sensitivity of the receiver are provided. The receiver includes a detection unit and a receiving unit. The detection unit detects an input signal group, and outputs a detection result. The receiving unit receives the input signal group according to a sensitivity. Wherein, the receiving unit dynamically adjust the sensitivity used for receiving the input signal group according to the detection result of the detection unit.

Description

201138297

^-0122-TW 33258twf.doc/n VI. Description of the Invention: [Technical Field] The present invention relates to a receiver for dynamically adjusting the sensitivity of a receiver and a method of motion. [Prior Art] ❿ , and particularly with respect to a mode that adjusts the sensitivity of the receiver, the reception of the miscellaneous-interfaces enables the pre-stage electrical_signals to be correctly transmitted to the lower-level circuits. When the front-end signal of the receiver is abnormally transmitted, the noise is 'discriminable'. For example, in the monitor, the video scaler (Scaler) will use a low-voltage differential signal (1〇w bar differential signaling, LVDS). The group of signals containing the clock signal and the data signal is transmitted to the timing controller (9) ming c〇ntr〇Uer). The receiver in the timing controller receives the signal group and transmits the signal group to the timing control ^ internal circuit. The receiver's input signal is abnormal input or noise =, it may cause the timing controller's guard to be abnormal, causing the display to display different = face. In order to prevent noise from causing abnormal operation, the traditional technology uses logic gates. However, the so-called noise is an unpredictable messy signal, which is often not completely prevented by a logical method. SUMMARY OF THE INVENTION The present invention provides a receiver and a method for dynamically adjusting the sensitivity of a receiver. The receiver's receiving sensitivity 'can therefore filter the noise without degrading the performance of the receiver. 33258twf.doc/n 201138297 _Inventive embodiment proposes a The receiver includes a detecting unit and a receiving unit. The detecting unit detects an input signal group and outputs a detection result. The receiving unit receives the input signal group with a sensitivity, wherein the receiving unit moves according to the side result of the detecting unit. Receiving the sensitivity of the input signal group. The embodiment of the invention provides a method for dynamically adjusting the sensitivity of the receiver, comprising: detecting the phase of an input group and outputting a measurement result; receiving by a sensitivity The input signal group is dynamically adjusted according to the detection result. Based on the above, the detection unit detects an input signal group by the detecting unit, and then dynamically adjusts the receiving sensitivity of the receiving unit according to the detection result. When the noise is received, the receiving sensitivity of the receiving unit will be lowered, so the noise can be filtered and the noise will not be output to the next stage circuit. When the receiving unit receives the normal signal, the receiving unit's receiving sensitivity will be increased. 'Therefore, the performance of the receiver is not reduced. In order to make the above features and advantages of the present invention more obvious, The embodiments are described in detail below with reference to the accompanying drawings. [Embodiment] The energy (or amplitude) of the general noise is lower than the normal signal. In order to filter out the noise, the receiver input can be used in this embodiment. Designed for low sensitivity, so that noise can't pass through the receiver, and normal signals with large energy can pass through the receiver. However, this method can effectively prevent noise with less energy, but it also reduces the input of the receiver. Performance. That is to say, some of the smaller energy sources in 201138297yW 33258twf.doc/n may not be able to input low-sensitivity receivers. Using a low-sensitivity receiver will reduce the ability to tolerate normal signal errors. 1 is a schematic diagram of functional modules of a receiver 100 that can dynamically adjust sensitivity according to an embodiment of the invention. The receiver 100 includes a detecting unit 110 and a receiving unit 120. The detecting unit 110 detects the input signal group IN ′ and outputs the detection result dr to the receiving unit 12 〇. The receiving unit 12 receives the input signal group IN with a sensitivity and provides the output signal out to the next stage circuit (not shown). The receiving unit 120 dynamically adjusts the sensitivity according to the detection result DR of the detecting unit 110. When the detecting unit 11 detects that the input signal group IN is noise, the receiving sensitivity of the receiving unit 12〇 is dynamically lowered, so that the noise can be filtered and the noise is not output to the next level circuit. When the detecting unit Π0 detects the input signal group Ν normal signal, the receiving sensitivity of the receiving unit 120 is dynamically adjusted, so that the performance of the receiver 100 is not lowered. 2 is a schematic diagram of a power month b module of the receiving unit 12A of FIG. 1 according to an embodiment of the present invention. Here, the input signal group contains input signal pairs INp and INn. The receiving unit 12A includes an amplifier ΑΜρ, a first switch SW, a second switch SW2, a first resistance illusion, and a second resistor R2. The input-input and the second input of the θ AMP receive the input signals, mP and Inn, respectively. The first switch SW1 and the second switch 2 are determined to be turned on or off according to the SDR of the detecting unit 110. The first resistor R1 is connected in series with the first switch SW1 between the first input of the amplifier amp and a third voltage (e.g., system voltage VDD). The second resistor R2 is coupled to the second open 33258 twf.doc/n 201138297 J2.xw switch SW2 between the second input of the amplifier AMP and a second voltage (e.g., ground voltage). In general, 'normal signals are regular, and noise is not regular. Therefore, if the phase of the input signal group can be locked, it indicates that the input signal group IN is a normal signal. When the detection result DR shows that the detecting unit 110 has not locked the phase of the input signal group IN, the first switch SW1 and the second switch SW2 are turned on. At this time, the first resistor ri is a pull-up resistor and the common mode voltage of the first input terminal of the amplifier AMP is pulled up, and the second resistor R2 is a pull-down resistor to pull down the common mode voltage of the second input terminal of the amplifier AMP. Since the common-mode voltage of the first input and the second input of the amplifier AMP has been pulled apart, the receiving sensitivity of the amplifier AMP is dynamically lowered, so noise can be filtered. When the detection result DR shows that the detecting unit 110 has locked the phase of the input signal group IN, the first switch SW1 and the second switch SW2 are turned off. At this time, the first resistor R1 and the second resistor R2 do not pull off the common mode voltage of both the first input terminal and the second input terminal of the amplifier AMP. Therefore, the amplifier AMP is dynamically adjusted back to high sensitivity. FIG. 3 is a schematic diagram showing functional blocks of the receiving unit 120 of FIG. 1 according to another embodiment of the present invention. The receiving unit 120 includes an amplifier amp, a first current source CS1, and a second current source CS2. The input of amplifier AMP receives input signal group IN, while the output provides output signal out. The first current source CS1 determines the current amount of the first current II according to the detection result DR of the detecting unit 110, and supplies the first current II to the first power terminal of the amplifier amp. The second current source CS2 determines the current amount ' of the second current 12' according to the detection result dr and supplies the second current I2 to the second power terminal of the amplifier AMp. The aforementioned first current II and second current can provide the operating power required by the amplifier AMP. When the detection result DR shows that the detecting unit 11 has not locked the phase of the input signal group IN, the current of the power supply terminal of the amplifier AMP (i.e., the first current II and the second current 12) is turned down. By reducing the current at the power supply terminal, the gain of the amplifier AMP can be adjusted to be smaller, and the sensitivity of the amplifier AMP is dynamically lowered. When the detection result dr shows that the detecting unit 110 has locked the phase of the input signal group IN, the current of the power supply terminal of the amplifier AMP is turned up. As the current at the power supply terminal of the amplifier AMP becomes larger, the gain also becomes larger, and the sensitivity of the amplifier AMP is also dynamically adjusted. In some embodiments, the set of input signals can include a clock signal CLKin and a data signal Din (e.g., input signal pairs iNp and iNn). The detecting unit 110 can detect the clock signal CLKin and output the detection result DR. The receiving unit 120 adjusts the sensitivity correspondingly according to the detection result DR, and receives the data signal Din with the adjusted spirit scale. The following describes the implementation of the detection unit no by taking "Detecting the phase of the clock signal CLKin" as an example. FIG. 4 is a schematic diagram of a power module of the detecting unit 110 of FIG. 1 according to an embodiment of the invention. The test element 110 includes a delay locked loop (DLL). The lock delay circuit includes a phase detector (PD) 410, a charge pump (CP) 42〇, and a low-pass filter. A low-pass filter (LPF) 430 and a voltage-controlled delay line (v〇ltage controlled delay 201138297 i22-TW 33258 twf.doc/n line, VCDL) 440. The phase debt detector 41 receives and compares the phases of the clock signals CLKin and CLKout. The charge pump 42 is charged or discharged corresponding to the low pass filter 43A according to the comparison result of the phase_channel 410. Thus, low pass filtered state 430 can provide a delayed control voltage Vci^ to voltage controlled delay line 440. The voltage-controlled delay line 44 is delayed in accordance with the control of the delay control voltage Vctrl, correspondingly delays the clock signal CLKin, and outputs the delayed clock signal as the clock signal CLKout. The above-mentioned lock-up loops are well known in the art, so the details will not be described again. When the lock delay circuit locks the clock signal CLKin, the delay control voltage Vctrl approaches a certain preset voltage, and the phase of the clock signal CLKout also approaches a certain preset phase. Therefore, in some embodiments, the detecting unit 11A can output the delay control voltage Vctrl or the clock signal CLK〇ut of the voltage-controlled delay line Mo as the debt measurement result DR. FIG. 5 is a schematic diagram showing functional blocks of the detecting unit 110 in the figure according to another embodiment of the present invention. The detecting unit 110 includes a phase locked loop (PLL). The phase locked loop includes a phase frequency detector (PFD) 510, a charge pump 52 〇, a low pass filter 530, and a voltage controlled oscillation. (Voltage: controlled 〇scmat〇r, VC0) 540 and a divider 5 50. The phase frequency detector 5 丨〇 receives and compares the phase and frequency of the % pulse k number CLKin and the feedback clock CLKfb. The charge pump 520 charges or discharges the low pass filter state 530 according to the comparison result of the phase frequency detector 51A. Therefore, the low pass chopper can provide the frequency control voltage Vctrl to the voltage controlled oscillator 540. The voltage controlled oscillation 540 is controlled according to the frequency control voltage vctri, and correspondingly generates the time signal 20118297 -0122-TW 33258twf.d〇c/n pulse signal CLKout. After the frequency divider 55 除 divides the clock signal clk (10), the signal is output as a feedback clock CLKfb to the phase frequency detection benefit 510. The above-mentioned phase-locked loop is a well-known technique, so the details in the basin will not be described again. _Back__ will change with the voltage. When the phase-locked loop is locked, the pulse signal CLKi is set to a voltage 'and the clock signal CLK= | will also approach a certain-pre-rate. Therefore, in some embodiments, the π 110 can be used to detect the frequency control of the voltage controlled oscillator 54 电 as the detection result dr. The figure is a schematic diagram of a functional module for detecting no in the figure according to another embodiment of the present invention. The detecting unit 11G includes a phase locked loop 61〇 j and a frequency comparator 62G. The phase-locked loop 61G can be referred to FIG. 5 and Xiang Longming. The frequency comparison state 620 is connected to the phase-locked loop 61〇. The phase of the clock signal CLKin can be locked, indicating that the input signal group = is a normal signal. When the phase-locked loop 61G is locked, the clock of the output clock of the _° back to _ is rarely fixed. Therefore the comparator .620 compares the frequency and 'rate of the output signal CLKQUt

Fref. The frequency comparator 62 〇 16 compares the result as a debt measurement result β value to the receiving unit 120. 1 Searching FIG. 7 is a schematic diagram showing the functional blocks of the detecting suppressor 110 in the drawing according to a further embodiment of the present invention. The debt measurement unit 11A includes a phase locked loop = late loop 710 and a voltage comparator 720. If 71〇 is a phase-locked loop, the phase-locked loop 71〇 can be implemented with reference to FIG. 5 and the related description, and the frequency control voltage Vctrl of the factory 401 is output to the voltage comparator=empty, 33258twf.doc/n 201138297 7H) is a lock-delay loop'. The lock delay = 1 〇 ' can be implemented with reference to FIG. 4 and the related description, and the delay of the voltage-controlled delay line 440 is controlled by the voltage comparator 720. 8 is a timing diagram showing a phase-locked loop (or a lock-up loop internal control voltage Vct read reference voltage Vref) according to an embodiment of the present invention. In the locking process of the phase-locked loop (or lock-delay loop), the control is controlled. Slowly descending from the second DD, when the lock is straight, the control voltage is fixed at a certain voltage value. Therefore, the present embodiment uses the voltage to compare the frequency control voltage (or delay control voltage) VcM with the vehicle feeder Wo. The reference voltage Vref. When the value of the control voltage Vctrl is less than the reference voltage, the detecting unit 11〇 can determine that the phase locked loop (or the lock delay loop) is locked, and transmits the comparison result to the receiving unit 12 as the detection result DR. FIG. 9 is a schematic diagram of a functional module of the receiving unit 12A of FIG. 1 according to another embodiment of the present invention. In this embodiment, the detecting unit 11() may be a phase locked loop or a lock delay loop. It is the frequency control voltage Vctrl of the internal voltage controlled oscillator 540 of the phase-locked loop (as shown in FIG. 5), and may also be the delay control voltage Vctrl of the internal voltage-controlled delay line 44〇 of the lock-up loop (as shown in FIG. 4). Unit 120 package The amplifier AMP, the first transistor, and the second transistor M2. The transistors M1 and M2 may be NMOS transistors or other types of transistors. The first input and the second round of the amplifier AMp receive input. The input signal pair of the signal group IN is iNp and INn. The control terminals of the transistors M1 and M2 receive the detection result dr (here, the control voltage Vctrl). The first end of the first transistor M1 is connected to the amplifier 20110297

—0122-TW 33258twf.doc/n An input, and the second end of the first transistor M1 is connected to the first voltage (eg, system voltage VDD). The first end of the second transistor M2 is coupled to the first input terminal ' of the amplified state AMP and the second terminal of the second transistor is coupled to the second voltage (e.g., ground voltage). When the control voltage Vctrl is larger, the resistance of the NM〇s transistors M1 and M2 is smaller, so that the sensitivity of the amplifier AMp is worse. When the control voltage Vctrl is small, the larger the resistance of the NM〇s f crystal M1盥^, the better the sensitivity of the amplifier AMP.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a schematic diagram of a functional block of a more compact 接收+receiver 夭 12〇 in accordance with the present invention. Figure U is a timing diagram illustrating the internal control voltage Vctrl and the reference voltage of the phase-locked loop (4) lock-up loop of Figure 1A. t This implementation of the financial, _ unit UG can be the age loop or lock avoidance ^ test results DR can be the phase-locked loop internal pressure control vibrator 54 〇 pressure Vctrl (as shown in Figure 5), can also be lock late The delay inside the loop ^ delay line 440 controls the voltage (10) (as shown in Figure 4). The receiving material m includes a voltage comparator _, an amplifier AMp, at least one

::Off, at least one first resistor, at least—the second switch, and at least one first: voltage= comparator 丨_ is connected to the price measuring unit 110 to receive the side voltage 1). Voltage comparator 1010 compares the results. At least the reference voltage value, and the output comparison ^ ^ open, the first resistor, the second turn will make the number of turns can be determined according to the design f. The real 'switch (ie SWM, coffee ^ 4 brothers - resistance (ie R1), R1_2, called, ri_4), 4 second 11 i^2-TW 33258twf.doc/n 201138297 (ie SW2-1, SW2 -2, SW2-3, SW2-4) and 4 first resistors (ie R2-1, R2-2, R2-3, R2-4). In addition, this embodiment will use four different levels of reference. The voltage values VI, V2, V3 and V4 are as shown in Fig. 11. The first input terminal and the second input terminal of the amplifier AMP receive the input signal pairs ΐΝρ and INn of the input signal group IN. The first resistor is connected in series with the first switch. At a first input of the amplifier AMP and a first voltage (eg, a system voltage)

Between VDD), for example, the first resistor R1-1 and the first switch SW1-1 are connected in series between the first input terminal of the amplifier AMP and the system voltage VDD, and so on, and the rest of the first resistors R1-2 RM and the rest. The first switches SW1-2 to SW1-4. The second switch and the second resistor are connected in series between the second input of the amplifier AMp and the second voltage (for example, a ground voltage), for example, the second resistor R2-1 and the second switch sww are connected in series with the first &amp of the amplifier AMp. Between the input terminal and the ground voltage, and so on, the remaining second resistors r2_2 to r2_4 and the remaining second switches SW2-2 to SW2-4. The voltage comparator 1〇1〇 compares the control voltages Vctrl盥夂 VI to V4' and outputs the comparison results S1, S2, S3 &>

According to the comparison result of the second switch, the second switch 2 and the second switch _ are determined according to the comparison result S3, and the second switch SW2-4 is compared with the second switch SW2-4 according to the comparison switch 1帛-switch SW. When the control voltage Vctrl A is determined to be the conduction side 1010 of the moxibustion W, the voltage is compared with the switch SW1-1~SW1_4, and all the first switches SW2-1~SW2 are turned on and off. -4导12 201138297,.υ12,τψ 3_ (turn οη). At this time, the resistance of the pull-up resistor and the pull-down resistor is the most common between the common-mode voltage of the first-input terminal of the amplifier AMP and the common-mode voltage, so the sensitivity is the worst. w, when the control voltage Vctrl is between the reference voltage V1 and the reference voltage (ie vi>Vctri>V2)' the voltage comparator 1〇1〇 will output the comparison result S by S1, S3 and S4 One switch SW1_4 and the second switch SW2-4 are turned off (turn 0 is all, and the remaining first switch two SW1-3 is turned on with the remaining first switches SW2-1~SW2-3. When the control voltage Vctd is between the reference voltage V2 and When the reference voltage V3 is between (i.e., V2 > Vcm > V3), the voltage comparator 1010 will switch the first switches SW1-3 to SW1-4 and the second switch by outputting the comparison results S1, %, %, and S4. §w2-3~SW2-4 are turned off and the first switches SWM to SW1-2 are turned on with the second switches SW2-1 to SW2-2. When the control voltage Vctri is between the reference voltage V3 and the reference voltage V4 ( That is, V3 > Vctrl > V4), the voltage comparator 1〇1〇 will switch the first switches SW1-2 to SW1-4 and the second switch SW2-2 by outputting the comparison results SI, S2, S3 and S4. SW2-4 is turned off, and the first switch SW1-1 and the second switch SW24 are turned on. When the control voltage Vctrl is smaller than the reference voltage 'V4', all the first switches SW1-1 to SW1-4 and all the second switches SW2-1 SW2-4 is cut off. At this time, the pull-up resistor and the pull-down resistor have the largest resistance value, that is, the common mode voltage of the first input terminal of the amplifier AMP is the smallest from the common mode voltage of the second input terminal, so the sensitivity is the best. The embodiment shown in Fig. 10 can gradually increase the sensitivity of the amplifier AMP depending on the degree of signal locking. 13 201138297

i22-TW 33258twf.doc/n Take the low voltage differential signal (LVDS) as an example. Figure 12 is a schematic diagram showing the work of the purely embossed money (LVDS) of the figure W, the receiver package (4), the single phantom 1G, and the four receiving UOmOf, 120_4) and the four latches (ie u, L2, L3, L4). The input signal group IN contains the first data signal to the mp disk, the signal pair mP and D2n, and the third data signal to the output == four dragons Xinlin mP and D4n which are called

The receiving unit has the data signals [Dip, Din]~[D4P, D4n] corresponding to each of the 12G-4. Among them, the debt test (4) „DR can adjust the receiving unit 12 (M~12 (the implementation of the receiving unit 120-1~120-4 of m, can be a spring day) as an example of the receiving unit 120. 拴 latch u~ L refers to the corresponding receiving unit 12〇_1~12 (M's input, 2nd and 2nd receive the output clock signal and the pick-up and receive order is based on the flip unit. The thief early coffee ~ 12 (M round

The debt measurement unit 110 includes an amplifier coffee and a lock delay circuit 1220. The connection of the amplifier 1210 (or the phase-locked DR is determined. The implementation of the amplifier is listed in the receiving unit (10). The amplifier receives the clock and the real-time clock signal Μn turns out to give the lock late loop (or phase-locked loop) The input of the 1220 is connected to the output of the amplifier. ^ phase 14 201138297— 33258twf.doc/n (or phase-locked loop) 1220 phase-locks the clock signal CLKin and provides the debt measurement result DR The receiving unit 12 (M to 12 (M disk amplification = two dynamic adjustment receiving units 12A) to 12 (M and amplification, sensitivity). Here, the method of dynamically adjusting the receiver sensitivity is performed. The method includes: detecting the phase of the input signal group IN, and outputting the detection result DR; receiving the input signal group IN with a sensitivity; and dynamically adjusting the sensitivity according to the detection result DR according to the spring. The input signal group IN includes "Yeah" In the application example of the pulse ## and a data signal, the step of "detecting the phase of the input signal group IN" may be the phase of the clock signal, the output side result DR', and the "sensitivity (4) Input signal group IN" The step may be that the data signal is received by the sensitivity. ― As described above, when the input end of the receiving unit 120 has no input signal or the signal is not connected (ie, floating), the input end of the receiving unit 12〇 has It may receive various kinds of noises. At this time, because the input signal group m is a choke, the detection unit 110 (for example, a phase-locked loop or a lock-delay loop) is beneficial. Therefore, the subtraction unit 12G is dynamic. The condition of the light recording degree. Because the sensitivity of the receiving unit 70 120 is reduced, most of the signals can be filtered out. Take the example of Figure 12 to make the phase-locked loop (or lock-delay loop) (four) locked with two Conditions: 1. The input clock signal must have a large energy, can pass, low sensitivity amplifier 121G; 2. It is necessary to maintain a fixed frequency of the wheel clock signal, in order to make the phase-locked loop (or lock-up loop) 122ΘLock. The frequency of one input 4 pulse s number changes, the phase-locked loop (or lock-delay loop) 1220 will return to the unlocked state. So, when the normal clock signal starts 15 201138297 jTW 33258twf.d〇 When c/n is input, 'because of the clock signal The energy is large and the frequency is fixed, so it can be input to the phase-locked loop (or lock-up loop) 1220 by the amplifier 1210 to lock the phase-locked loop (or lock-delay loop) 1220. At this time, the amplifier 1210 and the receiving unit 12 (M) 〜12()_4 will be adjusted to a high-sensitivity state, and the input of the feed IN will not be attenuated due to insufficient performance of the amplifier. Although the invention has been disclosed above by way of example, it is not intended to limit the invention 'any It is to be understood that the scope of the present invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram showing the functional blocks of a receiver capable of dynamically adjusting sensitivity according to an embodiment of the invention. 2 is a functional block diagram of the receiving unit of FIG. 1 according to another embodiment of the present invention. FIG. 3 is a schematic diagram of functional blocks of the receiving unit of FIG. FIG. 4 is a schematic diagram showing the function modules of the detecting unit of FIG. 1 according to an embodiment of the invention. FIG. 5 is a schematic diagram showing functional modules of the detecting unit of FIG. 1 according to another embodiment of the present invention. FIG. 6 is a schematic diagram showing functional modules of the detecting unit of FIG. 1 according to another embodiment of the present invention. 16 201138297· 33258twf.doc/n FIG. 7 is a schematic diagram showing the function module of FIG. 1 according to a further embodiment of the present invention. H early _ FIG. 8 is a timing diagram showing the phase-locked loop (or the lock-up loop internal control voltage Vctrl and the reference voltage Vref) according to an embodiment of the present invention. FIG. 9 is a diagram illustrating the γ function of FIG. 1 according to still another embodiment of the present invention. Fig. 10 is a schematic diagram of a functional module in the figure according to a further embodiment of the present invention. Fig. 11 is a diagram showing the voltage and reference voltage of the phase-locked loop (or lock-up loop) of the head 10 Schematic diagram of the timing diagram. Figure 12 is a schematic diagram illustrating the function module for applying the receiver shown in Figure i to low voltage (LVDS). Cut 15戚 [Main component symbol description] 100, 1200: Receiver 110: Detection unit • 12 〇, 120-1 ～ 120-4: receiving unit 410: phase detector 420, 520: charge pump 430, 530: low pass filter 440: voltage controlled delay line 510. phase frequency predator 540: voltage control Oscillator 550: Frequency divider 17 201138297, TW 33258twf.doc/n 610: Phase-locked loop 620: Frequency comparator 710, 1220: Phase-locked loop or lock-up loop 720, 1010: Voltage comparator 1210, AMP: Amplifier Clock signals CLKin, CLKout, CLKfb, CLKp, cLKn CS1 CS2: current source DR: detection results

Fref : Reference frequency II, 12 : Current IN : Input signal group INp, INn : Input signal

Dip, Din, D2p, D2n, D3p, D3n, D4p, D4n: data signal LI~L4: 拴 latch M1, M2: transistor OUT: output signals R1 ~ R2, R1-1 ~ ri_4, R2-1 ~ R2 -4 : Resistor S1 to S4 : Comparison result SW1-SW2, SW1-1 to SW1-4, SW2-1 to SW2-4: Switch

Vctrl: control voltage

Vref, VI~V4: reference voltage

Claims (1)

201138297 7-0122-TW 33258twf.doc/n VII. Patent application scope: L A receiver includes: a detecting unit that detects an input signal group 'and outputs a detection result; and — a receiving unit, The sensitivity receives the input signal group 'where the receiving unit dynamically adjusts the sensitivity according to the detection result. 2. The receiver of claim 1, wherein the receiving unit comprises: an amplifier, a first input end and a second input end receiving the input k 7 tiger group; Determining, according to the detection result, the first switch is turned on or off; - the first resistor is connected to the first resistor and the first resistor is connected between the first input terminal and the first voltage; - the second switch 'determines that the second switch is turned on or off according to the detection result; and - a second resistor 'the second switch and the second resistor are connected in series with the second input of the amplifier - Between the second voltages. 3. The receiver of claim 1, wherein the receiving unit comprises: - an amplifier 'the wheel receiving end receives the input signal group; _ - the first current source, determining a first according to the detection result a current amount of current, and the first current is supplied to the first power terminal of the amplifier; and 19 i22-TW 33258twf.doc/n 201138297 a first current source 'determined according to the detection result-- The receiver power supply unit of the first aspect of the present invention includes: a "wei" device, and a second current source. The first input end and a second input receive the first transistor, and the control end receives the detection result, the first end of the crystal is connected to the first round of the amplifier The first end is connected to a first voltage; and the aa is a second transistor, the control end thereof receives the detection result, and the first end of the crystal is connected to the second wheel end of the amplifier, and the second body is The second end is connected to a second voltage.曰5· The receiver of claim 1, wherein the unit comprises: , a ^^--voltage comparator connected to the (four) measuring unit to receive the detecting result, the voltage comparator comparing the detecting The resulting voltage value and at least - the voltage value, and output a comparison result; ', the evening - amplifier m human end and the second input end receive the round signal group; at least - the first switch, according to the comparison result Determining that the first - is turned on or off; at least one first resistor, the first switch and the first resistor are connected in series between the first input end of the amplifier and a first voltage; X 20 201138297 - 33258twf.doc / n at least one second switch is turned on or off; and at least one second resistor 'between the second switch and the second input terminal of the second amplifier and a second voltage. The receiver of claim 1, wherein the input group includes a clock signal and a data signal, and the detecting unit extracts the The surface output is still fruitful, and the receiving unit _$ sensitivity receives the poor material signal. The receiver of claim 6, wherein the detection port comprises a lock delay circuit, and the lock delay circuit receives the clock signal. Material HI, please refer to the delay control voltage of a voltage controlled delay line in the _*, ,, k lock delay circuit described in item 7 of the patent scope. Unit It is requested to receive 11 of the full-time (4) 7 items, of which Determining, according to the comparison result, the third order 'connected to the lock delay loop to receive the lock delay loop delay control lightning (four) ^ " 7 delay control voltage, the voltage comparator compares the fruit transmission i to the single J test voltage ' And the comparison result is taken as the detection and test unit package 6 pin, where the u·such as the application for the special test result is the receiver of the object loop, wherein the frequency of the application of the special vibration device Control voltage. The measuring unit further comprises: a receiver according to 10th, which is the 201138297』_TW 33258twf.d〇c/n. The frequency comparison is connected to the output end of the phase-locked loop, and the frequency comparator compares the frequency of the output signal of the phase-locked loop with the reference frequency, and transmits the comparison result to the receiving unit as the detection result. 13. The receiver of claim 1, wherein the measuring unit further comprises:, a voltage ratio kH, connected to the shooting phase loop to reduce the phase locked loop - voltage controlled oscillation | Controlling the voltage, the electric current comparator compares the frequency control voltage with the reference voltage, and transmits the comparison result to the receiving unit as the detection result. Η 如 如 申请 申请 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如Amplifying the gain, receiving the clock signal with the sensitivity; and - a lock-up loop, wherein the input end of the loop is connected to the amplifier, wherein the 5-lock delay circuit provides the detection result to the receiving unit and the amplification benefit, To adjust this sensitivity dynamically. 15. The receiver of claim 2, wherein the wheeled signal group comprises a clock signal and a data signal, the receiving unit receives the data signal with the sensitivity, and the detecting unit comprises: An amplifier that receives the clock signal with the sensitivity; and - a phase-locked loop 'the end of the phase loop is connected to the amplifier 22 201138297 0122-TW 33258twf.d〇c/n where the phase loop provides the service to the Decrease the unit to dynamically adjust the sensitivity. 〇孩玫16. A method for dynamically adjusting the sensitivity of a receiver, comprising: detecting a phase of an input signal group, and outputting a detection result·; receiving the input signal group with a sensitivity; and dynamically according to the detection result Adjust this sensitivity. The method of adjusting the sensitivity in the method of the sensitivity range 16th dynamic adjustment Weiering & amp includes: when the phase of the input signal group is not locked, an amplification of both the 'slave end and the second input end The common mode voltage is pulled apart; and the first phase is locked, and the common mode voltage of both the input and/or the input of the amplifier is not pulled. The method of dynamically adjusting the receiver's sensibility as described in item 16 of the /2 bis range, 'the step of adjusting the sensitivity includes: the phase of the == is not locked' will be - the signal group of the power supply end of the amplifier The phase has been locked. The power supply of the amplifier is said to be ', ', and (4) i ̄ ̄ = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = The clock 'outputs the side result' and the step of receiving the 1 h group with sensitivity is to receive the data signal with the sensitivity. twenty three