TWI450257B - Thin film transistor liquid crystal display driving method and device - Google Patents

Description

Driving method and device for thin film transistor liquid crystal display

The present invention relates to the field of liquid crystal display, and more particularly to a driving method of a TFT liquid crystal display and a TFT liquid crystal display.

Referring to FIG. 1 , a liquid crystal display panel (LCD Panel) 120 using a Thin Film Transistor (TFT) 103 as a switching element and an external driving device thereof: a gate driver 200, a source driver (Source Driver) 300, a common electrode driver (Vcom Driver) 400. The conventional liquid crystal display panel 120 is composed of an upper substrate 100, a lower substrate 110, and a liquid crystal layer (not shown) interposed between the two substrates. The upper substrate has a thin film transistor 103, a plurality of data transmission lines VS ₁ to VS _N connected to the source of the thin film transistor 103, and a plurality of scanning lines VG ₁ to VG _M connected to the gate of the thin film transistor 103, and the thin film transistor 103 is connected to the drain. The pole element electrode 102. Placed on the lower substrate is a common electrode 111, and a drive line vcom connecting the common electrode and the common electrode driver 400.

Referring to FIG. 2, which is an equivalent circuit of a primitive 101, according to actual physical properties, the circuit characteristic of the two-layer substrate can be regarded as an equivalent storage capacitor (Cst) 104, and the two poles of the storage capacitor 104 are the common electrode 111 and the diagram, respectively. Element electrode 102.

The driving method of the conventional liquid crystal display 120 is simply described as follows: the row scanning signals VG ₁ to VG _M generated by the gate driver 200 control the on and off of the thin film transistor 103. The level of the data signals VS ₁ ~VS _N generated by the source driver 300 represents different color information. When the line scan signal arrives, the corresponding row of thin film transistors 103 is turned on, and the data signals VS ₁ to VS _N charge the storage capacitor 104 via the thin film transistor 103, and the potential difference across the storage capacitor 104 changes the arrangement of the liquid crystal molecules and Corresponding to the transmittance of the light in that area, thus determining the gray scale of each primitive point. When the line scan signal turns off the thin film transistor, the voltage difference between the picture element electrode and the common electrode remains unchanged until the next scan signal arrives due to the storage effect of the storage capacitor on the charge, so the picture is periodically updated according to the scan signal. .

Referring to FIG. 3, it is a driving waveform of a conventional TFT liquid crystal display. The waveforms of the common electrode voltage VCOM and the source drive voltage VS change in the same cycle, and the driving period t1 → te1 → t2 → te2 is one scanning period (the period is T). The common electrode VCOM is driven to the low common electrode potential vcoml 408 during the t1 period; to the potential vci 501 during the te1 period; to the high common electrode potential vcomh 407 during the t2 period; to the ground potential gnd 502 during the te2 period. The source driving terminal VS is driven to the positive polarity gray scale potential vsp during the t1 period; to the system input power supply potential vci 501 during the te1 and te2 periods; and to the negative gray scale potential vsn during the t2 period.

FIG. 4 shows the principle of a conventional source driver 300. The conventional source driver 300 includes a gray scale voltage generator 302, a switch matrix 303, and an output drive buffer (used as a unity gain operational amplifier, hereinafter referred to as a buffer) op 301. The power rail of the array, output buffer is avdd 503 and ground gnd 502. The switch array 303 selects and outputs different gray scale potentials to the output buffer according to the control signal, so that the source driving voltage VS varies within the gray scale potential range. In addition, switches sw1 305, sw2 304 are added for power saving operation. As previously described for the driving waveform of a conventional liquid crystal display, the switch sw1 305 is closed during the t1 and t2 driving periods, the switch sw2 304 is turned off, and the source driving output outputs a positive (negative) polarity (vsn or vsp) gray scale. The potential is turned on, and in the period of te1 and te2, the switch sw2 304 is closed, the switch sw1 305 is turned off, and the source driving output terminal outputs the potential vci 501.

FIG. 5 shows the structure of the common electrode driver 400. The high common electrode potential vcomh 407 is output to the common electrode output terminal VCOM via the output buffer opap 401 and the control switch sw4 403, and the low common electrode potential vcom1 408 is output to the common electrode output terminal VCOM via the output buffer opan 402 and the control switch sw7 406. . During the t1 driving period switch sw7 406 is closed, sw4 403, sw5 404, sw6 405 are disconnected, the common electrode output terminal vcom is driven by the output buffer opan 402 to the low common electrode potential vcoml 408; the switch sw5 404 is closed during the te1 driving period , sw4 403, sw6 405, sw7 406 disconnected, the common electrode output terminal VCOM is driven to the input power supply potential vci 501; during the t2 driving time period switch sw4 403 is closed, sw5 404, sw6 405, sw7 406 is disconnected, common electrode output The terminal VCOM is driven by the output buffer opap 401 to the high common electrode potential vcomh 407; during the te2 driving period switch sw6 406 is closed, sw4 403, sw5 404, sw7 406 are disconnected, and the common electrode output terminal VCOM is driven to the ground potential gnd 502, Thereafter, t1→te1→t2→te2 is repeated.

FIG. 6 shows a drive wafer power architecture portion 500. The input power of the chip is vci 501, and the ground of the chip is gnd 502. The system input power generates a positive high voltage power supply vgh 505 via a charge pump 510, and a negative high voltage power supply vgl 506 powers the Gate Driver. The positive and medium voltage power supply avdd generated by the charge pump supplies power to the VCOM Driver and Source Driver, and generates a negative medium voltage power supply vcl (usually -vci) to the VCOM Driver to generate a low common electrode potential vcoml 408.

According to the circuit operation of the conventional driving method, the power consumption of each stage of driving one cycle T is analyzed as follows. For a concise analysis process, Figure 7 shows an equivalent circuit for a conventional drive method power analysis. As shown in FIG. 7, the panel is equivalent to a capacitor C, and the two ends of the capacitor C are VS _N and VCOM, respectively. Table 1 shows the charge stored at the potential and capacitance across the panel capacitor when driving the steady state at each stage.

As can be seen from the table:

During the t1→te1 phase, this process releases all of the charge on capacitor C, eliminating the need for power to provide power.

In the stage of te1→t2, the process output buffer opap 401 and the output drive buffer op 301 charge the panel capacitor C, the current flows from the power supply avdd to the capacitor C via the buffer opap 401, and then flows to the system via the buffer op 301. Gnd, so this process consumes the power provided by the power avdd via the buffer opap 401.

The charge change is: ΔQ=C*(vsn-vcomh)

The average current is:

The average power consumption is:

Note that here vcomh>vsn.

In the t2→te2 phase, the external system power supply vci directly charges the capacitor C, and the current flows from the vci through the panel capacitor C to the system ground gnd, so only the external system power supply vci provides power consumption.

The charge change is: ΔQ=C*(vci-vsn+vcomh);

The average current is:

The average power consumption is:

Note that here vci>vsn-vcomh.

During the te2→t1 phase, the process source drive output buffer op 301 and common electrode output buffer opan 402 charge the capacitor. This current flows from avdd 503 via output buffer op 301 to panel capacitor C, and then through buffer opan. 402 flows to the system negative power supply vcl 504, so this process consumes the power consumption of the two power supplies, namely the medium voltage supply avdd 503 and the negative medium voltage supply vcl 504.

The charge change is: ΔQ=C*(vsp-vcoml-vci)

The average current is:

The average power consumption of the two power supplies is:

Combining the power consumption of the first four conversion processes, the total power consumption of one cycle T is:

P(total)=P(opap)+P(vci)+P(op)+P(opan)

Since the medium voltage power supply avdd and the negative medium voltage power supply vcl are both generated by the external system power supply vci via the charge pump, assuming that the efficiency of vci to generate avdd is η1 and the efficiency of vci to generate vcl is η2, the total power consumption can be written as:

At present, the conventional driving method still has shortcomings in the power saving mode, and the energy saving effect is not good enough.

An object of the embodiments of the present invention is to provide a driving method for a TFT liquid crystal display, which aims to solve the problem that the conventional driving method is not energy-saving.

In view of this, in an aspect of the present invention, an embodiment provides a driving method of a thin film transistor (TFT) liquid crystal display, wherein a source driving end and a common electrode are repeatedly driven by a potential signal of a scanning period, and the method scans The cycle includes the following steps:

(A) in the first period of time, the source driving end is driven to a positive gray scale potential vsp, and the common electrode is driven to a low common electrode potential;

(B) in the second period of time, the source driving end is driven to a ground potential, and the common electrode is driven to a ground potential;

(C) in the third period of time, the source driving end is driven to a potential vsn-Δv, and the common electrode is driven to a system input power supply potential, wherein the vsn is a negative gray scale potential;

(D) in the fourth period of time, the source driving end is driven to the negative gray scale potential vsn, and the common electrode is driven to a high common electrode potential;

(E) in the fifth period of time, the source driving end is driven to a ground potential, and the common electrode is driven to a ground potential;

(F) in the sixth period, the source driving end is driven to a potential vsp-Δv, and the common electrode is driven to a ground potential;

Where Δv is a preset potential value, and 0<Δv<vsn/vsp.

In another aspect of the present invention, another embodiment provides a driving device for a thin film transistor (TFT) liquid crystal display, including a source driver, a common electrode driver, and a gate driver, wherein the source driver includes: a gray scale potential generator; a switch array; an output drive buffer; a first switch connected to the output drive buffer; a second switch connected to the system input power potential; an N-type metal oxide field effect transistor And connecting the second switch; a P-type metal oxide field effect transistor connected in series with the N-type metal oxide field effect transistor; and a third switch connected to the ground.

The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It is understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

8 is a diagram showing a driving method of a TFT liquid crystal display according to an embodiment of the present invention. The common electrode voltage VCOM and the source driving voltage VS waveform are changed in the same cycle, and the driving time period t1→te1→te2→t2→te3→te4 is one scan. Cycle (set the period to T). The common electrode VCOM is driven to the low common electrode level vcoml during the t1 period, driven to the ground potential gnd during the te1 period, driven to the system input power supply potential vci during the te2 period, and driven to the high common electrode during the t2 period The potential vcomh is driven to the ground potential gnd during the te3 and te4 periods. The source driving terminal VS is driven to the positive polarity gray scale potential vsp during the t1 period, to the ground potential gnd during the te1 period, and to the potential vsn-Δv (Δv) during the te2 period. 0, the size can be adjusted), is driven to the negative gray scale potential vsn during the t2 period, is driven to the ground potential gnd during the te3 period, and is driven to the potential vsp-Δv during the te4 period, after which t1→te1→ Te2→t2→te3→te4.

FIG. 9 shows a source-driven circuit structure 310 provided by a first embodiment of the present invention. The source driving structure adds a voltage boosting device (LS 307), an N-type metal oxide field effect transistor (NMOS) 308, and a P-type metal oxide field effect transistor (PMOS) 309 to the existing source driving. And the grounding switch sw3 306.

During the t1 and t2 driving period, the switch sw1 305 is closed, and the switches sw2 304 and sw3 306 are disconnected from the source to be driven by the output buffer to the target potential (positive gray scale potential vs or negative gray scale potential vsn); at te1 and te3 The driving time period switch sw3 306 is closed, the switches sw1 304, sw2 305 are disconnected, the source is driven to the ground potential; the switch sw2 304 is closed during the te2 and te4 driving period, the switches sw1 305, sw3 306 are disconnected, and the gray scale of the input is turned The potential is boosted by a voltage boosting device (LS 307) and input to the gates of NMOS 308 and PMOS 309, where NMOS 308 and PMOS 309 serve as source follower, source of NMOS 308 and PMOS 309 (ie, source drive output) VS1, VS2...VSN) There is a gate voltage difference VGS relative to the gate, so the target output potential is changed to vsn-Δv or vsp-Δv (Δv) via LS 307 and source follower NMOS 308. Changed by LS 307 as needed).

FIG. 10 shows a circuit structure of a source driver according to a second embodiment of the present invention. The main difference between the second embodiment and the first embodiment is that the second embodiment removes the voltage boost on the basis of the first embodiment. The device (LS 307) is closed during the t1 and t2 driving period switches sw1 305, the switches sw2 304, sw3 306 are disconnected, and the source is driven by the output buffer to the target potential (positive gray scale potential vsp or negative gray scale potential vsn) In the te1 and te3 driving time period switch sw3 306 is closed, the switches sw1 304, sw2 305 are disconnected, the source is driven to the ground potential; in the te2 and te4 driving time period switch sw2 304 is closed, the switches sw1 305, sw3 306 are off On, the input gray scale potential is directly output to the gates of NMOS 308 and PMOS 309, and NMOS 308 and PMOS 309 are also used here as source follower devices, so the sources of NMOS 308 and PMOS 309 (ie, source drive output VS1) , VS2...VSN) There is still a gate voltage difference VGS relative to the gate, the target output potential is changed to vsn-Δv or vsp-Δv via the source follower device NMOS 308, and PMOS 309 can be based on NMOS 308 And the size of the PMOS 309 is adjusted).

In the driving method provided by the present invention, since the driving potential is the same as the conventional method when the common electrode VCOM is operated in the power saving mode, that is, the system input power supply potential VCI 501 and the ground potential gnd 502 are utilized, so the conventional method is The common electrode driving structure 400 can still be used in the new method, but needs to be modified in the timing operation, the specific operation is as follows: the switch sw7 406 is closed during the t1 driving period, the switches sw4 403, sw5 404, sw6 405 are disconnected, The common electrode is driven to the low common electrode potential vcoml 408 by the output buffer opan 402; the switch sw4 403 is closed during the t2 driving period, the switches sw5 404, sw6 405, sw7 406 are turned off, and the common electrode is driven by the output buffer opap 401 to the high common Electrode potential vcomh 407; at te1, te3, te4 driving period switch sw6 405 is closed, switches sw4 403, sw5 404, sw7 406 are disconnected, common electrode is driven to ground potential gnd 502; switch sw5 404 is closed during te2 driving period The switches sw4 403, sw6 405, sw7 406 are disconnected, and the common electrode is driven to the system input power supply potential vci 501.

In the present invention, the new driving method simultaneously turns on the common electrode driving terminal VCOM and the source driving terminal VS to the ground potential gnd 502 in the power saving mode processing, thereby discharging the charge stored in the display capacitor on the display screen. Then, the source driver terminal VS is directly driven to the target gray scale potential (vsn or vsp) by the external input power source vci 501, and finally the source driver terminal is driven to the target gray scale potential through the output buffer op 301, the common electrode After the load capacitance is turned on to the ground potential gnd 501, the external power source is directly driven to the target potential (vcoml or vcomh), and then driven to the target potential by the output buffer.

The driving method of the TFT liquid crystal display provided by the present invention has the following beneficial effects: the processing method of directly grounding both ends of the load capacitor (source VS and common electrode VCOM) is more power-saving.

The source driver can be driven to the target potential according to the target gray scale potential, and then driven to the target potential by the output buffer, and the conventional source driver is driven to the system input potential vci 501 regardless of the target potential. If the next gray level potential is lower than vci 501, power consumption is wasted.

According to the above analysis of the circuit operation of the driving method of the present invention, the power consumption of each stage of driving one cycle T is analyzed as follows. For the sake of brevity of the analysis process, FIG. 11 shows an equivalent circuit of power consumption analysis of the driving method of the TFT liquid crystal display provided by the present invention. As shown in FIG. 11, the panel is equivalent to a capacitor C, and the two ends of the capacitor C are VS _N and VCOM, respectively. Table 2 shows the charge stored at both ends of the panel capacitor and the charge stored in the capacitor when the system is driven at various stages.

During the t1→te1 phase, this process releases all of the charge on capacitor C, eliminating the need for power to provide power.

In the te1→te2 phase, the external system power supply vci charges the panel capacitor C, and the current flows from vci through the capacitor C and then from the source driven source follower device PMOS 309 to the system ground gnd.

The charge change is: ΔQ=C*(vsn-Δv-vci)

The average current is:

The average power consumption is:

In the stage of te2→t2, the process output buffer opap 401 and the output drive buffer op 301 charge the panel capacitor C, the current flows from the power supply avdd to the capacitor C via the buffer opap 401, and then flows to the system via the buffer op 301. Gnd, so this process consumes the power provided by the power avdd via the buffer opap 401.

The charge change is: ΔQ=C*(vsn-Δv-vci-vsn+vcomh)=C*(vcomh-Δv-vci)

The average current is:

In the t2→te3 phase, this process pulls all the ends of the capacitor C to the ground, and the charge on the capacitor C is completely released, without the power supply providing power consumption.

In the te3→te4 phase, the external system power supply vci is charged to the panel capacitor C via the source swf device NMOS 308 in the source driver, and the current flows from the vci to the capacitor C via the source of the source follower NMOS 308, and then It flows to the system ground gnd via the switch sw6 405 in the common electrode driver, so this process consumes the power consumption provided by the external system power supply vci.

The charge change is: ΔQ=C*(vsp-Δv)

The average current is:

The average power consumption is:

In the stage of te4→t1, the process output drive buffer op 301 and output buffer opan 402 charge the panel capacitor C, current flows from the medium voltage source avdd 503 to the capacitor C via the output drive buffer op 301, and then passes through the output buffer. The opan 402 flows to the negative medium voltage source vcl 504, so this process consumes the power consumption of the two power supplies, namely the medium voltage supply avdd 503 and the negative medium voltage supply vcl 504.

The charge change is: ΔQ=C*(vsp-Δv)

The average current is:

The average power consumption is:

The above is only the preferred embodiment of the present invention, and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection of the present invention. Within the scope. For example, the elements or units used in the various embodiments can be modified and implemented by those skilled in the art, without departing from the scope of the invention.

100. . . Upper substrate

110. . . Lower substrate

101. . . Primitive

102. . . Element electrode

103. . . Thin film transistor

104. . . Storage capacitor

111. . . Common electrode

120. . . LCD panel

200. . . Gate driver

300. . . Source driver

301. . . Buffer (OP) array

302. . . Gray scale potential generator

303. . . Switch array

305. . . Switch sw1

304. . . Switch sw2

306. . . Switch sw3

307. . . Voltage booster (LS)

308. . . N-type metal oxide field effect transistor (NMOS)

309. . . P-type metal oxide field effect transistor (PMOS)

400. . . Common electrode driver

401/402. . . Output buffer opan

403. . . Switch sw4

404. . . Switch sw5

405. . . Switch sw6

406. . . Switch sw7

407. . . High common electrode potential vcomh

408. . . Low common electrode potential vcoml

409. . . Common electrode potential VCOM generator

501. . . System input power potential vci

502. . . Ground potential gnd

503. . . Buffer power rail avdd

T1→te1→te2→t2→te3→te4. . . Drive time period / T scan period

VCOM. . . Common electrode voltage

VS. . . Source drive voltage

Vsn. . . Negative gray scale potential

Vsp. . . Positive gray scale potential

Gnd. . . Ground potential

△v. . . Preset potential value

Vcomh. . . High common electrode potential

Vcoml. . . Low common electrode potential

1 is a schematic structural view of a TFT liquid crystal display provided by a prior art;

2 is an equivalent circuit diagram of a primitive provided by the prior art;

3 is a driving waveform diagram of a TFT liquid crystal display provided by a prior art;

4 is a structural diagram of a source driver provided by a prior art;

5 is a structural diagram of a common electrode driver provided by a prior art;

6 is a partial diagram of a driver chip power architecture provided by the prior art;

7 is an equivalent circuit of a power consumption analysis of a driving method provided by the prior art;

8 is a waveform diagram of a driving method of a TFT liquid crystal display according to an embodiment of the present invention;

9 is a circuit structure of a source driver according to a first embodiment of the present invention;

10 is a circuit structure of a source driver according to a second embodiment of the present invention;

11 is an equivalent circuit of power consumption analysis of the driving method provided by the present invention.

T1→te1→te2→t2→te3→te4. . . Drive time period / T scan period

VCOM. . . Common electrode voltage

VS. . . Source drive voltage

Vsn. . . Negative gray scale potential

Vsp. . . Positive gray scale potential

Gnd. . . Ground potential

△v. . . Preset potential value

Vcomh. . . High common electrode potential

Vcoml. . . Low common electrode potential

Claims (2)

A driving method of a thin film transistor (TFT) liquid crystal display, wherein a source driving end and a common electrode are repeatedly driven by a potential signal of a scanning period, and the scanning period of the method comprises the following steps: (A) in the first time period, The source driving end is driven to a positive gray scale potential vsp, and the common electrode is driven to a low common electrode potential; (B) in the second period of time, the source driving end is driven to a ground potential, and The common electrode is driven to a ground potential; (C) the third driving period is driven to a potential vsn-Δv, and the common electrode is driven to a system input power potential, wherein the vsn a negative gray scale potential; (D) in the fourth period, the source driving end is driven to the negative gray scale potential vsn, and the common electrode is driven to a high common electrode potential; (E) in the first The fifth driving period is driven to the ground potential, and the common electrode is driven to the ground potential; and (F) the sixth driving period is driven to a potential vsp-Δ v, and the common electrode is driven to a ground potential; wherein the Δv It is a preset potential value, and 0 < Δv < vsn / vsp. The driving method of claim 1, wherein before the step (A), the method further comprises: releasing the charge stored in the load capacitance of the TFT liquid crystal display.