TWI449135B - Mems and a protection structure thereof - Google Patents

Description

MEMS and its protection device

The invention discloses a protection device, in particular a protection device applied to a microelectromechanical system and a contact pad.

With the development of technology and the development of semiconductor technology, electronic components have been successfully applied to various aspects of life. Micro-electro-mechanical system (MEMS) technology is a process for manufacturing micro-mechanical components by a conventional semiconductor process, and a micro-sized mechanical component can be completed by semiconductor technology such as electroplating or etching. Common applications include voltage control components used in inkjet printers, gyroscopes used to detect car tilt in automobiles, or diaphragms used to sense sound in microphones. Since the MEMS technology can integrate the mechanical structure and the electronic circuit, it can be batch-made, and has the advantages of low cost, high quality, and high integration.

Currently, MEMS are integrated on a single wafer using the concept of system on chip (SOC), especially in a standard complementary metal oxide semiconductor (CMOS) process, such as in the same die (die) The MEMS region and the CMOS region are simultaneously formed. In the process of integrating existing CMOS and MEMS systems, many problems may arise, such as how to avoid process interactions and subsequent product use between regions when forming processes to form CMOS area components or forming MEMS. The interference with each other is a problem that must be studied and solved at present.

The invention thus proposes a protection structure, in particular a protection device applied at the interface between the microelectromechanical region and the non-microelectromechanical region, or applied to the contact pads in the non-microelectromechanical region, to ensure the microelectromechanical region and the non-micro in the semiconductor process. The electromechanical areas do not interfere with each other.

According to the scope of the patent application, the present invention provides a protective device for a contact pad. The contact pad is disposed in a dielectric layer on a semiconductor substrate, and the contact pad includes a connection region and a peripheral region surrounding the connection region. The protective structure comprises at least one retaining wall, an insulating layer and a mask layer. The retaining wall is disposed in the dielectric layer on the peripheral area and surrounds the connecting area. The insulating layer is disposed on the dielectric layer. The mask layer is disposed on the dielectric layer and covers the insulating layer and has an opening to expose the connection region of the contact pads.

According to the scope of the patent application, the present invention further provides a semiconductor structure including a semiconductor substrate, a dielectric layer, a protective structure, and a mask layer. The semiconductor substrate includes a microelectromechanical region and a non-microelectromechanical region, and the dielectric layer is disposed on the semiconductor substrate. The protection structure is disposed between the MEMS region and the non-microelectromechanical region, and includes a first metal layer disposed on the top metal layer of the dielectric layer, at least one dielectric layer disposed on the top metal layer, and a first barrier An insulating layer disposed on the dielectric layer. The mask layer is disposed on the dielectric layer and covers the insulating layer.

The protection structure proposed by the invention is suitable for the contact pad or the interface between the microelectromechanical system and the non-micro electro mechanical system, and the closed protection structure can effectively avoid the erosion of the etching gas such as hydrofluoric acid, and can protect the components in the non-microelectromechanical region. Will be destroyed and improve product yield and reliability.

Please refer to FIG. 1 . FIG. 1 is a schematic plan view showing a microelectromechanical region and a non-microelectromechanical region according to a preferred embodiment of the present invention. Here, a die is taken as an example to illustrate the application of the present invention. The MEMS and contact pad protection devices are still implemented in a wafer containing a plurality of dies. As shown in FIG. 1, a MEMS region 100 and a non-microelectromechanical region 102 are provided on a die 50. The microelectromechanical region 100 is provided with various microelectromechanical components (not shown), such as a diaphragm, a motor, etc., while the non-microelectromechanical region 102 can be a logic region, a memory region or a peripheral circuit region, etc., in which various semiconductors are disposed. Components (not shown), such as various active or passive components. The surface of the non-microelectromechanical region 102 has a plurality of contact pads 104 that allow external signals to pass through the corresponding contact pads 104 to drive components within the non-MEMS region 102 and perform input/output of the respective signals.

Generally, in the preparation of a microelectromechanical device, after completing all kinds of semiconductor processes such as microelectromechanical components, semiconductor components, and metal interconnects, the system wafer is subjected to at least one etching process to etch gas (for example, hydrofluoric acid). An etchant such as (HF)) or an etching solution removes the inter-metal dielectric layer (IMD) in the microelectromechanical region 100 to form various movable or spatial microstructured mechanical components in the microelectromechanical region 100. In order to ensure that the etching proceeds, the etchant does not penetrate the non-micro-electromechanical region 102 via the edge of each contact pad 104 or via the interface between the microelectromechanical region 100 and the non-microelectromechanical region 102, thereby destroying the components in the non-microelectromechanical region 102. . Accordingly, the present invention provides a protection device that can be applied to the interface between the microelectromechanical region 100 and the non-microelectromechanical region 102, or to the contact pads 104 in the non-microelectromechanical region 102.

First, the protection device of each contact pad 104 in the non-micro-electromechanical region 102 is taken as an example. Referring to FIG. 2, FIG. 2 is a cross-sectional view showing a contact pad protection structure according to a preferred embodiment of the present invention. Draw along the line AA' in Figure 1. As shown in FIG. 2, a dielectric layer 112 and a contact pad 104 are disposed on the semiconductor substrate 106 of the die 50. The material of the dielectric layer 112 may be yttrium oxide (SiO2), tetraethoxy decane (TEOS), plasma reinforced tetraethoxy decane (PETEOS) or various interlayer dielectric materials. The contact pads 104 disposed in the dielectric layer 112 may comprise various conductive materials such as metal tungsten, aluminum or copper. In addition, the contact pad 104 includes a connection region 108 and a peripheral region 110. The connection region 108 is defined as a region where the contact pad 104 is exposed, so that the contact pad 104 located therein is exposed to facilitate subsequent package process wiring. The solder joint is required, and the peripheral area 110 surrounds the connection area 108. Please refer to the illustration in FIG. 1 together.

As described above, in order to ensure etching, the etchant 122 erodes the dielectric layer 112 of the peripheral region 110, thereby infiltrating and destroying the components inside the non-microelectromechanical region 102. The preferred embodiment has a design on each of the contact pads 104. Protection structure. The protective structure includes at least one retaining wall 116, an insulating layer 118, and a mask layer 120. As shown in FIG. 2, after the process of the contact pad 104 is completed, for example, a via plug or the like can be used to fabricate the desired retaining wall 116, and the retaining wall 116 is disposed on the peripheral region 110. The electrical layer 112 surrounds the connection region 108; the insulating layer 118 is disposed on the dielectric layer 112 and the barrier wall 116.

The retaining wall 116 is a continuous annular structure, and the material thereof may include metal tungsten, metal aluminum, amorphous silicon or silicon nitride or other etchant resistant to hydrofluoric acid (HF). 122 etched material. The retaining wall 116 encloses the connecting region 108 in the planar layout structure of FIG. 1 and exposes the connecting region 108 of the contact pad 104; and in the vertical structure illustrated in FIG. 2, the retaining wall 116 is in substantial upward contact. The insulating layer 118, in turn, substantially contacts the contact pads 104, thereby forming a complete and closed protective structure, thereby effectively preventing the etchant 122 from penetrating into the non-microelectromechanical regions 102 from the periphery of the contact pads 104. The protective structure of the present embodiment may have a single retaining wall 116 or, as the case may be, a plurality of retaining walls 116 disposed in parallel with each other between the insulating layer 118 and the contact pads 104 and collectively surrounding the connecting region 108. The planar layout of the retaining wall 116 may be a closed structure of various polygons, circles, etc. Please refer to FIG. 3, which is a schematic diagram of an embodiment of the planar layout of the retaining wall of the present invention. As shown in Fig. 3, the retaining wall 116 is a polygon. Preferably, the polygon has an internal angle α of about 130 degrees.

The material of the insulating layer 118 includes amorphous germanium or tantalum nitride. The material of the insulating layer 118 and the retaining wall 116 may be the same as the product requirements, for example, the same is amorphous, but may be different. For example, the insulating layer 118 is amorphous. And the retaining wall 116 is metal tungsten. The insulating layer 118 covers the retaining wall 116 and contacts the retaining wall 116. The insulating layer 118 may have a patterned shape, for example, an annular structure corresponding to the layout pattern of the retaining wall 116, and together with the retaining wall 116 surround the connecting region 108. . In another embodiment of the present invention, the insulating layer 118 may also be a layered structure covering the non-microelectromechanical region 102 in its entirety. As shown in FIG. 4, it has the same layout pattern as the mask layer 120 and may be patterned in the same manner. The process is etched, so that the insulating layer 118 covers not only the peripheral region 110 but also other regions than the peripheral region 110, but the connection region 108 is exposed.

Referring again to FIGS. 2 and 4, the mask layer 120 has an opening 123 to expose the connection region 108 of the contact pad 104, which is a layered structure covering the non-microelectromechanical region 102, covering the dielectric layer 112. And the insulating layer 118 has a high resisting ability to the etchant 122 to ensure that the surface of the entire non-microelectromechanical region 102 is not eroded by the etchant 122. For example, when the etchant 122 is hydrofluoric acid (HF), the material of the mask layer 120 may include a metal such as aluminum. Since the insulating layer 118 is provided under the mask layer 120, the phenomenon that the mask layer 120 is directly electrically connected to the contact pad 104 to cause a short circuit can be avoided.

Please refer to FIG. 5, which is a schematic view of another preferred embodiment of the contact pad protection structure of the present invention. As shown in FIG. 5, in order to enhance the insulation effect, a bottom layer 124 may be further disposed under the insulating layer 118 at the bottom end of the insulating layer 118 while contacting the dielectric layer 112 and the retaining wall 116, as shown in FIG. 5; Alternatively, the bottom layer 124 is located at the top end of the insulating layer 118 and contacts the mask layer 120. Underlying material 124 comprises silicon nitride (SiN), silicide oxynitride (silicon oxynitride), hafnium silicon oxynitride (HfSiON), zirconium dioxide (ZrO ₂₎ or hafnium oxide (HfO _2), or other high dielectric High-k dielectric material. When the insulating layer 118 is amorphous, a reactive gas such as oxygen may be gradually added during formation to form a gradient insulating layer 118, which has a strong anti-etching property at the bottom and a top insulating effect.

Please refer to FIG. 6. FIG. 6 is a schematic view of still another preferred embodiment of the contact pad protection structure of the present invention. As shown in FIG. 6, the contact pad protection structure of the present invention may further include an adhesive layer 126 disposed between the insulating layer 118 and the dielectric layer 112 or disposed between the insulating layer 118 and the mask layer 120. Between, or between the insulating layer 118, the dielectric layer 112 and the mask layer 120. The material of the adhesive layer 126 may include titanium metal or titanium nitride (Ti/TiN). It is to be noted that, since the material of the adhesive layer 126 is electrically conductive, if it is disposed between the insulating layer 118 and the retaining wall 116, it is necessary to prevent the adhesive layer 126 from simultaneously contacting the mask layer 120 and the retaining wall 116 to cause a short circuit. .

As described above, the present invention can form a protective structure between the microelectromechanical region and the non-microelectromechanical region in addition to the protective structure formed on each of the contact pads. Please refer to Fig. 7. Fig. 7 is a schematic cross-sectional view showing the protective structure between the microelectromechanical region and the non-microelectromechanical region of the present invention, which is drawn along the tangent line BB' of Fig. 1. As shown in FIG. 7, the semiconductor substrate 106 has a microelectromechanical region 100 and a non-microelectromechanical region 102 disposed between the microelectromechanical region 100 and the non-microelectromechanical region 102. The dielectric layer 112 is disposed on the semiconductor substrate 106. In particular, the dielectric layer 112 is disposed in the protective structure region 101 and the non-microelectromechanical region 102, and the dielectric layer 112 in the microelectromechanical region 100 is exposed to the etchant 122. It is removed to form various mechanical elements (not shown) that are movable or have a spatial microstructure.

In order to prevent the etchant 122 from penetrating into the non-microelectromechanical region 102, the present invention provides a protective structure in the protective structure region 101. The protective structure includes an insulating layer 118, at least one first retaining wall 134, a top metal layer 130, a plurality of metal layers 128, and a plurality of second retaining walls 132. The plurality of metal layers 128 and the plurality of second retaining walls 132 are disposed in the dielectric layer 112. The metal layers 128 are connected to the second retaining walls 132, and the top end contacts the top metal layer 130, and the bottom end contacts the semiconductor. Substrate 106. A top metal layer 130 is disposed opposite the plurality of metal layers 128 and the plurality of second barrier walls 132. The material of the plurality of metal layers 130, the plurality of second retaining walls 132 and the top metal layer 130 comprises metal aluminum, metal tungsten, metallic copper or various metals resistant to hydrofluoric acid etching, and is formed by the metal interconnect process. In the structure area 101. A first retaining wall 134 and an insulating layer 118 are disposed above the top metal layer 130. The material of the first retaining wall 134 comprises metal tungsten, metal aluminum, amorphous germanium or tantalum nitride or other material etchable by the etch resist 122. The protective structure of the present invention may have a single layer of first retaining wall 134 or, as the case may be, a plurality of first retaining walls 134 disposed in parallel with each other. The material of the insulating layer 118 comprises amorphous germanium or tantalum nitride. The material of the insulating layer 118 and the first retaining wall 134 may be amorphous as well, but may also be different, for example, the insulating layer 118, depending on various processes or products. It is amorphous, and the first retaining wall 134 is metallic tungsten. In addition, the mask layer 120 is a layered structure covering the non-microelectromechanical region 102 and the protective structure region 101, covering the dielectric layer 112 and the insulating layer 118 to ensure the surface of the entire non-microelectromechanical region 102. It is not etched by the etchant 122.

Similarly, the protective structure of the present invention may further comprise an adhesive layer 126; or, may also comprise a bottom layer 124, the implementation of which is as described above, and will not be repeatedly described herein.

As shown in FIG. 7, the protection structure of the present invention is located between the microelectromechanical region 100 and the non-microelectromechanical region 102, and has a plurality of metal layers 128, a plurality of second retaining walls 132, a top metal layer 130, and a first retaining wall. The insulating layer 118 and the insulating layer 118 form a complete anti-etching structure from above, thereby effectively preventing the etching gas 122 from penetrating into the non-microelectromechanical region 102 from the microelectromechanical region 100. In addition, the protection structure of the present invention is located between the microelectromechanical region 100 and the non-microelectromechanical region 102, and the implementation manner thereof may be a linear structure as the protection structure region 101 of FIG. 1 spanning the microelectromechanical region 100 and non-micro Between the electromechanical regions 102. Alternatively, as shown in Fig. 8, a closed protective structure is formed around the entire microelectromechanical region 100, or conversely, around the entire non-microelectromechanical region 102. In this embodiment, the first retaining wall 134 may be formed to form a closed polygon. Preferably, the polygon has an internal angle α of about 130 degrees, as shown in FIG.

In summary, the present invention provides a protective structure suitable for use in a general semiconductor contact pad or microelectromechanical system, and the enclosed protective structure can effectively avoid the erosion of an etchant such as hydrofluoric acid, and can protect the non-micro-electromechanical region. Components are not destroyed, improving product yield and reliability.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

50. . . Grain

100. . . Microelectromechanical region

101. . . Protective structure area

102. . . Non-microelectromechanical region

104. . . Contact pad

106. . . Semiconductor substrate

108. . . Connection area

110. . . Surrounding area

112. . . Dielectric layer

116. . . Retaining wall

118. . . Insulation

120. . . Mask layer

122. . . Etchant

123. . . Opening

124. . . Bottom layer

126. . . Adhesive layer

128. . . Metal layer

130. . . Top metal layer

132. . . Second retaining wall

134. . . First retaining wall

Figure 1 is a schematic plan view of a microelectromechanical region and a non-microelectromechanical region in the present invention.

Figure 2 is a schematic cross-sectional view showing the contact pad protection structure of the present invention.

Figure 3 is a schematic plan view of the layout of the retaining wall of the present invention.

4 to 6 are schematic views showing an embodiment of a contact pad protection structure in the present invention.

Figure 7 is a schematic cross-sectional view showing a protective structure between a microelectromechanical region and a non-microelectromechanical region in the present invention.

Figure 8 is a schematic view of another embodiment of the protective structure of the present invention.

104. . . Contact pad

106. . . Semiconductor substrate

108. . . Connection area

110. . . Surrounding area

112. . . Dielectric layer

116. . . Retaining wall

118. . . Insulation

120. . . Mask layer

122. . . Etchant

123. . . Opening

Claims (20)

A protective structure of a contact pad, the contact pad is disposed in a dielectric layer on a semiconductor substrate, and the contact pad comprises a connection region and a peripheral region surrounding the connection region, the protection structure comprises: at least one retaining wall, The dielectric layer is disposed on the peripheral region, wherein the retaining wall surrounds the connecting region; an insulating layer is disposed on the dielectric layer, and the barrier wall contacts the insulating layer and the contact pad; and A mask layer is disposed on the dielectric layer and covers the insulating layer, and the mask layer has an opening to expose the connection region of the contact pad. The protective structure of the contact pad of claim 1, wherein the retaining wall comprises tungsten, aluminum, amorphous germanium or tantalum nitride. The protective structure of the contact pad of claim 1, wherein the insulating layer comprises amorphous germanium or tantalum nitride. The protective structure of the contact pad of claim 1 is further provided with a bottom layer disposed at the bottom of the insulating layer. The protective structure of the contact pad of claim 4, wherein the underlayer comprises tantalum nitride, tantalum carbide, tetraethoxysilane, non-doped germanium glass, phosphor haze glass or borophosphon glass. The protective structure of the contact pad of claim 1, wherein the mask layer comprises a metal. The protective structure of the contact pad of claim 1, further comprising an adhesive layer disposed between the insulating layer and the mask layer. The protective structure of the contact pad of claim 7, wherein the adhesive layer comprises titanium metal or titanium nitride. The protective structure of the contact pad of claim 1, further comprising an adhesive layer disposed between the insulating layer and the dielectric layer. The protective structure of the contact pad of claim 9, wherein the adhesive layer comprises titanium metal or titanium nitride. A semiconductor structure comprising: a semiconductor substrate comprising a microelectromechanical region and a non-microelectromechanical region; a dielectric layer disposed on the semiconductor substrate; a protective structure disposed between the MEMS region and the non-microelectromechanical region And the protective structure comprises: a top metal layer disposed in the dielectric layer; at least one first retaining wall disposed in the dielectric layer on the top metal layer; and an insulating layer disposed on the dielectric layer On the electrical layer, the first barrier wall contacts the insulating layer and the top metal layer; and a mask layer is disposed on the dielectric layer and covers the insulating layer. The semiconductor structure of claim 11, wherein the protective structure further comprises a plurality of metal layers and a plurality of second retaining walls connected to each other and disposed between the top metal layer and the semiconductor substrate. The semiconductor structure of claim 11, wherein the first retaining wall comprises tungsten, aluminum, amorphous germanium or tantalum nitride. The semiconductor structure of claim 11, wherein the insulating layer comprises amorphous germanium or tantalum nitride. The semiconductor structure of claim 11 further comprises a bottom layer disposed at the bottom of the insulating layer. The semiconductor structure of claim 11, wherein the mask layer comprises a metal. The semiconductor structure of claim 11, further comprising an adhesive layer disposed between the insulating layer and the mask layer. The semiconductor structure of claim 17, wherein the adhesive layer comprises titanium metal or titanium nitride. The semiconductor structure of claim 11, further comprising an adhesive layer disposed between the insulating layer and the dielectric layer. The semiconductor structure of claim 19, wherein the adhesive layer comprises titanium metal or titanium nitride.