TWI448793B - Display panel - Google Patents

Description

Display panel

The present invention relates to a display panel, and more particularly to a display panel having a partition wall structure.

Today's social multimedia technology is quite developed, and most of them benefit from the advancement of semiconductor components or display devices. As far as the display is concerned, a liquid crystal display having superior characteristics such as high image quality, good space utilization efficiency, low power consumption, and no radiation has gradually become the mainstream of the market.

Generally, the liquid crystal display panel is composed of two substrates and a liquid crystal layer sandwiched between the two substrates, and the liquid crystal is injected into the two substrates through a vacuum liquid crystal injection method or a liquid crystal dropping type injection method. In the above vacuum liquid crystal injection method, a sealant is formed between two substrates, and after the two substrates are assembled, the liquid crystal material is injected between the two substrates by vacuum injection through an injection port reserved for the sealant. In addition, the liquid crystal dropping type injection method is to first form a sealant on one of the substrates and inject a liquid crystal material on the substrate, and then bond the two substrates to seal the liquid crystal material between the two substrates.

Regardless of the above method, if the sealing quality of the sealant is insufficient, the liquid crystal material may flow outside the sealant, resulting in a decrease in the manufacturing yield of the display panel. Therefore, how to avoid the liquid crystal material of the liquid crystal display panel from overflowing the sealant to improve the production yield of the display panel is also one of the positive developments.

The present invention provides a display panel that can prevent a display medium (eg, liquid crystal material) of a display panel from flowing out of the display panel.

The present invention provides a display panel having a display area, a peripheral area, and a sealant area between the display area and the peripheral area. The display panel includes a first substrate, a pixel array layer, at least one pad electrode, and a second substrate. , a sealant, at least one partition wall structure, and a display medium. The pixel array layer is located in the display area of the first substrate. The pad electrode is located in the sealant region of the first substrate. The second substrate is located opposite to the first substrate. The sealant is located in the sealant region between the first substrate and the second substrate and at least partially covers the pad electrode. The partition wall structure is disposed on at least one of the first substrate and the second substrate and is corresponding to the pad electrode, wherein the partition wall structure has a blocking portion and an extending portion, and the blocking portion is located between the pad electrode and the pixel array layer, And the extension extends from the display area to the sealant area. The display medium is located between the first substrate, the second substrate, and the sealant.

The present invention provides a display panel having a display area, a peripheral area, and a sealant area between the display area and the peripheral area. The display panel includes a first substrate, a pixel array layer, at least one pad electrode, and a second substrate. , a sealant, at least one partition wall structure, and a display medium. The pixel array layer is located in the display area of the first substrate. The pad electrode is located in the sealant region of the first substrate. The second substrate is located opposite to the first substrate. The sealant is located in the sealant region between the first substrate and the second substrate and at least partially covers the pad electrode, wherein at least one channel is formed between the pad electrode and the sealant. The partition wall structure is located on at least one of the first substrate and the second substrate, and corresponds to a channel between the pad electrode and the pixel array layer. The display medium is located between the first substrate, the second substrate, and the sealant.

The present invention provides a display panel having a display area, a peripheral area, and a sealant area between the display area and the peripheral area. The display panel includes a first substrate, a pixel array layer, at least one pad electrode, and a second substrate. , a sealant, at least one partition wall structure, and a display medium. The pixel array layer is located in the display area of the first substrate. The pad electrode is located in the sealant region of the first substrate, and the pad electrode includes an electrode layer, a cover layer and a contact electrode layer. The cover layer covers the electrode layer, wherein the cover layer has a first groove pattern to expose the electrode layer. The contact electrode layer is coated on the cover layer, and the contact electrode layer is electrically connected to the electrode layer through the first trench pattern, wherein the contact electrode layer has a second trench pattern at the corresponding first trench pattern. The second substrate is located opposite to the first substrate. The sealant is located in the sealant region between the first substrate and the second substrate and at least partially covers the pad electrode. The partition wall structure is disposed within the second groove pattern. The display medium is located between the first substrate, the second substrate, and the sealant.

Based on the above, the present invention is provided with a partition wall structure at the corresponding pad electrode, which can prevent the display medium in the display panel from flowing from the display area to the sealant area through the groove or channel located at the electrode of the pad. The surrounding area. Since the arrangement of the partition wall structure can effectively prevent the display medium from flowing into the peripheral area, the present invention can improve the process yield of the display panel.

The above described features and advantages of the present invention will be more apparent from the following description.

1 is a top plan view of a display panel in accordance with an embodiment of the present invention. Fig. 2 is a schematic cross-sectional view taken along line I-I' of Fig. 1. Referring to FIG. 1 and FIG. 2, the display panel of this embodiment has a display area A, a peripheral area B, and a sealant area C between the display area A and the peripheral area B. Here, the peripheral area B is surrounded by the display area A, and the sealant area C is located between the display area A and the peripheral area B.

In addition, the display panel includes a first substrate 100, a pixel array layer 102, at least one pad electrode BP, a second substrate 200, a sealant 400, at least one partition wall structure W, and a display medium 300.

The first substrate 100 and the second substrate 200 are disposed opposite to each other. The materials of the first substrate 100 and the second substrate 200 may each be glass, quartz, organic polymer, or opaque/reflective materials (eg, conductive materials, metals, wafers, ceramics, or other applicable materials). Or other applicable materials. According to an embodiment, the first substrate 100 and the second substrate 200 are all transparent substrates. According to another embodiment, one of the first substrate 100 and the second substrate 200 is a transparent substrate and the other is an opaque substrate.

The pixel array layer 102 is located in the display area A of the first substrate 100. According to the present embodiment, the pixel array layer 102 is composed of a plurality of pixel structures P arranged in an array. Each of the pixel structures includes a scan line, a data line, an active element electrically connected to the scan line and the data line, and a pixel electrode electrically connected to the active element.

In addition, an electrode film 202 may be further disposed on the second substrate 200. The electric field generated between the electrode film 202 and the pixel array layer 102 can control the display medium 300 to cause the display panel to display a particular image. The electrode film 202 described above includes a transparent conductive material such as indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium antimony zinc oxide, or other suitable oxide, or at least The stack of the two. In addition, the second substrate 200 may additionally be provided with a color filter array (not shown) or other components and a film layer.

The sealant 400 is located in the sealant region C between the first substrate 100 and the second substrate 200 such that the first substrate 100 and the second substrate 200 are assembled/attached together, and the sealant 400 is on the first substrate 100 and the first A receiving space is defined between the two substrates 200. The sealant 400 can be a thermosetting adhesive, a light curing adhesive, or other suitable material.

The display medium 300 is located between the first substrate 100, the second substrate 200, and the sealant 400. In other words, the display medium 300 is disposed in the accommodation space between the first substrate 100, the second substrate 200, and the sealant 400. The display medium 300 described above may be a liquid crystal display medium, an electrophoretic display medium, or other display medium.

In addition, a pad electrode BP is provided on the first substrate 100 as shown in FIG. Since the pad electrode BP is at least partially disposed in the sealant region C, the pad electrode BP is at least partially covered by the sealant 400. It is worth mentioning that although the present embodiment is illustrated by taking two pad electrodes BP as an example, the present invention does not limit the number of pad electrodes BP. In addition, this embodiment does not limit the position of the pad electrode BP as long as it is at least partially located in any position in the sealant region C.

Fig. 3 is an enlarged schematic view of a region R of Fig. 1, and Fig. 4 is a schematic cross-sectional view taken along line II-II' of Fig. 3. Referring to FIG. 1 , FIG. 3 and FIG. 4 simultaneously, the pad electrode BP of the embodiment includes an electrode layer 110 , a cover layer 112 , and a contact electrode layer 114 . The electrode layer 110 is located on the first substrate 100 and is electrically connected to the pixel array layer 102 in the display area A. For example, the electrode layer 110 of the pad electrode BP is electrically connected to a common electrode line (not shown) in the pixel array layer 102. The electrode layer 110 is made of a metal material based on conductivity and process convenience, but the present invention is not limited thereto. Other electrically conductive materials may also be used for electrode layer 110, in accordance with other embodiments. For example: alloys, nitrides of metallic materials, oxides of metallic materials, oxynitrides of metallic materials, or other suitable materials, or stacked layers of various suitable materials.

The cover layer 112 covers the electrode layer 110, and the cover layer 112 has a first trench pattern 112a to expose the electrode layer 110. The cover layer 112 comprises an inorganic material (for example: yttria, tantalum nitride, yttrium oxynitride, other suitable materials, or a stacked layer of at least two of the above materials), an organic material (for example, polyester (PET), polyolefin) Classes, polypropylenes, polycarbonates, polyalkylene oxides, polyphenylenes, polyethers, polyketones, polyalcohols, polyaldehydes, or other suitable materials, or combinations thereof, Or other suitable materials, or a combination of the above.

The contact electrode layer 114 is coated on the cover layer 112, and the contact electrode layer 114 is electrically connected to the electrode layer 110 through the first trench pattern 112a. In other words, since the first trench pattern 112a of the cap layer 112 exposes the electrode layer 110, the contact electrode layer 114 coated on the cap layer 112 can be electrically connected to the exposed electrode layer 110 through the first trench pattern 112a. connection. The contact electrode layer 114 may be a transparent conductive material (for example, indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium antimony zinc oxide, or other suitable oxide, or at least two of the above) Stacked layers) or metal materials. In addition, since the contact electrode layer 114 is conformally coated on the cover layer 112, the contact electrode layer 114 has the second trench pattern 114a at the first trench pattern 112a of the corresponding cover layer 112. In the embodiment, the first trench pattern 112a and the second trench pattern 114a are a mesh pattern or a strip pattern, but the invention is not limited thereto.

It is worth mentioning that, since the contact electrode layer 114 of the pad electrode BP has the second groove pattern 114a, when the sealant 400 is applied to the sealant region C, the sealant 400 may not completely fill the pad. The second trench pattern 114a of the electrode BP has at least one channel T between the sealant 400 and the pad electrode BP. Here, since the first trench pattern 112a and the second trench pattern 114a are a mesh pattern or a strip pattern, the channel T between the sealant 400 and the pad electrode BP is a mesh channel (see FIG. 3). Shown) or a strip channel (not shown), but the invention is not limited thereto.

According to an embodiment, a conductive ball 500 may be further disposed above the pad electrode BP to pass through the conductive ball 500 to electrically connect the pad electrode BP and the electrode film 202 on the second substrate 200. In other words, through the arrangement of the conductive balls 500, the pad electrode BP and the electrode film 202 can be electrically connected to the common voltage at the same time. Since the pad electrode BP is located in the sealant region C, the conductive ball 500 on the pad electrode BP is covered or covered by the sealant 400.

As described above, since the contact electrode layer 114 of the pad electrode BP has the second trench pattern 114a, a channel T may be left between the sealant 400 and the pad electrode BP. In order to prevent the display medium 300 in the display area A from flowing out through the above-mentioned channel T, because when the edge of the pad electrode BP is close to the edge of the sealant 400, even if the edge of the pad electrode BP is not covered by the sealant 400 In the display area A, in this embodiment, a partition wall structure W is disposed on at least one of the first substrate 100 and the second substrate 200, and the partition wall structure is disposed corresponding to the pad electrode BP.

According to this embodiment, the partition wall structure W has a barrier portion F and an extension portion E, the barrier portion F is located between the pad electrode BP and the pixel array layer 102 (P), and the extension portion E extends from the display region A to the sealant District C. In the present embodiment, the extension E extends from the display area A to the sealant area C and to the peripheral area B. However, the invention is not limited thereto. In other embodiments, the extension E of the partition wall structure W may also extend from the display area A to the sealant area C and no longer into the peripheral area B. Further, the barrier portion F and the extension portion E of the partition wall structure W of the present embodiment are U-shaped, but the present invention is not limited thereto. In other embodiments, the partition wall structure W may be other shapes or structures.

It is worth mentioning that, in the embodiment of FIG. 4, the partition wall structure W is located on the second substrate 200, and the vertical height position H1 of the partition wall structure W is at least lower than the vertical height of the contact electrode layer 114 of the pad electrode BP. Location H2. The above vertical height position H1 refers to a height position from the bottom of the first substrate 100 to the upper surface of the partition wall structure W. The vertical height position H2 refers to a height position from the bottom of the first substrate 100 to the upper surface of the contact electrode layer 114 of the pad electrode BP.

Since the partition wall structure W of the present embodiment substantially surrounds the pad electrode BP, the vertical height position H1 of the partition wall structure W is at least lower than the vertical height position H2 of the contact electrode layer 114 of the pad electrode BP. Therefore, the partition wall structure W can block the display medium in the display area A from flowing out of the display area A via the passage T between the sealant 400 and the pad electrode BP.

5 is a cross-sectional view of a pad electrode of a display panel in accordance with an embodiment of the present invention. The embodiment of FIG. 5 is similar to the embodiment of FIG. 4, and therefore the same elements are denoted by the same reference numerals and the description thereof will not be repeated. In the embodiment of Fig. 5, the partition wall structure W is located on the first substrate 100, and the vertical height position H1' of the partition wall structure W is at least higher than the vertical height position H2' of the passage T. The above vertical height position H1' refers to a height position from the bottom of the first substrate 100 to the upper surface of the partition wall structure W. The vertical height position H2' refers to the height position from the bottom of the first substrate 100 to the surface of the sealant 400 in the passage T.

As described above, since the partition wall structure W of the present embodiment is disposed substantially corresponding to the pad electrode BP, the vertical height position H1' of the partition wall structure W is at least higher than the vertical height position H2' of the channel T. Therefore, the partition wall structure W can block the display medium in the display area A from flowing out of the display area A via the passage T between the sealant 400 and the pad electrode BP.

6A and 6B are schematic cross-sectional views of a pad electrode of a display panel in accordance with an embodiment of the present invention. Referring to FIG. 6A, this embodiment is similar to the embodiment of FIG. 4, and therefore the same components are denoted by the same reference numerals and the description thereof will not be repeated. In the embodiment of FIG. 6A, the partition wall structure W is composed of a partition wall structure W1 located on the first substrate 100 and a partition wall structure W2 located on the second substrate 200. In particular, the vertical height position H1 of the partition wall structure W2 is at least lower than the vertical height position H2 of the contact electrode layer 114 of the pad electrode BP. The vertical height position H1 refers to a height position from the bottom of the first substrate 100 to the upper surface of the partition wall structure W2. The vertical height position H2 refers to a height position from the bottom of the first substrate 100 to the upper surface of the contact electrode layer 114 of the pad electrode BP. In this embodiment, the height position of the partition wall structure W1 is not limited, and the partition wall structure W1 may not contact the partition wall structure W2 or may interfere with each other.

As described above, since the partition wall structure W (partition wall structure W1, W2) is substantially corresponding to the pad electrode BP, and the vertical height position H1 of the partition wall structure W2 is at least lower than the contact electrode of the pad electrode BP. The vertical height position H2 of layer 114. Therefore, the partition wall structure W (partition wall structures W1, W2) can block the display medium in the display area A from flowing out of the display area A via the passage T between the sealant 400 and the pad electrode BP.

In addition, referring to FIG. 6B, this embodiment is similar to the embodiment of FIG. 5, and therefore the same components are denoted by the same reference numerals and the description thereof will not be repeated. In the embodiment of FIG. 6B, the partition wall structure W is composed of a partition wall structure W1 located on the first substrate 100 and a partition wall structure W2 located on the second substrate 200. According to the present embodiment, the vertical height position H1' of the partition wall structure W1 is at least higher than the vertical height position H2' of the passage T. The above vertical height position H1' refers to a height position from the bottom of the first substrate 100 to the upper surface of the partition wall structure W1. The vertical height position H2' refers to the height position from the bottom of the first substrate 100 to the surface of the sealant 400 in the passage T. In this embodiment, the height position of the partition wall structure W2 is not limited, and the partition wall structure W2 may not contact the partition wall structure W1 or may interfere with each other.

Similarly, the above-described partition wall structure W (partition wall structures W1, W2) is disposed substantially corresponding to the pad electrode BP, and the vertical height position H1' of the partition wall structure W1 is at least higher than the vertical height position H2' of the channel T. Therefore, the partition wall structures W1, W2 can block the display medium in the display area A from flowing out of the display area A via the passage T between the sealant 400 and the pad electrode BP.

7 is a top plan view of a pad electrode of a display panel in accordance with an embodiment of the present invention. Referring to FIG. 7, the structure of the present embodiment is similar to that of FIG. 3 described above, and therefore the same components are denoted by the same reference numerals and the description thereof will not be repeated. In the embodiment of Fig. 7, the extension E of the partition wall structure W has a front section E2 and a rear section E1. The front portion E2 is connected to the blocking portion F and the front portion E2 has an elongated structure. The rear portion E1 is adjacent to the front portion E2 and the rear portion E1 has a plurality of dot structures. In the present embodiment, the front portion E2 of the elongated structure extends from the display area A to the sealant area C. The dot structure E1 is located in the sealant region C and may extend to the peripheral region B or not to the peripheral region B.

Figure 8 is a top plan view of the pad electrode of the display panel in accordance with an embodiment of the present invention. Referring to FIG. 8, the structure of the present embodiment is similar to that of the above-described FIG. 3, and therefore the same components are denoted by the same reference numerals and the description thereof will not be repeated. In the embodiment of FIG. 8, the partition wall structure W is correspondingly disposed between the pad electrode BP and the pixel array layer 102 (P). Although the partition wall structure W of the present embodiment does not surround the pad electrode BP, since the partition wall structure W is disposed between the pad electrode BP and the pixel array layer 102 (P), the partition wall structure W can still block the display. The display medium in the area A flows out of the display area A via the passage T between the sealant 400 and the pad electrode BP. Further, the present invention does not limit the length of the partition wall structure W of Fig. 8. In other words, the length of the partition wall structure W of FIG. 8 may be equivalent to the width of the pad electrode BP or larger than the width of the pad electrode BP. The partition wall structure W of Fig. 8 may also be a continuous frame structure, that is, the partition wall structure W is disposed around the entire display area A.

It should be noted that the layout of the partition wall structure W of FIG. 7 and FIG. 8 may be configured as shown in FIG. 4, that is, the partition wall structure W of FIGS. 7 and 8 is disposed on the second substrate 200. Or adopt the structure of FIG. 5, that is, the partition wall structure W of FIG. 7 and FIG. 8 is disposed on the first substrate 100; or the structure of FIG. 6A or FIG. 6B is adopted, that is, FIG. 7 and FIG. 8 The partition wall structure W is disposed on the first substrate 100 and the second substrate 200. When the partition wall structure W of FIG. 7 and FIG. 8 is disposed on the first substrate 100, the second substrate 200, or the first substrate 100 and the second substrate 200, the vertical height of the partition wall structure W is according to FIG. 4 above. This is achieved in the manner described in FIG. 5 or FIG. 6A or FIG. 6B.

9 is a top plan view of a pad electrode of a display panel in accordance with an embodiment of the present invention. Fig. 10 is a schematic cross-sectional view taken along line III-III' of Fig. 9. Referring to FIG. 9 and FIG. 10, this embodiment is similar to the embodiment of FIG. 3 described above, and therefore the same components are denoted by the same reference numerals and the description thereof will not be repeated. In the embodiment of FIGS. 9 and 10, the partition wall structure W is disposed in the second groove pattern 114a of the pad electrode BP. In more detail, the partition wall structure W is disposed in the passage T between the pad electrode BP and the sealant 400. According to the embodiment, the second trench pattern 114a is a mesh pattern or a strip pattern, and thus the channel T is a mesh channel or a strip channel, but the invention is not limited thereto. The partition wall structure W disposed in the passage T is at least one dot structure. In the embodiment of Fig. 9, the dot-like partition wall structure W is array-aligned in the mesh passage T. In the present embodiment, the dot-shaped partition wall structure W is located on the first substrate 100, and the thickness D of the dot-shaped partition wall structure W is at least greater than the depth d of the channel T. The invention does not limit the number and location of the point partition structures.

As described above, since the partition wall structure W of the present embodiment is disposed in the second groove pattern 114a of the pad electrode BP, the thickness D of the dot-shaped partition wall structure W is at least larger than the depth d of the channel T. Therefore, the partition wall structure W can block the display medium 300 in the display area A from flowing into the peripheral area B.

In summary, the present invention is provided with a partition wall structure at the corresponding pad electrode, which can prevent the display medium in the display panel from flowing from the display area to the sealant area through the groove or channel at the pad electrode. And the surrounding area. Since the arrangement of the partition wall structure can effectively prevent the display medium from flowing into the peripheral area, the present invention can improve the process yield of the display panel.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

A. . . Display area

B. . . Surrounding area

C. . . Frame glue zone

W. . . Partition wall structure

F. . . Barrier

E. . . Extension

E1. . . Rear section

E2. . . Front section

BP. . . Pad electrode

T. . . aisle

P. . . Pixel structure

R. . . region

100. . . First substrate

102. . . Pixel array layer

110. . . Electrode layer

112. . . Cover layer

112a. . . First groove pattern

114. . . Contact electrode

114a. . . Second groove pattern

200. . . Second substrate

202. . . Electrode film

300. . . Display medium

400. . . Sealant

500. . . Conductive ball

H1, H1', H2, H2'. . . Vertical height position

D. . . thickness

d. . . depth

1 is a top plan view of a display panel in accordance with an embodiment of the present invention.

Fig. 2 is a schematic cross-sectional view taken along line I-I' of Fig. 1.

Figure 3 is an enlarged schematic view of a region R of Figure 1.

Fig. 4 is a schematic cross-sectional view taken along line II-II' of Fig. 3.

5, 6A, and 6B are schematic cross-sectional views of a pad electrode of a display panel in accordance with several embodiments of the present invention.

7 through 9 are top plan views of the pad electrodes of the display panel in accordance with several embodiments of the present invention.

Fig. 10 is a schematic cross-sectional view taken along line III-III' of Fig. 9.

A. . . Display area

B. . . Surrounding area

C. . . Frame glue zone

W. . . Partition wall structure

F. . . Barrier

E. . . Extension

BP. . . Pad electrode

114a. . . Second groove pattern

T. . . aisle

Claims (17)

A display panel having a display area, a peripheral area, and a sealant area between the display area and the peripheral area, the display panel comprising: a first substrate; a pixel array layer on the first substrate In the display area, at least one pad electrode is located in the sealant region of the first substrate, wherein the pad electrode comprises: an electrode layer; a cover layer covering the electrode layer, wherein the cover layer has a a first trench pattern to expose the electrode layer; and a contact electrode layer overlying the cap layer, the contact electrode layer being electrically connected to the electrode layer through the first trench pattern, wherein the contact The electrode layer has a second groove pattern corresponding to the first groove pattern; a second substrate is located opposite to the first substrate; and a sealant is located between the first substrate and the second substrate And at least partially covering the electrode of the pad; at least one partition wall structure is disposed on at least one of the first substrate and the second substrate and corresponding to the pad electrode, wherein the spacer Wall structure has a barrier And an extension portion between the pad electrode and the pixel array layer, and the extension portion extends from the display area to the sealant region, wherein the partition wall structure is located on the second substrate and the a vertical height position of the partition wall structure is at least lower than a vertical height position of the contact electrode layer, or the partition wall structure is located on the first substrate and a vertical of the partition wall structure a height position at least higher than a vertical height of one of the contact electrode layers; and a display medium between the first substrate, the second substrate, and the sealant. The display panel of claim 1, wherein the second groove pattern is a mesh pattern. The display panel of claim 1, wherein the sealant does not fill the second trench pattern of the contact electrode layer, and thus the sealant and the pad electrode have at least one channel therebetween. The display panel of claim 1, wherein the extension extends from the display area to the sealant area and extends to the peripheral area. The display panel of claim 1, wherein the extension extends from the display area to the sealant area, and the extension does not extend to the peripheral area. The display panel of claim 1, wherein the barrier portion of the partition structure and the extension portion form a U shape. The display panel of claim 1, wherein the extension of the partition structure has a front section and a rear section, the front section being connected to the barrier and having an elongated structure, the rear section being in close proximity The front section has a plurality of dot structures. The display panel of claim 1, further comprising: an electrode film on the second substrate; and at least one conductive ball on the electrode of the pad to make the pad of the first substrate The electrode is electrically connected to the electrode film of the second substrate. A display panel having a display area, a peripheral area, and a sealant area between the display area and the peripheral area, the display panel comprising: a first substrate; a pixel array layer on the first substrate In the display area, at least one pad electrode is located in the sealant region of the first substrate; a second substrate is located opposite to the first substrate; a sealant is located on the first substrate and the first substrate And at least partially covering the pad electrode between the two substrates, wherein at least one channel is formed between the pad electrode and the sealant; at least one partition wall structure is located on the first substrate and the first And at least one of the two substrates, and corresponding to the channel of the pad electrode and the pixel array layer, wherein the partition structure is located on the first substrate and a vertical height position of the partition structure a position at least higher than a vertical height of the channel, or the partition structure is located on the second substrate and a vertical height position of the partition structure is at least lower than a vertical height position of the contact electrode layer; and a display Medium, bit The first substrate, the second between the substrate and the sealant. The display panel of claim 9, wherein the pad electrode comprises: an electrode layer; a cover layer covering the electrode layer, wherein the cover layer has a first groove pattern to expose the electrode Layer; a contact electrode layer is electrically connected to the electrode layer through the first trench pattern, wherein the contact electrode layer has a first portion corresponding to the first trench pattern a trench pattern in which the sealant does not fill the second trench pattern of the contact electrode layer, such that the sealant and the pad electrode have the channel. The display panel of claim 10, wherein the channel is a mesh channel or a strip channel. The display panel of claim 9, wherein the partition structure surrounds the display area. The display panel of claim 9, further comprising: an electrode film on the second substrate; and at least one conductive ball on the electrode of the pad to make the pad of the first substrate The electrode is electrically connected to the electrode film of the second substrate. A display panel having a display area, a peripheral area, and a sealant area between the display area and the peripheral area, the display panel comprising: a first substrate; a pixel array layer on the first substrate In the display area, at least one pad electrode is located in the sealant region of the first substrate, wherein the pad electrode comprises: an electrode layer; a cover layer covering the electrode layer, wherein the cover layer has a a first trench pattern to expose the electrode layer; and a contact electrode layer overlying the cap layer, the contact electrode The layer is electrically connected to the electrode layer through the first trench pattern, wherein the contact electrode layer has a second trench pattern corresponding to the first trench pattern; and a second substrate located on the first substrate a sealant located in the sealant region between the first substrate and the second substrate and at least partially covering the pad electrode; a partition wall structure disposed in the second trench pattern The partition wall structure is located on the first substrate, and the partition wall structure has a thickness at least greater than a depth of the second trench pattern; and a display medium is disposed between the first substrate, the second substrate, and the sealant . The display panel of claim 14, wherein the sealant does not fill the second groove pattern of the contact electrode layer, and thus the sealant and the pad electrode have a passage. The display panel of claim 14, wherein the second groove pattern is a mesh pattern. The display panel of claim 16, wherein the partition wall structure is at least a point structure.