TWI448082B - Pulse generator trigger by event - Google Patents
Pulse generator trigger by event Download PDFInfo
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- TWI448082B TWI448082B TW100117299A TW100117299A TWI448082B TW I448082 B TWI448082 B TW I448082B TW 100117299 A TW100117299 A TW 100117299A TW 100117299 A TW100117299 A TW 100117299A TW I448082 B TWI448082 B TW I448082B
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Description
本發明係在事件觸發型脈波產生機制,所屬技術領域為電子電機,數位訊號處理,與嵌入式系統之應用等相關應用領域上。 The invention relates to an event-triggered pulse wave generation mechanism, and the technical field belongs to the related fields of application of electronic motors, digital signal processing, and applications of embedded systems.
電子裝置系統往往為複數個次系統或電路組成,而每一個次系統或電路,又有各自之時脈,其時脈又是不同步;往往一些儀器系統希望產生單一脈波且其時序與時脈寬度又要與一另時脈系統能同步以作精確調控之事件觸發脈波產生機制,為工業界電路設計者時時刻刻所想的技藝;中華民國發明專利I298976號之單擊發雙極性波形產生裝置及方法之先前技藝中,用一些NAND、D-FF等邏輯元件完成事件觸發脈波產生機制,如圖一所示;上述利用不同種類分離式數位IC元件組合成事件觸發脈波產生機制之邏輯電路設計,其缺點為需用不同種類分離式數位IC元件造成,零件管理麻煩、故障時檢測費時與所佔電路空間佈局增大與複雜;為了解決上述之問題,本發明提出一演算法則於單晶片微處理機產生事件觸發脈波產生機制。 Electronic device systems are often composed of multiple subsystems or circuits, and each subsystem or circuit has its own clock, and its clock is not synchronized; often some instrument systems want to generate a single pulse and its timing is timely. The pulse width must be synchronized with the other clock system to precisely control the event trigger pulse wave generation mechanism, which is the skill of the industrial circuit designer all the time; the Republic of China invention patent I298976 clicks double In the prior art of the polarity waveform generating device and method, the event triggering pulse wave generating mechanism is completed by using logic elements such as NAND and D-FF, as shown in FIG. 1; the above-mentioned different types of discrete digital IC components are combined into an event-triggered pulse wave. The logic circuit design of the generation mechanism has the disadvantages that different types of discrete digital IC components are required, the parts management is troublesome, the time-consuming detection and the occupied circuit space layout are increased and complicated; in order to solve the above problems, the present invention proposes a The algorithm generates an event-triggered pulse generation mechanism on a single-chip microprocessor.
本發明專利提出事件觸發型脈波產生機制,該機制可以整合到現有的微處理控制系統並可簡化電子電路設計與相關電子元件之成本與維護管理成本。 The invention patent proposes an event-triggered pulse wave generation mechanism, which can be integrated into an existing micro-processing control system and can simplify the cost and maintenance management cost of electronic circuit design and related electronic components.
在系統設計中常常會有利用事件觸發的方式而產生單一或多個的脈波訊號,而其所產生的脈波訊號也往往需要跟系統時脈相呼應,如圖二所示;上面波形為原系統的時脈,而當一事件處發,可在下一時脈產生精確的在下一脈波內產生出一個正向或負向的脈波。最常見的就如中華民國發明專利I298976號之單擊發雙極性波形產生裝置及方法中用一些NAND、D-FF等分離式數位邏輯元件完成事件觸發脈波產生機制;另一方式則是利用可程式化的邏輯元件組合NAND、D-FF等分離式數位邏輯元件功能,但其設計成本較高,本發明專利此設計中於單晶片微控制器,實現一演算法直接整合電路,並透過程式設計達事件觸發其功能與效果,可以有效的達到降低成本與維護管理容易的功效。事件觸發的機制常常應用在電子電路各種不同的設計下,此設計也可以有效與廣泛的應用在各種不同的設計與相關領域中;目前已經應用於壓電材料極性消除驅動器。 In the system design, there are often single or multiple pulse signals generated by the event triggering method, and the pulse signals generated by the system often need to respond to the system clock, as shown in Figure 2; The clock of the original system, when an event occurs, can produce a positive or negative pulse in the next pulse in the next clock. The most common one is the click-issue bipolar waveform generating device and method of the Republic of China invention patent I298976. Some NAND, D-FF and other separate digital logic elements are used to complete the event-triggered pulse wave generating mechanism; the other method is to utilize The programmable logic element combines the functions of separate digital logic elements such as NAND and D-FF, but the design cost is high. The present invention is designed in a single-chip microcontroller to realize an algorithm directly integrating the circuit and The program design event triggers its functions and effects, which can effectively achieve the effect of reducing cost and maintaining management. Event-triggered mechanisms are often used in a variety of different designs of electronic circuits. This design can also be effectively and widely used in a variety of different designs and related fields; it has been applied to piezoelectric material polarity cancellation drivers.
請看第四圖,其為事件觸發的機制其最佳實施例之一,此設計應用了其微控制器300裡面外部中斷的特點而架構,在此用到兩個外部中斷,其中一個為輸入原始的CLK訊號源(中斷1端3010),另一個為事件處發源(中斷2端3020),另一個則為脈波輸出3030腳位;中斷1端3010主功能為提供軟體事件觸發輸入用;如用電腦控制的方式命令系統產生脈波訊號,其輸入為原始時脈3040,當電腦端下命令時,微控制器程式執行序則會跳到中斷副程式做執行與偵測原始時脈訊號;中斷2端3020主功能為提供外部硬體的方式做觸發,如有外部的開關按鈕的方式做事件中斷;當外部有事件中斷3050後,一樣將演算執行序跳至中斷副程式做執行;其演算流程圖400如圖五所示,演算法主程式的功能為初始設定與指定插斷輸入與輸出,迴圈等待插斷;當事件插斷發 生時,進入插斷程式;首先檢測系統時脈是否為正上升緣,若否則為繼續抓取時脈正上升緣;一旦抓取時脈上升緣;則計數器加1;此時指定插斷輸出為低電位;此時檢查計數器是否為2;若不等於2則返回到插斷程式之起點,繼續抓取時脈正上升緣與繼續檢驗計數器是否為2;若計數器等於2,則計數器歸零,並指定插斷輸出為高電位;而能完成輸出脈波的寬度等於時脈寬度又能同步系統本身的時脈上升緣,最後返回主程式,等待下一外部插斷事件之發生。圖六為實際測試結果圖,上面波形為原始訊號源500,下方波形為事件觸發產生脈波訊號600,在此也可看出此設計可以符合預期的效果。 Consider the fourth diagram, which is one of the preferred embodiments of the event-triggered mechanism. This design uses the architecture of the external interrupts in the microcontroller 300. Two external interrupts are used, one of which is an input. The original CLK signal source (interrupt 1 end 3010), the other is the event source (interrupt 2 end 3020), the other is the pulse wave output 3030 pin; interrupt 1 end 3010 main function is to provide software event trigger input; If the computer system controls the system to generate the pulse signal, the input is the original clock 3040. When the computer commands, the microcontroller program execution sequence will jump to the interrupt subroutine to execute and detect the original clock signal. Interrupt 2 end 3020 main function to provide external hardware to trigger, if there is an external switch button to do the event interrupt; when there is an external event interrupt 3050, the arithmetic execution sequence jumps to the interrupt subroutine to perform; The calculation flow chart 400 is shown in Figure 5. The function of the main program of the algorithm is the initial setting and the specified interrupt input and output, and the loop is waiting for the interrupt; when the event is interrupted When it is born, enter the interrupt program; firstly, check if the system clock is positive rising edge, if otherwise continue to grab the positive rising edge of the clock; once the clock rising edge is grabbed; the counter is incremented by 1; Is low; at this time, check if the counter is 2; if it is not equal to 2, return to the starting point of the interrupt program, continue to grab the positive rising edge of the clock and continue to check whether the counter is 2; if the counter is equal to 2, the counter is reset to zero And specify the interrupt output as high; and the output pulse width is equal to the clock width and can synchronize the clock rising edge of the system itself, and finally return to the main program, waiting for the next external interrupt event. Figure 6 shows the actual test result. The upper waveform is the original signal source 500, and the lower waveform is the event trigger to generate the pulse signal 600. It can also be seen that the design can meet the expected effect.
20‧‧‧邏輯設計元件 20‧‧‧Logical design components
2010‧‧‧原始輸入脈波 2010‧‧‧Original input pulse
2020‧‧‧事件觸發源 2020‧‧‧ Event trigger source
2030‧‧‧輸出訊號 2030‧‧‧ Output signal
300‧‧‧微控制器 300‧‧‧Microcontroller
3010‧‧‧中斷1端 3010‧‧‧Interrupted 1
3020‧‧‧中斷2端 3020‧‧‧Interrupted 2 end
3030‧‧‧脈波輸出 3030‧‧‧ Pulse output
3040‧‧‧原始時脈 3040‧‧‧ Original clock
3050‧‧‧事件中斷 3050‧‧‧Event disruption
400‧‧‧演算流程圖 400‧‧‧calculation flow chart
500‧‧‧原始訊號源 500‧‧‧ original source
600‧‧‧產生脈波訊號 600‧‧‧ Generate pulse signal
第一圖係先前技術。 The first picture is prior art.
第二圖係可程式化的邏輯元件設計法示意圖。 The second diagram is a schematic diagram of the programmable logic component design method.
第三圖係脈波產生之需求示意圖。 The third picture is a schematic diagram of the demand for pulse wave generation.
第四圖係事件觸發的機制架構圖示意圖。 The fourth picture is a schematic diagram of the mechanism diagram of the event triggering.
第五圖係事件觸發的機制其演算設計流程示意圖。 The fifth picture is a schematic diagram of the calculation process flow of the mechanism triggered by the event.
第六圖係實際測試本發明結果畫面。 The sixth figure is a practical test of the result screen of the present invention.
400‧‧‧演算流程圖 400‧‧‧calculation flow chart
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TWI448082B true TWI448082B (en) | 2014-08-01 |
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Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW418563B (en) * | 1997-07-29 | 2001-01-11 | Nippon Electric Co | Pulse signal generation device for generating and outputting pulse signal without error synchronized with signal of fixed cycle |
US20040158761A1 (en) * | 2002-12-27 | 2004-08-12 | Toshihiko Matsuoka | Clock control circuit apparatus, microcomputer, clock signal oscillation frequency adjusting method, oscillation circuit apparatus, and memory interface circuit apparatus |
TWI225655B (en) * | 2001-01-16 | 2004-12-21 | Samsung Electronics Co Ltd | Synchronous memory devices with synchronized latency control circuits and methods of operating same |
TW200929157A (en) * | 2007-12-21 | 2009-07-01 | Holtek Semiconductor Inc | Signal processing circuit and method |
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- 2011-05-18 TW TW100117299A patent/TWI448082B/en not_active IP Right Cessation
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW418563B (en) * | 1997-07-29 | 2001-01-11 | Nippon Electric Co | Pulse signal generation device for generating and outputting pulse signal without error synchronized with signal of fixed cycle |
TWI225655B (en) * | 2001-01-16 | 2004-12-21 | Samsung Electronics Co Ltd | Synchronous memory devices with synchronized latency control circuits and methods of operating same |
US20040158761A1 (en) * | 2002-12-27 | 2004-08-12 | Toshihiko Matsuoka | Clock control circuit apparatus, microcomputer, clock signal oscillation frequency adjusting method, oscillation circuit apparatus, and memory interface circuit apparatus |
TW200929157A (en) * | 2007-12-21 | 2009-07-01 | Holtek Semiconductor Inc | Signal processing circuit and method |
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