TWI447890B - Chip package structure and fabrication method thereof - Google Patents

Description

Chip package structure and its manufacturing method

The present invention relates to a chip package structure and a method of fabricating the same. In particular, the present invention relates to a high-wafer accumulating chip package structure and a method of fabricating the same.

The integrated circuit is usually packaged into a wafer to provide an electronic product for its function after electrical connection. Since current consumer electronic products, such as mobile communication devices, are getting smaller and smaller, the functions are required to be more and more complex, which must rely on the high-accumulation chip package structure. The largest number of wafers are arranged in smaller and smaller spaces.

The solution currently seen is to increase the electrical and modular performance by stacking the wafers. If you want to increase the number of wafers to meet the changing functions of electronic products, you must stack them in the already stacked wafers. As a result, the number of stacked chips is limited and cannot be continuously expanded. In addition, due to current semiconductor technology, it is possible to produce an integrated circuit with excellent performance. The better the performance, the higher the power consumption, in other words, the stacked wafers will continue to generate a large amount of waste heat to be discharged during operation. Since the wafers are stacked together, there is almost no passage for the large amount of waste heat generated from the integrated circuits, and moreover, stacking is performed in the stacked wafers. This is even worse for the problem of trying to solve the problem that the integrated circuit continuously generates a large amount of waste heat.

Also, the constant generation of a large amount of waste heat from the stacked wafers causes the surrounding temperature to rise. Since the wafer, the encapsulating material and the stacked structure each have a large or small coefficient of thermal expansion. Since the thermal expansion coefficients of the surrounding materials generally do not match each other, the deformation of the wafer, the encapsulating material and the stacked structure may also be mismatched at high temperatures. When the difference in thermal expansion coefficient of adjacent materials is too large, friction and cracks are easily generated, which deteriorates the stability of the stacked structure. Therefore, there is an urgent need for a novel chip package structure to completely solve this problem.

The present invention is to provide a chip package structure and a method of fabricating the same. The chip package structure of the invention can not only provide a high-accumulation wafer stack, but also consider the heat dissipation problem of a large amount of waste heat of the wafer, so that the material can be prevented from deforming, generating friction and causing cracks at high temperatures, thereby destroying the stack structure. The disadvantage of stability.

The present invention therefore provides a chip package structure including a first wafer having a first wafer contact, a second wafer under the first wafer, a second wafer contact, and a left side of the first wafer and the second wafer. a third wafer, a third wafer connector electrically connected to the third wafer, comprising a third wafer connector contact, a fourth wafer located on the right side of the first wafer and the second wafer, and a fourth electrode electrically connected to the fourth wafer a four-wafer connector comprising a fourth wafer connector contact and a buffered insulating thermally conductive material covering the first wafer, the second wafer, the third wafer, the third wafer connector, the fourth wafer and the fourth wafer a connector and selectively exposing the first wafer contact, the second wafer contact, the third wafer connector contact, and the fourth wafer connector contact.

The invention then proposes a chip package structure comprising: a wafer, a wafer connector and a buffer insulating thermally conductive material. The chip connector includes a surface conductor and a surface contact, and the surface contact is electrically connected to the wafer. The buffered insulating thermally conductive material covers the wafer and the wafer connector.

The present invention then proposes a method of forming a wafer package structure. First, a release film is provided. Next, the first wafer, the second wafer, the third wafer, the third wafer connector, the fourth wafer and the fourth wafer connector are respectively disposed on the release film, wherein the third wafer connector is electrically connected to the third wafer And disposed on the left side of the release film, the fourth wafer connector is electrically connected to the fourth wafer and placed on the right side of the release film, and the third wafer connector includes a third wafer connector contact, and the fourth wafer connector includes a The fourth wafer connector contacts, the first wafer and the second wafer are located between the fourth wafer and the third wafer, wherein the first wafer comprises a first wafer contact and the second wafer comprises a second wafer contact. Then, the first wafer, the second wafer, the third wafer, the third wafer connector, the fourth wafer and the fourth wafer connector are coated with a buffered insulating and thermally conductive material, and the first wafer contact and the second wafer are selectively exposed. The wafer contacts, the third wafer connector contacts and the fourth wafer connector contacts form a desired wafer package structure.

The present invention then proposes a method of forming a wafer package structure. The method first provides a wafer followed by a connector substrate comprising an activatable catalyst particle. The catalyst particles are activated to form a surface wire on the surface of the connecting substrate, and a surface contact is formed on the exposed surface wire to form a connecting member, electrically connect the wafer to the surface contact, and finally use a buffer insulation to conduct heat. The material encapsulates the connectors and the wafer to form a wafer package structure.

1 to 7 are schematic views showing a method of forming a wafer package structure of the present invention. Referring to FIG. 1, first, a release film 101 is provided as a basis for forming a chip package structure. The release film 101 may be a polymer such as a polymer material such as polyethylene terephthalate (PET), polymethyl methacrylate (PMMA) or silicone. The release film 101 may also have a slight adhesive force, for example, a tape having a low viscosity for temporarily fixing the components in the chip package structure. Next, referring to Fig. 2, the pre-formed third wafer connector 135 and the fourth wafer connector 145 are placed by the adhesive force of the release film 101 and temporarily fixed to the release film 101. The third wafer connector 135 and the fourth wafer connector 145 are spaced a little apart to form a recess 102. The third wafer connector 135 is used for electrical connection to the third wafer in the future, so that the third wafer connector contact 136 is included (the contact is only shown by two points in the figure, but the third wafer connector 135 may contain A plurality of third wafer connector contacts 136). Similarly, the fourth wafer connector 145 is used for electrical connection with the fourth wafer in the future, so that the fourth wafer connector contact 146 is included (the contact is shown by only two points in the figure, but the fourth wafer connector 145 may include a plurality of fourth wafer connector contacts 146).

The manner in which the third wafer connector 135 and the fourth wafer connector 145 are formed may be as follows. Please refer to FIGS. 3A to 3E, which are schematic diagrams showing the steps of forming the wafer connector of the present invention. Referring first to Figure 3A, first, a connector substrate 190 is provided that includes an activatable catalyst particle. When the catalyst particles are activated, for example, using a laser to activate, a wire is formed. The activatable catalyst particles may be metal complex particles, metal chelate particles, metal oxide particles or metal nitride particles, etc., such as manganese, chromium, palladium, platinum, aluminum, zinc, copper, A complex, chelate, oxide or nitride of silver, gold, nickel, cobalt, ruthenium, osmium, iron, tungsten, vanadium, niobium, indium, titanium, or any combination thereof. Next, referring to FIG. 3B, proceeding, for example, by electroplating, a layer of copper is formed on the catalyst particles activated on the surface of the connector substrate 190, and the surface wires 194 formed on the surface of the connector substrate 190 are bonded to the surface. Point 195. Referring again to FIG. 3C, the insulator substrate 190 is covered with an insulating layer 192 and the surface contacts 195 are selectively exposed. For example, after the insulating layer 192 is used to fully cover the connector substrate 190, the insulating layer 192 is selectively removed according to the wiring requirements, that is, the surface contact 195 may be exposed. Thereafter, referring to FIG. 3D, a desired electrical connection point 193 is formed on the exposed surface contact 195, thereby obtaining a third wafer connection member 135 or a fourth wafer connection member 145, and the electrical connection points 193 are respectively formed. The third wafer connector contact 136 or the fourth wafer connector contact 146 may have different embodiments depending on different electrical connection configurations, such as solder balls, tin plating, silver plating, copper plating, and the like.

Referring to FIG. 3E, an insert portion 196 may also be formed on the connector substrate 190 as needed. For example, after the surface conductors 194 and the surface contacts 195 are formed on the connector substrate 190, the insulating layer 192 is completely covered, and then the surface contacts 195 are exposed to form an insert portion 196. The plug portion 196 is, for example, a recessed or male plug-in portion that can be used for external connection with another electronic device 197, such as a memory card.

Next, referring to FIG. 4A, the first wafer 110, the second wafer 120, the third wafer 130, and the fourth wafer 140 are respectively placed in the recess 102 according to a predetermined circuit layout, and then filled with a buffer insulation. Thermally conductive material 150. The third wafer 130 is electrically connected to the third wafer connector 135. Preferably, the third wafer 130 is electrically connected to the third wafer connector 135 in a vertical manner. Similarly, the fourth wafer 140 is electrically connected to the fourth wafer connector 145. Preferably, the fourth wafer 140 is also electrically connected to the fourth wafer connector 145 in a vertical manner. In addition, the first wafer 110 and the second wafer 120 are respectively disposed between the fourth wafer 140 and the third wafer 130. Preferably, the active surface of the second wafer 120 is disposed on the release film 101 in a horizontal manner, and The first wafer 110 is positioned above the second wafer 120 in a horizontal manner. The connecting member and the circuit layer can be electrically connected by wire bonding or flip chip. Since the single wafer package structure 100 of the present invention can accommodate at least four electronic wafers 110/120/130/140 to achieve a highly integrated wafer stack, this is one of the features of the present invention.

Regarding the assembly sequence of the respective wafers, the present invention proposes several embodiments. In an embodiment of the present invention, the third wafer connector 135 and the fourth wafer connection 145 may be first placed on the release film 101 to form the recess 102, and then the buffered insulating heat conductive material 150 may be bonded. The completed first wafer 110, second wafer 120, third wafer 130, and fourth wafer 140 are simultaneously placed in the recess 102 to form the necessary electrical connections. In another embodiment of the present invention, the third wafer connector 135 and the fourth wafer connector 145 may be first placed on the release film 101 to form the recess 102, and then the third wafer 130 and the third wafer are first The wafer connection member 135 is electrically connected, and after the fourth wafer 140 is electrically connected to the fourth wafer connection member 145, the first wafer 110 and the second wafer 120 which have been bonded using the buffer insulation thermal conductive material 150 are then transferred in the foregoing manner. In the notch 102. In another embodiment, the third wafer connector 135 can be electrically connected to the third wafer 130. After the fourth wafer connector 145 is electrically connected to the fourth wafer 140, the two are respectively disposed in the release mode. On the film 101, the first wafer 110 and the second wafer 120, which have been bonded using the buffer insulating heat conductive material 150, are then introduced into the recess 102 in the foregoing manner. The above embodiments can achieve the structure of the multi-wafer stack of the present invention.

The first wafer 110 may include a first wafer contact 111 as an electrical connection, for example, solder balls 112 may be formed thereon in advance. Similarly, the second wafer 120 may also include a second wafer contact 121 as an electrical connection, and solder balls (not shown) are formed thereon in advance. At least one of the first wafer 110, the second wafer 120, the third wafer 130, and the fourth wafer 140 is an active component, and at most all of the four may be an active component. Suitable active components can be a central processing unit, a communication chip, a wireless signal chip, a memory chip, a south bridge wafer, a north bridge wafer, a graphics chip, and the like. In addition, at least one of the first wafer 110, the second wafer 120, the third wafer 130, and the fourth wafer 140 is a passive component such as a resistor, an inductor, and/or a capacitor.

As desired, as shown in FIG. 4B, a plurality of wires 180 may be used to electrically connect at least one of the first wafer 110 and the third wafer connector 135 and the fourth wafer connector 145 in accordance with a predetermined circuit layout. If the electrical connection is made by wire bonding, a nickel/gold plating layer 113 is formed on the first wafer contact 111. Similarly, the third wafer connector electrical contact 136 electrically connected thereto is also in the form of a nickel/gold plated. Another wire 180 can also be used to electrically connect at least one of the second wafer 120 with the third wafer connector 135 and the fourth wafer connector 145 to form the desired electrical connection.

The first wafer 110, the second wafer 120, the third wafer 130, the third wafer connection 135, the fourth wafer 140, and the fourth wafer connection 145 are covered with a buffer insulating thermally conductive material 150. The buffer insulating thermally conductive material 150 typically covers portions of the first wafer 110, the second wafer 120, the third wafer 130, the third wafer connector 135, the fourth wafer 140, and the fourth wafer connector 145. For example, after the first insulating wafer 150, the second wafer 120, the third wafer 130, the third wafer connecting member 135, the fourth wafer 140, and the fourth wafer connecting member 145 are integrally covered by the buffer insulating heat conductive material 150, A portion of the buffered insulating thermally conductive material 150 is removed using a laser, so that the first wafer contact 111 and the second wafer contact 121 are selectively exposed to form the desired wafer package structure 100.

It should be noted that the insulating layer 192 of the third die attaching member 135 and the fourth die attaching member 145 may be made of the same or different materials as the buffered thermally conductive insulating material 150. When the material of the insulating layer 192 is the same as that of the buffered thermally conductive insulating material 150, the insulating layer 192 of the third wafer connecting member 135 or the fourth wafer connecting member 145 may be formed first, and then wrapped with the same material of the buffer insulating and heat conducting material 150 in the subsequent step. Overwrite. Alternatively, the third wafer connector 135 or the fourth wafer connector 145 is electrically connected to the third wafer 130 or the fourth wafer 140 without forming the insulating layer 192, and then coated with the buffer insulating heat conductive material 150 to form a wafer. Package structure 100.

The buffer insulating thermally conductive material 150 has both electrical insulation and thermal conductivity. On the one hand, the characteristics of electrical insulation can keep the electrical insulation of each wafer from its contacts, and on the other hand, its thermal conductivity can fully eliminate the large amount of waste heat of the wafer. A material having a diamond structure, ceramics (such as boron nitride, aluminum nitride, aluminum oxide, etc.), tantalum rubber, or tantalum rubber has both electrical insulating properties and thermal conductivity, and can also be a voltage switchable dielectric material (voltage Switchable dielectric (VSDM) material, for example, is an insulating material itself, but when it exceeds a certain voltage, it can become a conductor and has a heat-conducting effect. When the static electricity is too large, the current can be led to the grounding wire or the grounding solder ball through the material. Not shown). In addition, the buffer insulating heat conductive material 150 may further have expansion coefficients matched with the first wafer 110, the second wafer 120, the third wafer 130, and the fourth wafer 140. For example, the expansion coefficient of the buffer insulating heat conductive material 150 may be different. The coefficient of expansion between a wafer, a second wafer, a third wafer, and a fourth wafer and a subsequently formed dielectric layer (not shown) of the build-up layer is, for example, between 5 and 45 ppm/° C. 15-30ppm / °C, can avoid the material at high temperatures, deformation, friction and cracks, which in turn destroy the stability of the stack structure. In addition, the buffer insulating heat conductive material 150 may also be a soft, semi-solid gelatinous material.

Thereafter, if necessary, if the buffer insulating heat conductive material 150 is a soft, semi-solid gel-like material, the buffer insulating heat conductive material 150 may also be cured. Or, as shown in Fig. 5, the release film 101 can be removed if necessary, for example, by peeling off the low-viscosity tape.

Thus, a wafer package structure 100 can be obtained by the foregoing method. Referring to FIG. 4A, the chip package structure 100 of the present invention includes a first wafer 110, a second wafer 120, a third wafer 130, a fourth wafer 140, a third wafer connector 135, a fourth wafer connector 145, and a buffer insulation. Thermally conductive material 150. The third wafer 130 is electrically connected 135 to the third wafer connector in a vertical manner, and the fourth wafer 140 is also electrically connected to the fourth wafer connector 145 in a vertical manner. The third wafer connector 135 serves for electrical connection with the third wafer 130 and will therefore include a third wafer connector contact 136. Similarly, the fourth wafer connector 145 serves to electrically connect to the fourth wafer 140, and thus will include a fourth wafer connector contact 146. In addition, the fourth wafer 140 and the third wafer 130 are located to the left or the right of the first wafer 110 and the second wafer 120, respectively. Preferably, the active surface of the second wafer 120 is disposed horizontally between the fourth wafer 140 and the third wafer 130, and the active surface of the first wafer 110 is positioned above the second wafer 120 in a horizontal manner.

The first wafer 110 may include a first wafer contact 111 as an electrical connection, and may be formed thereon with a solder ball 112 (as shown in FIG. 4A) or a nickel/gold layer 113 (such as 4B) or copper. Pillar. The solder balls 112 or copper posts can be used for flip chip electrical connections, while the nickel/gold plating layer 113 can be used for wire bonding electrical connections. Similarly, the second wafer 120 may also include a second wafer contact 121 as an electrical connection, and a solder ball, a nickel/gold plating layer or a copper pillar (not shown) may be formed thereon in advance. At least one of the first wafer 110, the second wafer 120, the third wafer 130, and the fourth wafer 140 is an active component, and at most all of the four may be an active component. Suitable active components can be a central processing unit, a communication chip, a wireless signal chip, a memory chip, a south bridge wafer, a north bridge wafer, a graphics chip, and the like. In addition, at least one of the first wafer 110, the second wafer 120, the third wafer 130, and the fourth wafer 140 is a passive component such as a resistor, an inductor, and/or a capacitor.

Also, the buffer insulation heat transfer 150 covers a portion of the first wafer 110, the second wafer 120, the third wafer 130, the third wafer connection member 135, the fourth wafer 140, and the fourth wafer connection member 145, and is selectively The first wafer contact 111, the second wafer contact 121, the third wafer connector contact 136, and the fourth wafer connector contact 146 are exposed to form the desired wafer package structure 100. The material of the buffer insulating heat conductive material 150 may be the same as or different from the insulating layer 192 of the third wafer connecting member 135 and the fourth wafer connecting member 145. The buffer insulation thermal conductive material 150 has both electrical insulation and thermal conductivity characteristics, and can also be a voltage switchable dielectric (VSDM) material, for example, an insulating material itself, but when it exceeds a certain voltage, it can become The conductor has a heat conducting effect, and when the static electricity is too large, the current can be conducted to the grounding wire or the grounding tin ball (not shown) via the material. On the one hand, the characteristics of electrical insulation can keep the electrical insulation of each wafer from its contacts, and on the other hand, its thermal conductivity can fully eliminate the large amount of waste heat of the wafer. Diamond structure, ceramics (such as boron nitride, aluminum nitride, aluminum oxide, etc.), tantalum rubber, silicone rubber materials have both electrical insulation properties and thermal conductivity. In addition, the buffer insulating heat conductive material 150 may further have expansion coefficients matched with the first wafer 110, the second wafer 120, the third wafer 130, and the fourth wafer 140, for example, the expansion coefficient of the buffer insulating heat conductive material 150 is first. The coefficient of expansion of the inner dielectric layer (not shown) of the wafer, the second wafer, the third wafer, the fourth wafer and the subsequently formed build-up structure is, for example, between 5 and 45 ppm/° C., preferably 15 30ppm / °C, can avoid the material at high temperatures, deformation, friction and cracks, which in turn destroy the stability of the stack structure.

Further, according to the above-described first to fourth embodiments, another embodiment of a package structure in the present invention can be obtained with respect to the method of fabricating the wafer connector. Please refer to FIG. 4A as well. As shown in FIG. 4A, a package structure according to another embodiment of the present invention includes a wafer (such as the third wafer 130 in FIG. 4A) and a wafer connector (such as the third wafer connector 135 in FIG. 4A). And a buffer insulating thermally conductive material 150. The wafer connector 135 is located at the side of the chip package structure 100 compared to the wafer 130. Wafer connector 135 is fabricated through the manner of Figures 3A-3D having surface lead 194 and surface contact 195 as shown in Figure 3D. Connector 135 includes an activatable catalyst particle that can be formed by surface lead 194 and surface contact 195 by, for example, laser and electroplating. The buffer insulating thermally conductive material 150 encapsulates the wafer 130 and the wafer connector 135. In addition, as shown in FIG. 3D, the surface of the wafer connector 130 includes an insulating layer 192 that covers the wafer connector 130 and selectively exposes the surface contacts 195 such that the surface contacts 195 are electrically connected through, for example, solder balls. The point 193 is electrically connected to the wafer 130. Preferably, the active surface of the wafer 130 is electrically connected to the wafer connector 135 in a vertical manner. The material of the buffer insulating material 150 and the insulating layer 192 may be the same or different, preferably having both electrical insulation and thermal conductivity, such as diamond structure, ceramics (such as boron nitride, aluminum nitride, aluminum oxide, etc.). ), ruthenium rubber, silicone rubber, etc., may also be a voltage switchable dielectric material (VSDM) material, for example, itself is an insulating material, but when it exceeds a certain voltage, it can become a conductor, and has a heat conduction effect, in static electricity When it is too large, the current can be led to the ground wire or grounded solder ball (not shown) via this material.

In another embodiment of the present invention, the wafer connector 135 and the wafer 130 may be directly connected by a copper pillar, a tin plating, a silver plating or a metal paste, in addition to being electrically connected through an electrical connection point 193 such as a solder ball. Make an electrical connection. The relative position of the wafer connector 135 to the wafer 130, in addition to the wafer connector 135 being the side of the wafer 130, may also depend on the layout and design of the product, the underside of the wafer 130 or the top surface of the wafer 130.

Through the surface contacts 195, the wafer connector 135 can be conveniently connected to other components. As shown in FIG. 3E, after the surface wires 194 and the surface contacts 195 are formed on the connector substrate 190, the insulating layer 192 is completely covered, and then the surface contacts 195 are exposed to form an interposer portion 196. For example, a recessed or protruding plug-in portion is externally connected to another electronic device 197 (for example, a memory card). Or connected to other expansion input/output components such as USB ports or the like via various electrical connections.

Various embodiments of the chip package structure proposed by the present invention can be electrically connected to other electronic devices. For example, referring to FIG. 6, an embodiment of a wafer package structure of the present invention is electrically coupled to another wafer package structure 200. Alternatively, referring to FIG. 7, after at least one of the upper and lower sides can be made of at least one layer of the layered structure, the connection pads are connected to other package structures 200, for example, electrically connected to a build-up structure 210 to perform complementary functions. It should be noted that, if the coefficient of thermal expansion of the build-up structure is considered, the coefficient of expansion of the buffered and thermally conductive material 150 in the chip package structure may be between the first wafer, the second wafer, the third wafer, the fourth wafer, and the build-up structure. Between the expansion coefficients of the inner dielectric layer.

In summary, according to the method for manufacturing a package structure according to the present invention, since the present invention skillfully utilizes the wafer connectors located on the left and right sides, not only the wafers can be stacked up and down, but also can be extended to the left and right sides. By making full use of all the surfaces of the board, a four-chip package structure as shown in FIG. 4A can be formed, which can greatly increase the stacking ratio, and thus is particularly suitable for the design of the carrier board. In addition, the wafer connectors on the left and right sides of the package structure have surface wires and surface connection points, which can be formed by simple electroplating and laser methods, and can avoid the problems of the externally connected objects in the prior art. Filling holes in holes, holes, etc., adds a lot of manufacturing costs and time. Therefore, by using the pre-formed chip connector, the wafer can be quickly connected to the wafer, and the use of the side space in the package structure is increased, and the wafer can be easily connected to other electronic components through the chip connector, thereby greatly increasing the package. The flexibility of the structure.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

100. . . Chip package structure

101. . . Release film

102. . . Notch

110. . . First wafer

111. . . First wafer contact

112. . . Solder ball

113. . . Nickel/gold plating

120. . . Second chip

121. . . Second wafer contact

130. . . Third chip

135. . . Third chip connector

136. . . Third chip connector contact

140. . . Fourth chip

145. . . Fourth wafer connector

146. . . Fourth wafer connector contact

150. . . Buffered insulation material

180. . . Line

190. . . Connector substrate

191. . . Stereo wire

192. . . Insulation

193. . . Electrical connection point

194. . . Surface wire

195. . . Surface contact

196. . . Plugin department

197. . . Electronic device

200. . . Chip package structure

210. . . Layered structure

1 to 7 are schematic views showing a method of forming a wafer package structure of the present invention.

100. . . Chip package structure

101. . . Release film

110. . . First wafer

111. . . First wafer contact

112. . . Solder ball

120. . . Second chip

121. . . Second wafer contact

130. . . Third chip

135. . . Third chip connector

136. . . Third chip connector contact

140. . . Fourth chip

145. . . Fourth wafer connector

146. . . Fourth wafer connector contact

150. . . Buffered insulation material

Claims (51)

A chip package structure comprising: a first wafer comprising a first wafer contact; a second wafer under the first wafer, comprising a second wafer contact; a third wafer located at the a first wafer and a left side of the second wafer; a third wafer connection member electrically connected to the third wafer, comprising a third wafer connector contact; a fourth wafer located on the first wafer and the a fourth wafer connector electrically connected to the fourth wafer, comprising a fourth wafer connector contact; and a buffer insulating thermally conductive material covering the first wafer, the second a first wafer contact, the second wafer contact, the third wafer connector a contact, a contact with the fourth wafer connector. The chip package structure of claim 1, wherein at least one of the first wafer, the second wafer, the third wafer, and the fourth wafer is an active component. The chip package structure of claim 2, wherein the active component is selected from the group consisting of a central processing unit, a communication chip, a wireless signal chip, a memory chip, a south bridge chip, a north bridge chip, and a graphics chip. The chip package structure of claim 1, wherein at least one of the first wafer, the second wafer, the third wafer, and the fourth wafer is a passive component. The chip package structure of claim 4, wherein the passive component is selected from the group consisting of a resistor, an inductor, and a capacitor. The chip package structure of claim 1 is electrically connected to another chip package structure. According to the chip package structure of claim 1, at least one of the upper and lower sides can be used as a build-up structure. The chip package structure of claim 7, wherein a coefficient of expansion of the buffer insulating thermally conductive material is between the first wafer, the second wafer, the third wafer, the fourth wafer, and a dielectric layer of the buildup structure. Between the coefficients. The wafer package structure of claim 1, wherein the buffered insulating thermally conductive material comprises a voltage switchable dielectric material. The chip package structure of claim 1, wherein at least one of the first wafer and the third wafer connector and the fourth wafer connector are electrically connected via a wire. The chip package structure of claim 1, wherein at least one of the second wafer and the third wafer connector and the fourth wafer connector are electrically connected via a wire. The chip package structure of claim 1, wherein the third wafer connector and the first At least one of the four wafer connectors includes a plug portion. The chip package structure of claim 11, wherein the plug portion is combinable with another electronic device. A chip package structure comprising: a wafer; a wafer connector comprising a surface conductor and a surface contact, wherein the surface contact is electrically connected to the wafer, and the wafer connector is located relative to the wafer a side of the chip package structure; and a buffer insulating thermally conductive material covering the wafer and the wafer connector. The wafer package structure of claim 14, wherein the wafer connector comprises an activatable catalyst particle. The wafer package structure of claim 14, wherein the surface of the wafer connector comprises an insulating layer, wherein the insulating layer selectively exposes the surface contact. The chip package structure of claim 16, wherein the insulating layer is made of the same material as the buffer insulating thermally conductive material. The wafer package structure of claim 14, wherein the wafer connector is located on a side of the wafer package structure as compared to the wafer. The chip package structure of claim 14, further comprising a second wafer electrically connected to the wafer connector via a wire. The wafer package structure of claim 14, wherein the wafer connector comprises an insert portion. The wafer package structure of claim 20, wherein the plug portion is combinable with another electronic device. The chip package structure of claim 14 is electrically connected to another chip package structure. According to the chip package structure of claim 14, at least one of the upper and lower sides can be used as a build-up structure. The wafer package structure of claim 14, wherein the buffered thermally conductive material comprises a voltage switchable dielectric material. A method of forming a chip package structure includes: providing a release film; and a first wafer, a second wafer, a third wafer, a third wafer connection, a fourth wafer, and a fourth wafer connection Separatingly disposed on the release film, wherein the third wafer connector is electrically connected to the third wafer and disposed on the left side of the release film, and the fourth wafer connector is electrically connected to the fourth wafer and placed on the release film On the right side, and the third wafer connector includes a third wafer connector contact, and the fourth wafer connector includes a first a fourth wafer connector contact, the first wafer and the second wafer being located between the third wafer and the fourth wafer, wherein the first wafer comprises a first wafer contact and the second wafer comprises a second a wafer contact; and coating the first wafer, the second wafer, the third wafer, the third wafer connector, the fourth wafer, and the fourth wafer connector with a buffer insulating thermally conductive material, and selectively The first wafer contact, the second wafer contact, the third wafer connector contact, and the fourth wafer connector contact are exposed to form the wafer package structure. The method of claim 25, wherein the third wafer connector and the fourth wafer connector are first disposed on the release film, and the third wafer and the fourth wafer are placed on the release film, The third wafer connector is electrically connected to the third wafer, and the fourth wafer connector is electrically connected to the fourth wafer, and then the first wafer and the second wafer are placed. The method of claim 26, wherein the first wafer and the second wafer are previously coated with the buffered insulating thermally conductive material. The method of claim 25, wherein the third wafer is first electrically connected to the third wafer connector, the fourth wafer is electrically connected to the fourth wafer connector, and the third wafer and the third wafer are respectively respectively The connecting member, and the fourth wafer and the fourth wafer connecting member are disposed on the release film, and then the first wafer and the second wafer are placed. The method of claim 28, wherein the first wafer and the second wafer are previously coated with the buffered insulating thermally conductive material. The method of claim 25, wherein the third wafer connector and the fourth wafer connector are first disposed on the release film, and the first wafer, the second wafer, and the third wafer are respectively A fourth wafer is placed on the release film. The method of claim 30, wherein the first wafer, the second wafer, the third wafer, and the fourth wafer are previously coated with the buffer insulating thermally conductive material. The method of claim 25, further comprising curing the buffered insulating thermally conductive material. The method of claim 25, further comprising removing the release film. The method of claim 25, further comprising electrically connecting the chip package structure to another chip package structure. The method of claim 25, further comprising the upper and lower sides of the chip package structure, at least one side of which is a build-up structure. The method of claim 35, wherein the buffer insulating thermally conductive material has a coefficient of expansion between the expansion coefficients of the first wafer, the second wafer, the third wafer, the fourth wafer, and the build-up dielectric layer . The wafer package structure of claim 25, wherein the buffered insulating thermally conductive material comprises a voltage switchable dielectric material. The method of claim 25, wherein a laser is used to selectively expose the first wafer contact, the second wafer contact, the third wafer connector contact, and the fourth wafer connector contact. The method of claim 25, wherein at least one of the first wafer, the second wafer, the third wafer, and the fourth wafer is an active component. The method of claim 39, wherein the active component is selected from the group consisting of a central processing unit, a communication chip, a wireless signal chip, a memory chip, a south bridge wafer, a north bridge wafer, and a graphics wafer. The method of claim 25, wherein at least one of the first wafer, the second wafer, the third wafer, and the fourth wafer is a passive component. The method of claim 41, wherein the passive component is selected from the group consisting of a resistor, an inductor, and a capacitor. The method of claim 25, further comprising using a plurality of wires to electrically connect at least one of the first wafer and the third wafer connector and the fourth wafer connector. The method of claim 25, further comprising using a plurality of wires to electrically connect at least one of the second wafer and the third wafer connector and the fourth wafer connector. The method of claim 25, wherein at least one of the third wafer connector and the fourth wafer connector comprises an insert portion. A method of forming a wafer package structure, comprising: providing a wafer; providing a connector substrate comprising an activatable catalyst particle; activating the catalyst particle to form a surface wire on a surface of the connector substrate; Forming a surface contact on the exposed surface lead to form a connector; electrically connecting the wafer to the surface contact; and coating the connector and the wafer with a buffer insulating thermally conductive material to form the wafer The package structure, wherein the connector is located on a side of the chip package structure compared to the wafer. The method of claim 46, further comprising coating the connector substrate with an insulating layer and selectively exposing the surface contact. The method of claim 46, wherein a laser is used to activate the catalyst particles. The method of claim 46, wherein an electroplating method is used to form the surface conductor and the surface contact. The method of claim 46, wherein the connector is located on a side of the wafer package structure as compared to the wafer. The method of claim 46, further comprising forming a plug-in portion on the connector.