TWI446335B - Flat panel display and image signal resolution detecting method thereof - Google Patents

Description

Flat panel display and image signal resolution detection method thereof

The invention relates to a flat panel display and an image signal resolution detecting method thereof.

Due to its light weight, low power consumption and easy carrying, flat panel displays have gradually replaced traditional cathode ray tube (CRT) displays, which are widely used in computer systems to display image signals output by computer mainframes. .

Please refer to FIG. 1, which is a schematic diagram of a prior art computer system. The computer system 100 includes a computer host 110 and a flat panel display 120. The flat panel display 120 is connected to the computer host 110 via a data transmission line 130. The data transmission line 130 is configured to transmit an image signal output by the computer host 110 to the flat panel display 120.

The flat panel display 120 includes pixel units of M x N in a matrix, wherein M is the number of pixel units along the horizontal direction, and N is the number of pixel units along the vertical direction. Therefore, the flat panel display 120 can display a screen with a resolution of at most M×N, that is, the inherent resolution of the flat panel display 120 is M×N. Specifically, the flat horizontal resolution (Fixed Horizontal Resolution) and the inherent vertical resolution (Fixed Vertical Resolution) of the flat panel display 120 are M and N, respectively.

The host computer 110 can generally output image signals of different resolutions, for example, the resolution of the image signal can be 800×600, 1024×768 or 1280×1024, and the resolution of the image signal output by the host computer 110 is Can be adjusted by the user. Therefore, the image signal output by the host computer 110 has a variable resolution, that is, it has a variable vertical resolution (Variable Vertical Resolution) and a variable horizontal resolution (Variable Horizontal Resolution).

Assuming that the flat panel display 120 has an inherent resolution of 1024×768, if the flat panel display 120 is directly used to display an image signal output by the computer host 110, the resolution of the image signal at a certain time is 1280×1024 or 800. When x600, it will not be compatible with the inherent resolution of the flat panel display 120. That is to say, at this time, the flat panel display 120 may have problems such as screen display error or picture distortion, and the image signal output by the host computer 110 cannot be normally displayed.

A method for solving the above problem is to adjust the timing of the image signal outputted by the host computer 110, that is, to zoom (Scaling) the image, so that the resolution of the image signal is inherent to the flat panel display 120. The resolution matches. Since the image signal has a variable resolution, the resolution of the current image signal needs to be detected before the image is scaled, and then the zoom control is performed according to the detection result. To this end, the flat panel display 120 is usually provided with a zoom control circuit for performing resolution detection and zoom control on the image signal outputted by the host computer 110 to make the resolution of the image signal and the flat panel display 120 The intrinsic resolution matches.

Please refer to FIG. 2, which is a block diagram of the zoom control circuit of the flat panel display 120 shown in FIG. 1. The zoom control circuit 200 is disclosed in US Pat. No. 6,894,706, which includes a horizontal counter 210, a vertical counter 220, a decoder 230, a bypass controller 240, and a scaling unit 250. The horizontal counter 210 and the vertical counter 220 are used to determine the resolution of the image signal received by the flat panel display 120. The decoder 230 is configured to analyze the inherent resolution of the flat panel display 120. The bypass controller 240 and the scaling unit 250 are configured to perform scaling control on the image signal to match the resolution of the image signal with the inherent resolution of the flat panel display 120.

In the operation of the zoom control circuit 200, the following methods are used for resolution detection and picture zoom control.

First, the horizontal counter 210 receives a pixel clock signal (CLK) and a data enable signal (Data Enable, DE), and counts the pixel clock signal CLK in the start interval of the data enable signal DE (Counting). . The counting result of the horizontal counter 210 represents the horizontal resolution of the image signal. The vertical counter 220 receives a vertical Sync Pulse (Vsync), a horizontal Sync Pulse (Hsync), and the data enable signal DE, and the data is between the two adjacent vertical sync pulses Vsync. Enable the signal DE to count. The counting result of the vertical counter 220 represents the vertical resolution of the image signal. The decoder 230 receives the panel size code from the inside of the flat panel display 120, and parses the panel size coded signal therein to obtain the inherent vertical resolution and the inherent horizontal resolution of the flat panel display 120. .

Then, the bypass controller 240 receives the resolution of the image signal and the inherent resolution of the flat panel display 120, and compares the resolution of the image signal with the inherent resolution of the flat panel display 120, and further The comparison analysis results in a bypass enable signal (Bypass Enable). Specifically, if the resolution of the image signal matches the inherent resolution of the flat panel display 120, the bypass enable signal is an activation signal; otherwise, the bypass enable signal is an invalid signal.

Finally, the scaling unit 250 receives the image signal, the inherent resolution of the flat panel display 120, and the bypass control signal. If the bypass enable signal is an activation signal, the scaling unit 250 directly outputs the image signal to the driving circuit of the flat panel display 120 for processing. If the bypass enable signal is an invalid signal, the scaling unit 250 scales the image signal such that the vertical resolution and the horizontal resolution are respectively different from the inherent vertical resolution and horizontal resolution of the flat panel display 120. Consistent.

The resolution detection method directly counts the timing signals of the pixel clock signal CLK and the data enable signal DE by the scaling control circuit 200, thereby detecting the horizontal resolution and vertical resolution of the image signal. degree. The resolution detection method is simple and convenient. However, since the timing signal such as the pixel clock signal CLK and the data enable signal DE is internally parsed by the image signal, the image signal is transmitted by the computer host 110 to the During the transmission process of the zoom control circuit 200 of the flat panel display 120, it is easily interfered by other signals or interfered by environmental factors, so that the noise is easily attached to the timing signals such as the pixel clock signal CLK and the data enable signal DE. Therefore, the timing signals such as the pixel clock signal CLK and the data enable signal DE are easily mixed with some interference pulses. The above-mentioned resolution detection method directly uses the counters 210 and 220 to count the pixel clock signal CLK and the data enable signal DE, respectively, and the interference pulse may be included in the counting process. Therefore, the accuracy of the horizontal resolution and the vertical resolution of the image signal obtained by the above resolution detection method is low. Moreover, since the zoom control circuit 200 performs zoom control according to the horizontal resolution and the vertical resolution of the image signal, it may cause a malfunction, thereby causing the flat panel display 120 to display the screen normally.

In view of this, it is necessary to provide a flat panel display that highly accurately detects image signal resolution and reduces scaling control malfunction.

At the same time, there is a need for an image signal resolution detection method applied to the flat panel display.

A flat panel display includes a display panel, a data interface, a zoom control circuit, and a pulse generator. The data interface receives an image signal, the image signal includes a vertical sync signal and a horizontal sync signal, the pulse generator provides an external count pulse independent of the image signal, and the zoom control circuit is respectively vertically synchronized The external count pulse is calculated between the pulses and between the two horizontal sync pulses to determine the vertical resolution of the image signal.

A flat panel display includes a display panel, a data interface, a zoom control circuit, and a pulse generator. The data interface receives an image signal, the pulse generator provides an external counting pulse independent of the image signal, and the scaling control circuit determines the vertical resolution of the image signal by calculating the external counting pulse.

An image signal resolution detecting method includes the steps of: receiving an image signal, comprising a vertical sync signal and a horizontal sync signal; providing an external count pulse, which is independent of the pulse signal of the image signal; The external count pulse is calculated between two vertical sync pulses and between two horizontal sync pulses to determine the vertical resolution of the image signal.

An image signal resolution detecting method includes the steps of: receiving an image signal; providing an external counting pulse, which is independent of a pulse signal of the image signal; respectively, in a frame of the image signal and a The external count pulse is calculated in the horizontal line to determine the vertical resolution of the image signal.

An image signal resolution detecting method includes the steps of: receiving an image signal; providing an external counting pulse independent of a pulse signal of the image signal; determining the image signal by calculating the external counting pulse Vertical resolution.

Compared with the prior art, the flat panel display of the present invention has a pulse generator disposed therein to independently provide an external counting pulse, which is not easily interfered by the surrounding environment and other signals. The flat panel display directly uses the calculation of the external counting pulse for vertical resolution detection, thereby effectively preventing the counting pulse from being inaccurate due to the interference pulse generated by the interference. Therefore, the image signal resolution detection performed by the flat panel display of the present invention has high accuracy.

Compared with the prior art, the image signal resolution detection method of the present invention determines the resolution of the image signal by calculating an external counting pulse. Since the external counting pulse is independent of the pulse signal of the image signal, it is not easily affected by the other signals and has an interference pulse inside. Therefore, the resolution of the image signal can be correctly detected by counting the external counting pulse, and the detection result obtained by the image signal resolution detecting method is highly accurate.

Please refer to FIG. 3, which is a circuit block diagram of a preferred embodiment of the flat panel display of the present invention. The flat panel display 300 includes a data interface 310, a zoom control circuit 320, a pulse generator 330, a timing controller 340, a scan driver 350, a data driver 360, and a display panel 370. The data interface 310 is configured to receive an image signal, which is a digital visual interface (DVI). The scaling control circuit 320 is configured to perform resolution detection and scaling control on the image signal. The pulse generator 330 is configured to provide an external pulse (EP) for the scaling control circuit 320 for resolution detection, which includes a crystal oscillator (OSC). The timing controller 340 is configured to control the driving timing of the scan driver 350 and the data driver 360. The scan driver 350 and the data driver 360 are configured to drive the display panel 370 to display a picture represented by the image signal.

Please refer to FIG. 4, which is a block diagram of the zoom control circuit 320 of the flat panel display 300 shown in FIG. The scaling control circuit 320 includes a first counting unit 321, a second counting unit 322, a mathematical operation unit 323, a program operation unit 324, and a scaling unit 325. The first counting unit 321 and the second counting unit 322 are respectively connected to the mathematical operation unit 323. The mathematical operation unit 323, the program operation unit 324, and the scaling unit 325 are sequentially connected.

The first counting unit 321 and the second counting unit 322 can count the pulse signals received by the first counting unit 321 and output the corresponding counting values. The mathematical operation unit 323 is a divider that divides the input signal. The program operation unit 324 internally stores a software program. The software program is based on the Video Electronic Standards Association (VESA) specification.

Table 1 schematically shows the data format specifications of the VESA specification. Specifically, the VESA specification specifies the range of video display resolution. Each data format includes a vertical horizontal line number Vtotal, a vertical resolution Vactive, a horizontal display pixel number Htotal, and a horizontal resolution Hactive. Taking the SXGA format as an example, the resolution is 1280×1024, and its Vtotal and Htotal are 1066 and 1688, respectively.

The algorithm of the software program mainly comprises identifying an input signal, determining a specific numerical range into which the input signal belongs according to the value represented by the input signal, and then determining a data format closest to the numerical range in the VESA specification, and further according to the data format. Output accurate vertical resolution Vactive and horizontal resolution Hactive.

The working principle of the flat panel display 300 is as follows: The flat panel display 300 receives an image signal from an image signal source (not shown) through the data interface 310. The image signal source can be a computer host or other electronic device capable of outputting image signals, such as a hard disk drive. The image signal includes a plurality of pixel data signals (Pixel Data, PD) and a plurality of timing signals. The timing signal includes a pixel clock pulse CLK, a data enable signal DE, a vertical sync pulse signal Vsync, and a horizontal sync pulse signal Hsync. The data interface 310 further outputs the image signal to the scaling control circuit 320. Specifically, the timing signal is output to the first counting unit 321 and the second counting unit 322, and the pixel data signal PD is output to the scaling unit 325.

The scaling control circuit 320 then performs resolution detection and scaling control on the image signal. The scaling control circuit 320 can perform resolution detection of the image signal by using one of the following resolution detection methods.

Please refer to FIG. 5 , which is a flowchart of a first image signal resolution detection method that can be adopted by the scaling control circuit 320 of the present invention. The image signal resolution detecting method includes the following steps: Step S11, providing an external counting pulse EP; Step S12, determining the vertical horizontal line number Vtotal of the image signal by the external counting pulse EP; Step S13 The external counting pulse EP determines the horizontal display pixel number Htotal of the image signal; in step S14, the vertical resolution Vactive and the horizontal resolution Hactive of the image signal are determined by a program operation.

The step S11 is specifically as follows: the pulse generator 330 generates an external counting pulse EP therein, and outputs the external counting pulse EP to the first counting unit 321 and the second counter 322. The external counting pulse EP is generated by piezoelectric resonance of the crystal oscillator inside the pulse generator 330, which is a pulse signal independent of the image signal output by the image signal source. Moreover, the frequency of the external counting pulse EP can be preset to 1 Hertz (Hz).

Referring to FIG. 6, the step S12 includes the following sub-steps: a first sub-step S121, receiving a vertical sync pulse signal Vsync, a horizontal sync pulse signal Hsync, and an external count pulse EP; a second sub-step S122, in the second vertical sync pulse Vsync Calculating the external count pulse EP and obtaining a first count value Value11; the third sub-step S123, calculating the external count pulse EP between the two horizontal sync pulses Hsync, and obtaining a second count value Value12; step S124, The first count value Value11 and the second count value Value12 are mathematically operated.

The first sub-step S121 is specifically as follows: the first counter 321 receives the vertical sync pulse signal Vsync from the data interface 310, and the external counter pulse EP is received by the pulse generator 330. The second counter 322 receives the horizontal sync pulse signal Hsync from the data interface 310, and the external counter pulse EP is also received by the pulse generator 330.

The second sub-step S122 is specifically as follows: the first counter 321 calculates the external counting pulse EP between two adjacent vertical sync pulses Vsync, and obtains a first count value Value11. That is, the first count value Value11 is a result obtained by the first counter 321 counting in a frame frame of the image signal, which represents that the external count pulse EP appears in one frame of the picture. frequency.

The third sub-step S123 is specifically as follows: the second counter 322 calculates the external counting pulse EP between two adjacent horizontal sync pulse signals Vsync, and obtains a second count value Value12. That is, the second count value Value12 is a result obtained by counting the second counter 322 in a horizontal line of the image signal, which represents the number of times the external count pulse EP appears in a horizontal line. .

The fourth sub-step S124 is specifically as follows: First, the mathematical operation unit 323 receives the first count value Value11 from the first counter 321; simultaneously receives the second count value Value12 from the second counter 322, and stores the second Count value Value12. Next, the mathematical operation unit 323 performs a mathematical division operation on the first count value Value11 and the second count value Value12, and the result of the division operation (ie, the first operation result) represents the vertical horizontal line number Vtotal of the image signal. That is, Vtotal=Value11/Value12. After the calculation ends, the mathematical operation unit 323 outputs the first operation result to the program operation unit 324.

Referring to FIG. 7, the step S13 includes the following sub-steps: a first sub-step S131, receiving the pixel clock signal CLK and the external counting pulse EP; and a second sub-step S132, calculating the pixel clock signal between the external counting pulses EP. CLK, and a third count value Value13 is obtained; the third sub-step S133 performs a mathematical operation on the second count value Value12 and the third count value Value13.

The first sub-step S131 is specifically as follows: the first counter 321 receives the pixel clock signal CLK from the data interface 310, and the external counter pulse EP is received by the pulse generator 330.

The second sub-step S132 is specifically as follows: the first counter 321 calculates the pixel clock signal CLK in an external counting pulse EP, and obtains a third count value Value13. That is, the third count value Value13 represents the number of times the pixel clock signal CLK appears in an external count pulse EP.

The third sub-step S133 is specifically as follows: First, the mathematical operation unit 323 receives the third count value Value13 from the first counter 321 while reading the second count value Value12 internally. Next, the mathematical operation unit 323 performs a mathematical division operation on the second count value Value2 and the third count value Value13, and the result of the division operation (ie, the second operation result) represents the number of pixels in the horizontal direction of the image signal. . That is, Htotal=Value12/Value13. After the calculation ends, the mathematical operation unit 323 outputs the second operation result Htotal to the program operation unit 324.

In the step S13, the calculation process of the third count value Value3 can also be implemented by the second counting unit 322. In addition, in the image signal resolution detecting method shown in FIG. 5, the step S13 of determining the number of pixels Htotal in the horizontal direction may also be implemented by the following calculation method: first, between two adjacent vertical sync pulse signals Vsync The pixel clock signal CLK is calculated and a fourth count value Value 14 is obtained. The calculation process can be implemented by one of the first counting unit 321 and the second counting unit 322. Next, the mathematical operation unit 323 performs a mathematical division operation on the fourth count value Value14 and the first operation result Vtotal obtained in the step S12, and the division result represents the number of pixels in the horizontal direction of the image signal. . That is, Htotal=Value14/Vtotal=Value14/(Value11/Value12)=Value14×Value12/Value11.

The step S14 is specifically as follows: First, the program operation unit 324 receives the first operation result and the second operation result, respectively. Next, the program operation unit 324 identifies the first operation result and the second operation result, and determines the values respectively represented by the two. The program operation unit 324 detects the specific numerical range in which the first operation result and the second operation result fall by the program operation, and identifies the data format of the image signal according to the specific value range. Finally, the program operation unit 324 determines the vertical resolution Vactive and the horizontal resolution Hactive of the image signal according to the data format.

The following is an example of the program operation process of the program operation unit 324: assuming that the first count value Value11 is 1079680 in step S12, and the second count value Value12 is 1012, the first operation result obtained in step S12 is 1067; The fourth count value Value14 in 13 is 1799408, and the second operation result obtained in step S13 is 1686. When the program operation unit 324 recognizes that the value of the second operation result is 1686, it detects the range of values falling by the second operation result, specifically, it falls between the range 1660 and 1770, that is, 1660<Htotal< 1700. At this time, the program operation unit 324 concludes that the data format closest to the second operation result in the VESA specification is the SXGA format, and the second operation result is converted into the horizontal display pixel number Htotal corresponding to the SXGA format. That is, the horizontal direction of the image signal shows the number of pixels Htotal=1688. Similarly, the program operation unit 324 can obtain the number of vertical horizontal lines Vtotal=1066 of the image signal. The program operation unit 324 further outputs the vertical resolution Vactive=1024 and the horizontal resolution Hactive=1280 corresponding to the SXGA format, that is, the scaling control circuit 320 detects that the resolution of the image signal is 1280×1024.

So far, the zoom control circuit 320 completes the detection of its image signal resolution. The image signal resolution detecting method calculates the vertical horizontal line number Vtotal and the horizontal direction display pixel number Htotal of the image signal by the external counting pulse EP. Since the external counting pulse EP is generated by the pulse generator 330 by the piezoelectric resonance of the crystal oscillator and directly applied to the scaling control circuit 320 for resolution detection, it is less susceptible to interference from surrounding environment or other signals. Therefore, the image signal resolution detection method directly uses the external counting pulse EP to implement resolution detection, and the detection result has high accuracy.

The image signal resolution detection method performs a program operation by the program operation unit 324 after calculating the vertical horizontal line number Vtotal of the image signal and the horizontal display pixel number Htotal. The program operation is based on the VESA specification, which can detect the number of the vertical horizontal line number Vtotal and the horizontal direction display pixel number Htotal within a range of values close to the actual value of the image signal. The actual value of the vertical resolution of the signal Vactive and the horizontal resolution Hactive. That is to say, the image signal resolution detecting method allows the vertical horizontal line number Vtotal and the horizontal direction display pixel number Htotal to fluctuate within a numerical range by the program operation. Therefore, even if the timing signal inside the image signal is fluctuated by the surrounding environment interference or other signals, the image signal resolution detection method can accurately detect the resolution of the image signal. The accuracy of the signal resolution detection method is higher.

Please refer to FIG. 8 , which is a flowchart of a second image signal resolution detection method that can be used by the scaling control circuit 320 of the present invention. The image signal resolution detection method includes the following steps: Step S21, providing an external counting pulse EP; Step S22, determining the vertical resolution Vactive of the image signal by the external counting pulse EP; Step S23, by using the The external counting pulse EP determines the horizontal resolution Hactive of the image signal; and in step S24, the vertical resolution Vactive and the horizontal resolution Hactive of the image signal are corrected by a program operation.

The step S21 is consistent with the step S11 of the first image signal resolution detecting method, and the external counting pulse EP is also generated by the pulse generator 330.

Referring to FIG. 9, the step S22 includes the following sub-steps: a first sub-step S221, receiving a vertical sync pulse signal Vsync, a horizontal sync pulse signal Hsync, a data enable signal DE, and an external count pulse EP; a second sub-step S222, The data enable signal interval between the two vertical sync pulses Vsync calculates the external count pulse EP, and obtains a first count value Value21; the third sub-step S223, the data enable signal DE start interval between the two horizontal sync pulses Hsync The external count pulse EP is calculated and a second count value Value22 is obtained. In a fourth sub-step S224, the first count value Value21 and the second count value Value22 are mathematically operated.

The counting process of the first count value Value21 and the second count value Value22 may be performed by the first counting unit 321 and the second counting unit 322, respectively, in the second sub-step S222 and the third sub-step S223. achieve. In the fourth sub-step S224, the mathematical operation unit is implemented by dividing the first count value Value21 and the second count value Value22 by the mathematical operation unit 323, that is, Vactive=Value21/Value22. The result of the division operation (ie, the first operation result) is the vertical resolution Vactive of the image signal.

Referring to FIG. 10, the step S23 includes the following sub-steps: a first sub-step S231, receiving the pixel clock signal CLK and the external counting pulse EP; and a second sub-step S232, calculating the pixel clock signal CLK in the external counting pulse EP. And obtaining a third count value Value23; the third sub-step S123, performing mathematical operations on the second count value Value22 and the third count value Value23.

In the second sub-step S232, the counting process of the third counting value Value23 can be implemented by one of the first counting unit 321 and the second counting unit 322. In the third sub-step S233, the second count value Value22 directly reads the second count value Value22 received in the step S22 by the mathematical operation unit 323, and the mathematical operation unit is used by the mathematical operation unit 323 is implemented by dividing the second count value Value2 and the second count value Value23, and the result of the division operation (ie, the second operation result) is the vertical resolution Hactive of the image signal. That is Hactive=Value22/Value23.

The step S24 is consistent with the step S14 of the first image signal resolution detecting method. Specifically, in step S24, the program operation unit 324 detects the specific numerical range in which the first operation result Vactive and the second operation result Hactive fall according to the VESA specification, and identifies the figure according to the specific numerical range. For the data format of the signal, the vertical resolution Vactive and the horizontal resolution Hactive of the image signal are corrected to the values according to the VESA specification and output according to the data format.

So far, the zoom control circuit 320 completes its image signal resolution detection work. The second image signal resolution detection method and the first image signal detection method are both determined by the external counting pulse EP and further by a program operation to determine the vertical resolution Vactive and horizontal resolution of the image signal. Degree Hactive. Since the external counting pulse EP is generated by the pulse generator 330 by the piezoelectric resonance of the crystal oscillator and directly applied to the scaling control circuit 320 for resolution detection, it is less susceptible to interference from surrounding environment or other signals. Therefore, the accuracy of the detection result obtained by the resolution detection by the image signal resolution detection method is also high.

After the scaling control circuit 320 detects the vertical resolution Vactive and the horizontal resolution Hactive of the image signal, the internal scaling unit 325 scales the vertical resolution Vactive and the horizontal resolution Hactive of the image signal to The inherent vertical resolution and horizontal resolution of the flat panel display 300 pre-programmed therein are matched, and the image signal is further output to the timing controller in a differential voltage differential signal (LVDS) format. 340.

The timing controller 340 analyzes the differential low voltage signal and further controls the operation timing of the scan driver 350 and the data driver 360, respectively. The scan driver 350 and the data driver 360 scan and drive the display panel 370 under the control of the timing controller 34 to display a screen.

The flat panel display 300 of the present invention has the pulse generator 330 disposed therein to generate the external counting pulse EP, and the internal scaling control circuit 320 further detects the first or second image signal resolution detection method. The resolution of the received image signal is measured. Specifically, the scaling control circuit 320 detects the resolution of the image signal by the external counting pulse EP. Since the external counting pulse EP is not easily interfered by the surrounding environment and other signals, the flat panel display 300 effectively avoids the problem that the detection result is inaccurate due to the counting pulse being interfered by the interference pulse. Therefore, the image signal resolution detection performed by the flat panel display 300 of the present invention has high accuracy. Moreover, the flat panel display 300 further includes the program operation unit 324 in the zoom control circuit 320, and the program operation unit 324 performs a program operation to correct the detection result, thereby realizing even the detection result and the actual value. There is a certain deviation, and the flat panel display 300 can still accurately obtain the resolution of the image signal. In addition, the flat panel display 300 further performs zoom control according to the resolution of the image signal detected by the flat panel display 300. Since the image signal resolution detection result is accurate, the flat panel display effectively reduces the zoom control performed by the flat panel display to cause a malfunction. possibility.

However, the flat panel display 300 of the present invention is not limited to the above embodiment. For example, the scaling control circuit 320, the timing controller 340, and the pulse generator 330 can also be integrated into a processor; and the image signal resolution detection performed by the scaling control circuit 320 can also be performed. The processor is implemented by a software program, and the algorithm of the software program may correspond to each image signal resolution detection method described in the above embodiments. For another example, the frequency of the external count pulse EP output by the pulse generator 330 may be preset to other values or the like.

Please refer to FIG. 11, which is a block diagram of a modification of the zoom control circuit of the flat panel display 300 of the present invention. The zoom control circuit 420 is similar to the zoom control circuit 320 described above, except that the zoom control circuit 420 uses a look up table (LUT) 424 instead of the program operation unit 324 inside the zoom control circuit 320. The lookup table 424 corrects the resolution detection result. The work of the lookup table 424 is also based on the VESA specification, which internally sets the resolution of the various data formats specified by the VESA specification.

After the input signal is recognized, the lookup table 424 determines the specific numerical range that the digital signal belongs to according to the value represented by the input signal, and then finds the data format closest to the numerical range and outputs the data. The format corresponds to the vertical resolution Vactive and the horizontal resolution Hactive. Therefore, the scaling control circuit 420 can also use the above two image signal resolution detection methods when performing the resolution detection, and only need to change the step of the program operation to the step of performing the lookup table.

In summary, the present invention complies with the requirements of the invention patent and submits a patent application according to law. However, the above description is only a preferred embodiment of the present invention, and the scope of the present invention is not limited to the above-described embodiments, and those skilled in the art will be equivalently modified or changed in accordance with the spirit of the invention. All should be included in the scope of the following patent application.

Flat panel display. . . 300

Display panel. . . 370

Data interface. . . 310

First counting unit. . . 321

Zoom control circuit. . . 320, 420

Second counting unit. . . 322

Pulse generator. . . 330

Mathematical unit. . . 323

Timing controller. . . 340

Program unit. . . 324

Scan drive. . . 350

Zoom unit. . . 325

Data drive. . . 360

Look up the table. . . 424

1 is a schematic diagram of a prior art computer system.

2 is a block diagram of a zoom control circuit of a flat panel display of the computer system shown in FIG. 1.

3 is a circuit block diagram of a preferred embodiment of the flat panel display of the present invention.

4 is a block diagram of a zoom control circuit of the flat panel display shown in FIG.

FIG. 5 is a flowchart of a first image signal resolution detection method according to the present invention.

FIG. 6 is a flow chart showing the steps of determining the number of horizontal lines in the vertical direction of the image signal according to the image signal resolution detecting method shown in FIG. 5.

FIG. 7 is a flow chart showing the steps of determining the number of pixels in the horizontal direction of the image signal according to the image signal resolution detecting method shown in FIG. 5.

FIG. 8 is a flow chart of a second image signal resolution detecting method according to the present invention.

FIG. 9 is a flow chart showing the steps of determining the vertical resolution of the image signal by the image signal image resolution detection method shown in FIG. 8.

FIG. 10 is a flow chart showing the steps of determining the horizontal resolution of the image signal by the resolution detecting method shown in FIG. 8.

Figure 11 is a block diagram showing a modification of the zoom control circuit of the flat panel display of the present invention.

Flat panel display. . . 300

Data interface. . . 310

Zoom control circuit. . . 320

Pulse generator. . . 330

Timing controller. . . 340

Scan drive. . . 350

Data drive. . . 360

Display panel. . . 370

Claims (10)

A flat panel display includes: a display panel; a data interface; a zoom control circuit; and a pulse generator; wherein the data interface receives an image signal, the image signal includes a vertical sync signal and a horizontal sync Signaling, the pulse generator provides an external counting pulse independent of the image signal, and the scaling control circuit calculates the external counting pulse between the two vertical synchronization pulses and the two horizontal synchronization pulses to determine the image signal The vertical resolution, wherein the scaling control circuit comprises a first counting unit, the first counting unit receives the image signal and the external counting pulse, and counts the received signal. The flat panel display of claim 1, wherein the data interface is a digital visual interface. The flat panel display of claim 1, wherein the pulse generator comprises a crystal oscillator. The flat panel display of claim 1, wherein the scaling control circuit comprises a program operation unit, and the program operation unit corrects the detection result of the image signal resolution. The flat panel display of claim 1, wherein the zoom control circuit comprises a lookup table, the lookup table is for the image The detection result of the resolution is corrected. The flat panel display of claim 1, wherein the zoom control circuit further comprises a second counting unit, wherein the second counting unit receives the image signal and the external counting pulse, and performs the received signal count. The flat panel display of claim 6, wherein the scaling control circuit further comprises a mathematical operation unit that performs a mathematical operation on the counting result of the first counting unit and the second counting unit. The flat panel display of claim 7, wherein the mathematical operation unit comprises a divider. An image signal resolution detection method includes the steps of: receiving an image signal, comprising a vertical sync signal and a horizontal sync signal; providing an external count pulse, which is independent of the pulse signal of the image signal; Calculating the external counting pulse between two vertical sync pulses and two horizontal sync pulses to determine a vertical resolution of the image signal, wherein the step of determining the vertical resolution of the image signal comprises: two vertical sync pulses Calculating the external counting pulse to obtain a first counting value; calculating the external counting pulse between the two horizontal synchronization pulses to obtain a second counting value; performing mathematical operations on the first counting value and the second counting value The image signal further includes a pixel clock signal, wherein the image is determined The step of horizontal resolution of the number includes: calculating the pixel clock pulse between two vertical sync pulses to obtain a fifth count value; performing mathematical operations on the first count value, the second count value, and the fifth count value . The image signal resolution detection method of claim 9, wherein the step of determining the vertical resolution of the image signal further comprises: providing a lookup table; determining, by the lookup table, the result according to the mathematical operation result The vertical resolution of the image signal.