TWI446133B - Method and control device for tail current control isolated converter - Google Patents

Description

Method and control device for tail current control isolated converter

The invention relates to converters, and more particularly to switch control of isolated converters.

Isolated converters are widely used in a variety of off-line power supply and high security requirements. Accurate, efficient, low electromagnetic interference (EMI), small size, low cost control strategies and control circuits become a must. And in order to achieve precise adjustment of the energy supplied to the load, feedback control must be employed. For isolated converters, one of the most basic requirements for feedback control is to electrically isolate the primary side from the secondary side.

Optocouplers are often used to achieve electrical isolation. The output voltage information on the secondary side is fed back to the primary side through the optocoupler to precisely control the primary side switch to transmit the optimized energy to the secondary side. One disadvantage of using optocouplers is the increased system cost. In addition, the optocoupler may be damaged at high isolation voltages. For example, in medical device applications, their power supply systems are very demanding in reliability and often need to withstand high voltage spikes.

Another type of feedback isolation uses a dedicated third or auxiliary winding. The output voltage on the secondary side is similar to the voltage on the auxiliary winding, so feedback can be obtained by detecting the voltage on the auxiliary winding. However, this approach has some problems with feedback. First, the output level cannot be accurately reflected, especially during load response. Second, as with optocouplers, this approach adds cost. Therefore, how to achieve accurate voltage feedback control in a simple way becomes a challenge.

In addition to cost and accuracy considerations, high efficiency and low electromagnetic interference (EMI) are also necessary. Among them, one way to reduce the switching loss is to use a soft switching technology, such as Zero Voltage Switching. In the zero voltage switching technique, when the switch is turned on, its drain-source voltage is zero and there is no conduction loss. In addition, a snubber capacitor can be connected in parallel on the power MOSFET, so that the voltage change rate dv/dt will be greatly reduced, thereby not only reducing the turn-off loss, but also significantly reducing electromagnetic interference (EMI). As switching losses are reduced, the converter can operate at higher switching frequencies, reducing the size of the transformer and other passive components.

Quasi-resonant converters are a typical isolated converter that uses soft switching techniques and feedback control. 1 shows a prior art quasi-resonant converter topology in which Lp and Rp are the inductance and resistance values of the primary side winding, Cp is the resonant capacitor, and Ld is the inductance of the auxiliary winding. When the secondary side energy is depleted (i.e., the magnetic flux is reset), the drain of the primary side switch Qp will generate an oscillating voltage. The resonant frequency is determined by Lp and Cp, and the attenuation factor is determined by Rp. The auxiliary winding Ld is used to detect the re-regulation of the magnetic flux, thereby controlling the Qp of the oscillating voltage to be turned on to reduce the switching loss. At the same time, the output voltage information is fed back to the primary side by an optical coupler to adjust the energy transmitted to the secondary side. As mentioned above, the quasi-resonant converter uses both auxiliary windings and optocouplers to implement feedback and soft switching functions. However, such a converter cannot guarantee zero voltage switching, and is large in size and high in cost.

In view of the problems in the prior art, it is an object of the present invention to provide a novel isolated converter for use in a DC-DC converter and an AC-DC converter. The novel isolated converter provided by the present invention does not require an auxiliary isolation device. For example, optocouplers and auxiliary windings provide isolated feedback with precise voltage regulation.

It is still another object of the present invention to provide a control method for implementing the above-described isolated converter and a control circuit thereof.

In order to achieve the above object, the technical solution adopted by the present invention is as follows: an isolated voltage converter comprising: a primary side circuit including a primary side switch and a primary side controller, wherein the primary side controller is used to control the primary side switch Turn-on and turn-off; a secondary side circuit including a secondary side switch and a secondary side controller, wherein the secondary side controller is used to control the conduction and shutdown of the secondary side switch; When reduced to zero, the secondary side controller keeps the secondary side switch conducting to reverse the secondary side current to a negative tail current; when the tail current reaches a tail current peak, the secondary side The controller turns off the secondary side switch; at the same time, the tail current couples a negative primary side coupling current in the primary side circuit, and conducts the primary side switch through the primary side controller.

In the isolated voltage converter of the present invention, the secondary side circuit further includes an output capacitor coupled between the output of the isolated voltage converter and ground.

In the isolated voltage converter of the present invention, the primary side switch is connected in parallel to the first capacitor.

In the isolated voltage converter of the present invention, the secondary side switch is connected in parallel to the second capacitor.

In the isolated voltage converter of the present invention, the primary side controller turns on the primary side switch when the drain voltage of the primary side switch is lower than the primary side reference trigger voltage; the primary side reference trigger voltage is equal to zero or close to zero .

In the isolated voltage converter of the present invention, the primary side controller turns off the primary side switch when the primary side current increases to the primary side current reference peak.

The isolated voltage converter of the present invention, when the secondary side current increases to a preset current value or the source-drain voltage of the secondary side switch is higher than a preset voltage value, The secondary side switch is turned on.

In the isolated voltage converter of the present invention, the secondary side controller increases the peak value of the tail current when the load is emphasized, and reduces the peak value of the tail current when the load is reduced; meanwhile, the primary The side controller detects a peak of the primary side coupling current and changes the primary side current reference peak in the same direction as the primary side coupling current peak.

In the isolated voltage converter of the present invention, the peak value of the tail current changes in the same direction as the peak value of the source voltage of the secondary side switch.

In the isolated voltage converter of the present invention, the primary side controller includes: a primary side reference voltage generator for receiving the primary side coupling current peak value and outputting the same direction change based on the primary side coupling current peak value a primary side reference voltage indicative of a primary side current reference peak; a primary side first comparator having an inverting input coupled to an output of the primary side reference voltage generator, receiving the primary side reference voltage, the non-inverting input thereof Receiving a detection value of the primary side current; a primary side second comparator having an inverting input receiving a drain voltage of the primary side switch, a non-inverting input receiving the primary side reference trigger voltage; and a primary a side RS latch having a reset input coupled to the output of the primary side first comparator, a set input coupled to the output of the primary side second comparator, the output of the primary side switch control signal.

In the isolated voltage converter of the present invention, the primary side controller further includes one or more voltage detecting circuits, a current detecting circuit, a reference voltage generator, and a gate driving circuit.

In the isolated voltage converter of the present invention, the secondary side controller includes: a secondary side reference voltage generator for receiving an output voltage or current and generating a secondary side reference voltage indicative of a peak current peak; a comparator having an inverting input coupled to an output of the secondary side reference voltage generator, receiving the secondary side reference voltage, and a non-inverting input coupled to a negative current indicative of the secondary side circuit a voltage signal of the value; a second comparator of the secondary side, the inverting input end of which is coupled to the secondary side reference trigger voltage, the non-inverting input terminal of which is coupled to the source voltage of the secondary side switch; the secondary side RS latch The reset input end is coupled to the output end of the secondary side first comparator, the set input end is coupled to the output end of the secondary side second comparator, and the gate control of the output secondary side switch signal.

In the isolated voltage converter of the present invention, the secondary side reference voltage generator receives an output current to generate a secondary side reference voltage that varies in the same direction as the output current.

In the isolated voltage converter of the present invention, the secondary side reference voltage generator receives an output voltage to generate a secondary side reference voltage that varies inversely with the output voltage.

In the isolated voltage converter of the present invention, the secondary side controller further includes one or more current detecting circuits, a voltage detecting circuit, a reference voltage generator, and a gate driving circuit.

The isolated voltage converter of the present invention further provides another secondary side controller that turns off the secondary side switch and keeps it off when the output voltage of the isolated converter is higher than a set upper threshold State until the output voltage is below a set lower threshold.

The isolated converter of the present invention, the other secondary side controller keeps the secondary side switch conducting when the secondary side current decreases to zero, so that the secondary side current commutation becomes a negative tail a current; when the tail current reaches a peak value of the tail current, turning off the secondary side switch; meanwhile, the tail current is coupled to a negative primary side coupling current in the primary side circuit, and the primary side is passed through the primary side controller The switch is turned on.

In the isolated converter of the present invention, the other secondary side controller includes: an output voltage detecting circuit for receiving the output voltage to generate a voltage detecting signal proportional to the output voltage; a first comparator, the inverting input receiving the voltage detection signal, the non-inverting input receiving a reference voltage representing the lower threshold; the secondary side second comparator receiving the voltage detection at the non-inverting input a signal having an inverting input receiving a reference voltage indicative of the upper threshold; a secondary side third comparator having a non-inverting input receiving a voltage signal proportional to a negative value of the secondary side current, the inverting input receiving a reference voltage indicative of a peak current peak; a fourth comparator on the secondary side, the non-inverting input receiving the source voltage of the secondary side switch, the inverting input receiving the secondary side reference trigger voltage, and the secondary side first RS lock a reset terminal coupled to the output of the secondary side first comparator, a set input terminal coupled to the output of the secondary side second comparator; a secondary side second RS latch , setting the input coupling Connected to the output end of the secondary side first comparator, the reset input end is coupled to the output end of the secondary side first RS latch; the secondary side third RS latch is set to the input end coupling Connected to the output of the secondary side second RS latch, the re-input input coupled to the output of the fourth RS latch on the secondary side; the secondary RS latch on the secondary side, which sets the input coupling Connected to the output end of the third side comparator of the secondary side, the reset input end is coupled to the output end of the fourth side comparator of the secondary side; the fifth side RS latch of the secondary side is configured to be coupled to the input end An output end of the fourth side comparator of the secondary side, the reset input end of which is coupled to the output end of the secondary side first or the gate; the secondary side first or gate, wherein one input end is coupled to the secondary side first An output of the RS latch, and the other input is coupled to the output of the fourth side RS latch of the secondary side; the secondary side of the second OR gate, wherein one of the inputs is coupled to the secondary side An output of the three RS latch, and the other input coupled to the output of the secondary side fifth RS latch, which outputs a gate control signal of the secondary side switch

The isolated converter of the present invention, the other secondary side controller further includes an NPN transistor, the base of the NPN transistor being coupled to the output of the secondary side first RS latch The emitter is coupled to the ground, and the collector is coupled to the output of the second or second gate of the secondary side.

In the isolated converter of the present invention, the output voltage detecting circuit may be a resistor divider network, and may further include an error amplifier.

A control method for an isolated converter, comprising: when the secondary side current reaches a zero value, continuing to maintain the secondary side switch conducting, so that the secondary side current commutation becomes a negative tail current; and the tail current is reached When the tail current peaks, the secondary side switch is turned off, and a negative primary side coupling current is coupled to the primary side to turn on the primary side switch.

In the isolated converter control method of the present invention, the negative primary side coupling current is discharged through a capacitor connected in parallel with the primary side switch; when the primary side switch's drain voltage is pulled down to zero voltage or close At zero voltage, the primary side switch is turned on.

The isolated converter control method of the present invention turns off the primary side switch when the positive primary side current reaches the primary side current reference peak.

In the isolated converter control method of the present invention, the change in the primary side current reference peak is the same as the peak change in the primary side coupled current.

In the isolated converter control method of the present invention, the peak value of the tail current changes in the same direction as the load change, and at the same time, the peak value of the primary side coupling current is detected, and the peak value of the primary side coupling current is the same as the tail current peak value. Change.

In the isolated converter control method of the present invention, when the output voltage of the converter is higher than a set upper threshold, the secondary side switch is turned off until the output voltage is lower than a set lower threshold.

The isolated converter circuit and the isolated converter control method provided by the invention can realize the isolated feedback control without the use of auxiliary isolation devices, such as the optical coupler and the auxiliary winding, and have accurate voltage adjustment performance and low electromagnetic interference. And the zero voltage switching function is realized in the process of turning on the primary side switch, which reduces the switching loss and improves the conversion efficiency. At the same time, the isolated converter circuit and the isolated converter control method can be implemented at a low level and low complexity at the integrated circuit level.

DETAILED DESCRIPTION OF THE INVENTION Various preferred embodiments of the present invention are described in detail below. While the invention has been described in terms of various preferred embodiments, those skilled in the art are On the contrary, any alternatives, modifications and equivalents are intended to be within the spirit and scope of the invention. The scope of protection of the present invention is defined by the scope of the patent application. For example, in the embodiment illustrated in Figure 5, the circuit employs one type of RS latch, and those skilled in the art will appreciate that other types of RS latches can be used to achieve the same functionality. In addition, in the following detailed description, specific details are set forth in the detailed description of the invention. However, it will be understood by those skilled in the art that the present invention can be implemented even in the absence of many details or combinations of other methods, elements, materials, and the like. In other instances, well-known methods, procedures, components, and circuit structures are not described in detail to avoid unnecessarily obscuring the invention.

The control method, primary side controller and secondary side controller disclosed by the present invention can be applied to any isolated DC-DC converter and isolated AC-DC converter. In the following detailed description, for the sake of brevity, only the flyback DC-DC converter is taken as an example to explain the specific operational principle of the present invention.

2 is a schematic diagram of a flyback voltage DC-DC converter in accordance with one embodiment of the present invention. The converter includes a primary side circuit and a secondary side circuit that are isolated by a transformer T1. Among them, the primary side circuit includes a DC input Vin, a primary winding, a primary side switch Qp, a capacitor C1, and a primary side controller. The switch Qp is periodically turned on or off. The primary side controller directly or indirectly receives the source voltages of the gate voltages Vswp, Qp of the switch Qp and the primary side current Ip, and generates a primary side gate control signal DRVP to control the on and off of the switch Qp. The secondary side circuit includes a secondary winding, a secondary synchronous rectifier Qs, a smoothing capacitor Cout, and a secondary side controller. The synchronous rectifier Qs is used to rectify the signal generated by the secondary winding, and the rectified signal is filtered by the filter capacitor Cout to output a voltage Vout to supply power to the load. The secondary side controller receives the source voltage Vsws of the rectifier Qs, the output voltage Vout, and the secondary side current Is, and generates a secondary side gate control signal DRVS to control the turning on and off of the rectifier Qs.

The secondary side controller keeps the rectifier Qs turned on for a short period of time after the secondary side current Is decreases to zero, and is called a negative tail current after Is is reduced to zero commutating to a negative current, and At the peak current peak, the secondary side controller turns off Qs. Therefore, Qs is controlled by a small negative tail current flowing from the drain of the rectifier Qs to the source. This tail current is coupled to the primary side such that Vswp is discharged through capacitor C1 until it is zero. The primary side controller then turns on the switch Qp using zero voltage switching (ZVS) when it detects that Vswp is zero. The tail current control referred to in the present invention is the above control process.

In one embodiment, the secondary side controller adaptively controls the peak value of the tail current based on the input voltage Vin. Since the peak value of the source voltage Vsws of the rectifier Qs is proportional to the input voltage Vin, this feedforward control is realized by controlling the peak value of the tail current based on the peak value of the Vsws. In another embodiment, the load information is fed back to the primary side via the tail current peak, and the primary side circuit obtains the information by detecting the value coupled to the primary side. Therefore, the secondary side signal is fed back to the primary side without passing through the auxiliary winding or the optical coupler. In addition to the zero voltage switching (ZVS) function, capacitor C1 is also used as a shutdown buffer for switch Qp. Similarly, in one embodiment, for the secondary side circuit, a capacitor C2 can be connected in parallel with the rectifier Qs for use as a shutdown buffer for the rectifier Qs.

In various embodiments of the invention, the switch Qp and the rectifier Qs may be MOSFETs, IGBTs or any other type of switch.

3 shows a timing diagram of an isolated converter employing tail current control, as shown in FIG. 2, in accordance with one embodiment of the present invention. As shown in FIG. 3, timing waveform diagrams of the signals Vswp, Ip, DRVP, Vsws, Is, and DRVS are respectively shown. At time t1, Ip increases to a maximum value Ipmax, and thus DRVP is reset to a low level to turn off Qp. The Ipmax is a reference value of the primary side current peak. The primary side current is coupled to the secondary side circuit, then a positive secondary side current Is will flow from bottom to top through the secondary winding and through the body diode of Qs. The secondary side circuit detects the positive current Is and sets DRVS to a high level to turn Qs on. The positive current causes the source-drain voltage Vsd of Qs to become a high level. If Qs is a low side switch, the above conduction control mode can also be used when the gate voltage of Qs is lower than a predetermined negative value. If Qs is a high side switch, as shown in Figures 2 and 3, the above conduction control mode can also be employed when Vsws is higher than a predetermined secondary side turn-on trigger voltage Vs2. Subsequently, the current Is gradually decreases until it reaches zero.

After Is reaches zero value, the secondary side controller keeps DRVS high and keeps Qs on. Because there is capacitance in the secondary side circuit, Is will commutate to a negative value after its zero value, becoming a negative tail current. At time t2, the tail current reaches its tail current peak Is0, and DRVS is set to a low level to turn Qs off. At the same time, a negative coupling current is generated on the primary side, the peak value of which is Irp, causing Vswp to discharge through C1. When Vswp is discharged to zero, DRVP is set to a high level, turning Qp on. In actual operation, a value Vp2 equal to or close to zero is used as the primary side conduction trigger voltage. When Vswp falls to Vp2, DRVP is set to a high level and Qp is turned on. Thereafter, Ip is increased, and the primary side current reference peak value Ipmax as described at time t1 is reached at time t3. As previously mentioned, in one embodiment, the peak current peak is fed through the input voltage Vin through Vsws. As Vin increases, the energy required to discharge Vswp to zero also increases accordingly. At the same time, the peak value of Vsws increases with the increase of Vin. By detecting Vsws, the secondary side controller increases the tail current peak Is0 based on the peak value of Vsws. Since the peak current Irp coupled to the primary side is proportional to Is0, Irp also increases to ensure that more energy discharges Vswp to zero.

Conversely, if the input voltage Vin decreases and Irp decreases accordingly, the conduction loss of Qp decreases. Therefore, Is0 and Vsws change in the same direction. This adaptive control ensures that the current coupled to the primary side is large enough to discharge C1 and small enough to turn Qp on to reduce the conduction loss of Qp.

In other embodiments, the feedback control achieves an accurate adjustment of the output voltage Vout by combining simple control with tail current control without the need for an auxiliary isolation device. This control method is implemented by using the output voltage Vout or the output current to adjust the tail current peak. During the load up response process, the output voltage Vout decreases or the output current increases. The secondary side controller detects this change and increases Is0 accordingly. By detecting the coupled current peak value Irp on the primary side, the primary side controller correspondingly increases the primary side current reference peak value Ipmax to adjust the output voltage Vout. During the load down response process, Ipmax decreases as Irp decreases. In other words, the primary side current reference peak Ipmax changes in the same direction as the primary side coupling current peak value Irp.

Figure 4 shows a circuit schematic for implementing tail current feedback control. As shown, it is a flyback voltage converter including a transformer T1, a discharge capacitor C1, a primary side switch Qp, a primary side controller 10, a secondary side synchronous rectifier Qs, a smoothing capacitor Cout, and a secondary side control. 20. The primary side controller 10 includes a first comparator U1, a second comparator U2, an Ipmax reference voltage generator 11, and a latch U3. The Ipmax reference voltage generator 11 receives the peak current Irp coupled to the primary side, and generates a reference voltage Vp1 in the same direction as Irp based on Irp. As the coupled peak current Irp increases, Vp1 increases. The inverting input of the comparator U1 is coupled to the output of the reference voltage generator 11, and the non-inverting input is coupled to the voltage Vpi. Where Vpi is the detected value of the primary side current Ip. And the ratio of the reference voltage Vp1 to the primary side current reference peak Ipmax is equal to the ratio of the primary side current detection value Vpi to the primary side current Ip. The inverting input of comparator U2 receives the drain voltage signal Vswp of the primary side switch Qp, and its non-inverting input receives the reference voltage Vp2. Wherein, the reference voltage Vp2 is a primary side switch conduction trigger voltage. The output terminal of the comparator U1 is coupled to the reset input terminal R of the latch U3, and the output terminal of the comparator U2 is coupled to the set input terminal S of the latch U3. The output of the latch U3 is coupled to the gate of Qp, and outputs a primary side gate drive signal DRVP.

The secondary side controller 20 includes a first comparator U4, a second comparator U5, a tail current peak reference voltage generator 21, and a latch U6. The tail current peak reference voltage generator 21 receives the output voltage Vout of the converter or the output current to generate a reference voltage Vs1 characterizing the tail current peak Is0, and the change of the reference voltage Vs1 is opposite to the change of the output voltage Vout, and the output current Change the same direction. The comparator U4 receives the reference voltage Vs1 at the inverting input and receives a voltage signal Vsi indicative of the negative value of the secondary side current Is at its non-inverting input. The ratio of Vs1 to Is0 is equal to the ratio of Vsi to |-Is|. Comparator U5 receives the source voltage Vsws of the secondary side rectifier Qs at its non-inverting input and receives the secondary side reference trigger voltage Vs2 at its inverting input. The output terminal of the comparator U4 is coupled to the reset input terminal R of the latch U6, and the output terminal of the comparator U5 is coupled to the set input terminal S of the latch U6. The output of latch U6 is coupled to the gate of rectifier Qs and outputs a signal DRVS to drive Qs. The secondary side controller 20 can also incorporate a secondary side synchronous rectifier as part of the controller.

FIG. 5 is a timing diagram showing the timing of adjusting the converter output by using a control method combining Bang-Bang control and tail current control shown in FIG. 3 according to still another embodiment of the present invention. According to a further embodiment of the invention, the hysteresis control is set to have a higher priority than the tail current control, and the output voltage is limited between an upper threshold Vo_up and a lower threshold Vo_low by hysteresis control. It is first assumed that Qp and Qs operate in the same manner as described in FIG. 3, and the output voltage Vout is between the upper threshold Vo_up and the lower threshold Vo_low. Once Vout is greater than Vo_up, Qp and Qs suspend the switching action until Vout falls back below Vo_low. The control method combining the hysteresis control and the tail current control will be described below based on the timing waveform diagram shown in FIG. The signals shown in FIG. 5 are in order: Vout, Vswp, Ip, DRVP, Vsws, Is, and DRVS. At time t1, the primary side controller detects Ip > Ipmax, thus setting DRVP to a low level to turn off Qp, which causes a positive current to flow through the secondary side, thereby causing Vsws to go high. At this time, although Vsws>Vs2, but there is Vout>Vo_up at the same time, and the latter has a higher priority, the DRVS remains at a low level until Vout<Vo_low. At time t2, Vout reaches Vo_low and the secondary side controller turns Qs back on. At this point, a negative tail current is generated from the Qs source to the drain. The subsequent control process returns to the normal tail current control as described in FIG.

At time t3, the negative tail current reaches the tail current peak Is0, and the secondary side controller sets DRVS to the low level to turn off Qs, so that the primary side generates a negative coupling current, and Vswp is discharged through C1 to Below Vp2, Qp is turned on. Vp2 is equal to zero or close to zero. Hysteresis control allows the switches Qp and Qs to be turned off during periods of Vout from greater than Vo_up to less than Vo_low under light load conditions, thereby reducing switching losses and improving converter efficiency.

As shown in FIG. 6, it is a circuit diagram combining hysteresis control and tail current control, which corresponds to the timing waveform diagram shown in FIG. Next, the operation of the primary side controller 30 and the secondary side controller 40 will be described in detail.

The primary side controller 30 includes a comparator U1, a comparator U2, and a latch U3. The comparator U1 receives at its non-inverting input a voltage signal Vpi proportional to the primary side current Ip, and its inverting input receives a reference voltage Vp1. The output of the comparator U1 is coupled to the reset input terminal R of the RS latch U3. The ratio of Vpi to Ip is equal to the ratio of Vp1 and Ipmax. The comparator U2 receives the reference voltage Vp2 at its non-inverting input terminal and receives the drain voltage Vswp of the primary side switch Qp at its inverting input terminal. The output of the comparator U2 is coupled to the set input S of the RS latch U3. The output of U3 is coupled to the gate of switch Qp. U3 outputs a signal DRVP to control switch Qp. When Ip>Ipmax, Vpi>Vp1, comparator U1 outputs a logic "1", and U3 is reset, so that the output DRVP signal is logic "0", thereby turning off Qp. When the tail current reaches Is0, as shown in FIG. 3, Qs is turned off, and a maximum negative current, that is, the primary side coupling current peak value Irp, and Irp=n1/n2*Is0 are generated on the primary side. Where n1 is the primary side winding turns and n2 is the secondary side winding turns. This negative current Irp causes Vswp to discharge via C1, causing Vswp < Vp2, and comparator U2 outputs a logic value of "1" to set DRVP to a high level. Where Vp2 is equal to or close to zero voltage. Therefore, Qp is turned on at zero voltage. Capacitor C1 implements the zero voltage switching (ZVS) function of Qp. Capacitor C1 should be selected to meet the following conditions:

among them,

The capacitor Cp is formed by connecting parasitic capacitors of the capacitors C1 and Qp in parallel, and Lp is the inductance of the primary winding. When Qp is turned off when Ip reaches Ipmax, C1 is used as its shutdown buffer.

It is to be noted that the primary side controller 10 of FIG. 4 and the primary side controller 30 of FIG. 6 have other equivalent embodiments that can achieve the same control functions. For example, the drain-source voltage (Vswp) detection circuit, the primary side current (Ip) detection circuit, the generators of the reference voltages Vp1 and Vp2, and the gate drive circuit may be further included. The input of the gate driving circuit is coupled to the output of the latch U3, and the output of the gate driving circuit is coupled to the gate of the Qp. The primary side controllers 10 and 30 can also employ other types of RS latches.

The secondary side controller 40 is used to control the on and off of the Qs, and includes a first comparator U4, a second comparator U5, a third comparator U6, a fourth comparator U7, and a first RS latch U8. a second RS latch U9, a third RS latch U10, a fourth RS latch U11, a fifth RS latch U12, a first OR gate U13, a second OR gate U14, and a resistor R1 and R2 constitutes an output voltage detection circuit. The comparator U4 receives the signal Vo1 at its inverting input terminal, and receives the lower threshold reference voltage Vth1 at its non-inverting input terminal, and its output terminal is coupled to the reset input terminal R of the latch U8 and the set input terminal S of the latch U9. Vo1 is a voltage signal obtained by dividing the resistors R1 and R2 in proportion to the output voltage Vout.

The comparator U5 receives the signal Vo1 at its non-inverting input terminal, receives the upper threshold reference voltage Vth2 at its inverting input terminal, and its output terminal is coupled to the set input terminal S of the latch U8. Wherein, Vth1 represents the aforementioned lower threshold Vo_low, Vth2 represents the aforementioned upper threshold Vo_up, and the ratio of Vth1 to Vo_low and the ratio of Vth2 to Vo_up are equal to the ratio of Vo1 to Vout. The comparator U6 receives at its non-inverting input terminal a voltage signal Vsi proportional to the negative value of the secondary side current, receives the tail current peak reference voltage Vs1 at its inverting input terminal, and has its output coupled to the set input of the latch U11. End S. When the secondary side current Is flows from the drain of Qs to the source as a negative current, Vsi is a positive value. The ratio of the absolute values of Vsi to Is is equal to the ratio of Vs1 to Is0.

The comparator U7 receives the source voltage Vsws of the secondary side rectifier Qs at its non-inverting input terminal, receives the secondary side reference trigger voltage Vs2 at its inverting input terminal, and has its output terminal coupled to the reset input terminal R of the latch U11 and The input terminal S of the latch U12. The output of the RS latch U8 is coupled to the reset input terminal R of the latch U9 and an input terminal of the OR gate U13. The output of the RS latch U9 is coupled to the set input S of the latch U10. The output of the latch U10 is coupled to an input of the gate U14. The output of the latch U11 is coupled to the other output of the gate U13 and the reset input R of the latch U10. The output of the OR gate U13 is coupled to the re-input R of the RS latch U12. The output of the latch U12 is coupled to the other input of the gate U14. Or the output of the gate U14 is coupled to the gate of the Qs. U14 outputs the DRVS signal to control the turn-on and turn-off of Qs. When Qp is turned off, the secondary side produces a positive current and boosts Vsws. When Vsws > Vs2 is detected, comparator U7 outputs a logic "1" and sets RS latch U12 high, turning on Qs. The secondary side current Is gradually decreases to zero and then becomes a negative tail current. When this tail current exceeds the tail current peak Is0, that is: Vsi>Vs1, the comparator U6 outputs a logic "1", sets the latch U11 to a high level, and U10 resets to a low level. At the same time, OR gate U13 outputs a logic "1" to reset latch U12 to a low level, so or gate U14 outputs a low level DRVS signal to turn Qs off. At the turn-off point of Qs, Vswp is discharged to zero via C1, turning Qp back on.

Hysteresis control will be described below with reference to FIG. When the output voltage Vout increases and Vout>Vo_up or Vo1>Vth2, the comparator U5 outputs a logic "1", sets the latch U8 and or the gate U13 to a high level, and the latches U9 and U12 are set to Low level. Latch U10 maintains an output logic "0", or gate U14 outputs a low level DRVS signal to turn Qs off. When Qs is turned off when the secondary side current is zero, the secondary side winding leakage inductance and the parasitic capacitance of Qs will cause voltage oscillation, causing Vsws to reach the secondary side conduction trigger voltage Vs2, and Qs is turned on. To avoid this false trigger, add transistor Q3. Here, an NPN transistor is used, the base of which is coupled to the output of the latch U8, coupled to the ground, and the collector is coupled to the DRVS terminal. When Vo1>Vth2, Q3 is turned on and DRVS is pulled down to the low level to ensure that Qs is in the off state. Since Qs is turned off when Vo1>Vth2, no tail current is generated, so Qp also remains off. Qp and Qs remain in the off state until Vo1 < Vth1. At this time, the latch U9 is set to a high level, and the DRVS is set to a high level to turn on Qs. Thereafter the control enters the steady state tail current control mode.

The secondary side controller 20 of FIG. 4 and the secondary side controller 40 of FIG. 6 may further have other equivalent replacements to achieve the same function. For example, an error amplifier can be used to replace the output voltage detection circuit composed of R1 and R2, and the output error signal is used to compare with the upper threshold and the lower threshold to achieve hysteresis control. The secondary side controllers 20 and 40 may further include one or more such as an output current detecting circuit, a secondary side current detecting circuit, a secondary side switch drain voltage detecting circuit, a reference voltage generator, and a secondary side switch. Gate drive circuit. Secondary side controllers 20 and 40 may also incorporate a secondary side synchronous rectifier as part of the controller.

In summary, one advantage of the tail current control of the present invention is that when the secondary side rectifier is turned off by the tail current, the negative current coupled to the primary side can pull the drain-source voltage of the primary side switch to zero. Thus, zero voltage switching (ZVS) is achieved, thereby reducing electromagnetic interference (EMI) and reducing switching losses. In other embodiments, feedback is achieved by adjusting the tail current peak based on load information on the secondary side without the use of an optocoupler or an auxiliary winding. The load information on the secondary side can be reflected to the primary side and detected for higher efficiency and higher output accuracy.

7, 8A and 8B are diagrams showing test signal waveforms of the circuit shown in Fig. 6. Fig. 7 sequentially shows steady-state waveform diagrams of the signals DRVP, DRVS, Ip, and Is. The main parameters of the circuit are set as follows: input voltage Vin=60V, output voltage Vout=12V, output current Iout=1A. As can be seen from Figure 7, the secondary side synchronous rectifier is turned off at the negative tail current peak and simultaneously produces a negative current on the primary side. This primary side negative current pulls Vswp to a low level and DRVP is set to a high level to turn the primary side switch on. When the primary side current Ip is increased to the primary side current peak reference voltage value, DRVP is set to logic "0".

Fig. 8A shows a waveform diagram of the above signals for a longer period of time than that of Fig. 7 using hysteresis control. The waveform shown in Fig. 8A is still obtained in the case where the circuit parameters are set to: input voltage Vin = 60 V, output voltage Vout = 12 V, and output current Iout = 1 A. At the dotted line in the middle of Fig. 8A, Vout > Vo_up, DRVS is set to a low level. The remaining positive current on the secondary side flows through the body diode of the secondary side rectifier and gradually decreases to zero. The signals DRVP and DRVS remain at a low level until Vout < Vo_low. As shown at the middle dotted line in Fig. 8B, when Vout < Vo_low, the DRVS is immediately set to a high level, and a tail current is generated, and the circuit enters a steady state operation mode.

The combination of tail current control and hysteresis control automatically adjusts the output voltage and operating frequency. In the case of heavy loads, the pause state of the primary side switch and the secondary side rectifier is longer than the duration of the corresponding pause operation state under light load conditions. Therefore, the switching loss is relatively small under light load conditions, and the efficiency is naturally relatively high.

The above description and embodiments of the present invention are merely exemplary methods and control devices for tail current controlled isolated converters and are not intended to limit the scope of the invention. Variations and modifications of the disclosed embodiments are possible, and other possible alternative embodiments and equivalent variations to the elements of the embodiments will be apparent to those of ordinary skill in the art. Other variations and modifications of the disclosed embodiments of the invention do not depart from the spirit and scope of the invention.

T1. . . transformer

Qp. . . Primary side switch

C1. . . Capacitor

Qs. . . Secondary synchronous rectifier

Cout. . . Filter capacitor

10. . . Primary side controller

20. . . Secondary side controller

U1. . . First comparator

U2. . . Second comparator

11. . . Ipmax reference voltage generator

U3. . . Latches

U4. . . First comparator

U5. . . Second comparator

twenty one. . . Tail current peak reference voltage generator

U6. . . Third comparator

30. . . Primary side controller

40. . . Secondary side controller

U7. . . Fourth comparator

U8. . . First RS latch

U9. . . Second RS latch

U10. . . Third RS latch

U11. . . Fourth RS latch

U12. . . Fifth RS latch

U13. . . First or gate

U14. . . Second or gate

R1. . . Resistor

R2. . . Resistor

The following figures illustrate embodiments of the invention. These figures and embodiments provide some embodiments of the invention in a non-limiting, non-exhaustive manner.

Figure 1 shows a prior art quasi-resonant converter topology;

2 is a schematic diagram of a flyback voltage DC converter according to an embodiment of the present invention;

3 is a timing diagram of an isolated converter employing tail current control in accordance with one embodiment of the present invention;

4 is a circuit diagram of implementing tail current feedback control according to an embodiment of the present invention;

5 is a timing chart showing an operation of an isolated converter using hysteresis control and tail current control according to still another embodiment of the present invention;

FIG. 6 is a schematic diagram of a circuit according to another embodiment of the present invention as shown in FIG. 5; FIG.

Figure 7 is a steady-state waveform diagram of each signal in the circuit shown in Figure 6 in the tail current control mode;

8A and 8B are waveform diagrams of the signals in the circuit shown in FIG. 6 in the case of a hysteresis control mode;

T1. . . transformer

Qp. . . Primary side switch

C1. . . Capacitor

Qs. . . Secondary synchronous rectifier

Cout. . . Filter capacitor

Claims (36)

An isolated voltage converter for powering a load includes: a primary side circuit including a primary side switch and a primary side controller; and a secondary side circuit including a secondary side switch and a secondary side controller, wherein: The secondary side controller controls the secondary side switch to continue to conduct when the secondary side current reaches a zero value, so that the secondary side current is commutated to a negative tail current and has a path, and the tail current reaches the tail When the current peaks, the secondary side switch is turned off; at the same time, the tail current is coupled to a negative primary side coupling current in the primary side circuit, and the primary side switch is controlled by the primary side controller; and the secondary side control When the load is increased, the peak value of the tail current is increased, and when the load is reduced, the peak value of the tail current is decreased. The isolated voltage converter of claim 1, wherein the secondary side circuit further comprises an output capacitor coupled between the output of the isolated voltage converter and ground. The isolated voltage converter of claim 1, wherein the primary side switch is connected in parallel with the first capacitor, and the primary side controller has a drain voltage lower than the set primary side of the primary side switch When the trigger voltage is referenced, the primary side switch is turned on. The isolated voltage converter of claim 3, wherein the primary side reference trigger voltage is equal to zero or close to zero. Isolated voltage conversion as described in claim 3 The primary side controller turns off the primary side switch when the primary side current increases to the primary side current reference peak. The isolated voltage converter of claim 1, wherein the secondary side controller turns on the secondary side switch when the secondary side current increases to a preset current value. The isolated voltage converter of claim 1, wherein the secondary side controller has the secondary side when the source-drain voltage of the secondary side switch is higher than a preset voltage value The switch is turned on. The isolated voltage converter of claim 5, wherein the primary side controller detects a peak of the primary side coupling current and causes the primary side current reference peak to change in the same direction as the primary side coupled current peak. . The isolated voltage converter of claim 1, wherein the secondary side controller turns off the secondary side switch and keeps it off when the output voltage is higher than a set upper threshold. State until the output voltage is below the set lower threshold. The isolated voltage converter of claim 1, wherein the tail current peak value changes in the same direction as the source voltage peak of the secondary side switch. The isolated voltage converter of claim 1, wherein the secondary side open relationship is connected in parallel with the second capacitor. The isolated voltage converter of claim 5 or 8, wherein the primary side controller comprises: a primary side reference voltage generator for receiving the primary side coupling current Peak, and based on the primary side coupling current peak, outputs a primary side reference voltage indicative of the primary side current reference peak in the same direction as the primary side; a primary side first comparator having an inverting input coupled to the primary side reference voltage generator The output terminal receives the primary side reference voltage, and the non-inverting input terminal receives the detected value of the primary side current; the primary side second comparator has an inverting input terminal receiving the drain voltage of the primary side switch, and the non-inverting input thereof Receiving the primary side reference trigger voltage; and a primary side RS latch having a reset input coupled to the output of the primary side first comparator, the set input being coupled to the output of the primary side second comparator It outputs the gate control signal of the primary side switch. The isolated voltage converter of claim 12, wherein the primary side controller further comprises one or more voltage detecting circuits, current detecting circuits, reference voltage generators, and gate driving circuits. The isolated voltage converter of claim 7, wherein the secondary side controller comprises: a secondary side reference voltage generator for receiving an output voltage or current and generating a peak characterizing the tail current a secondary side first comparator, the inverting input end of which is coupled to the output of the secondary side reference voltage generator, receives the secondary side reference voltage, and the non-inverting input terminal is coupled to represent the secondary a voltage signal of a negative value of the side current; a second comparator of the secondary side, wherein the inverting input end is coupled to the secondary side reference trigger voltage, and the non-inverting input end is coupled to the source voltage of the secondary side switch; a secondary side RS latch having a reset input coupled to the output of the secondary side first comparator, the set input coupled to the output of the secondary side second comparator, the output of the secondary side The gate control signal of the switch. The isolated voltage converter of claim 14, wherein the secondary side reference voltage generator receives an output current to generate a secondary side reference voltage that varies in the same direction as the output current. The isolated voltage converter of claim 14, wherein the secondary side reference voltage generator receives the output voltage to generate a secondary side reference voltage that varies inversely with the output voltage. The isolated voltage converter of claim 14, wherein the secondary side controller further comprises one or more current detecting circuits, a voltage detecting circuit, a reference voltage generator, and a gate driving circuit. The isolated voltage converter of claim 9, wherein the primary side controller comprises: a primary side reference voltage generator for receiving the primary side coupling current peak value and based on the primary side coupling current peak value And generating a primary side reference voltage characterization of the primary side current reference peak in the same direction; the primary side first comparator receives the primary side current detection value at the non-inverting input terminal, and the inverting input terminal receives the primary side reference a second comparator of the primary side, the inverting input receiving the drain voltage of the primary side switch, the non-inverting input receiving the primary side reference trigger voltage, and the primary side RS latch having a reset input coupled thereto Primary side first The output end of the comparator is coupled to the output of the primary side second comparator, which outputs a control signal of the primary side switch. The isolated voltage converter of claim 9, wherein the secondary side controller further comprises: an output voltage detecting circuit for receiving the output voltage to generate a voltage detect proportional to the output voltage a signal; a secondary side first comparator having an inverting input receiving the voltage detection signal, a non-inverting input receiving a reference voltage indicative of the lower threshold; and a secondary side second comparator having a non-inverting input receiving the same a voltage detection signal having an inverting input receiving a reference voltage indicative of the upper threshold; a secondary side third comparator having a non-inverting input receiving a voltage signal proportional to a negative value of the secondary side current, the inverting input The terminal receives the reference voltage representing the peak value of the tail current; the fourth comparator of the secondary side receives the source voltage of the secondary side switch at the non-inverting input terminal, and receives the secondary side reference trigger voltage at the inverting input end; The RS latch has a reset input coupled to the output of the secondary side first comparator, a set input coupled to the output of the secondary side second comparator; and a secondary side second RS latch , its design The input end is coupled to the output end of the secondary side first comparator, the reset input end is coupled to the output end of the secondary side first RS latch; the secondary side third RS latch is set to the input end The output end of the secondary side second RS latch is coupled to the output end of the secondary side fourth RS latch; a secondary side fourth RS latch having a set input coupled to the output of the secondary side third comparator, the reset input coupled to the output of the secondary side fourth comparator; the secondary side a fifth RS latch having a set input coupled to the output of the fourth side comparator of the secondary side, the reset input coupled to the output of the first or gate of the secondary side; and the first or gate of the secondary side, wherein One input end is coupled to the output end of the secondary side first RS latch, and the other input end is coupled to the output end of the secondary side fourth RS latch; the secondary side second or gate, one of the The input end is coupled to the output end of the secondary side third RS latch, and the other input end is coupled to the output end of the secondary side fifth RS latch, which outputs the gate control signal of the secondary side switch . The isolated voltage converter of claim 19, wherein the secondary side controller further comprises an NPN transistor, the base of the NPN transistor being coupled to the secondary side first RS lock The output of the register has an emitter coupled to the ground and a collector coupled to the output of the secondary or second gate. The isolated voltage converter of claim 19, wherein the output voltage detecting circuit comprises an error amplifier. A secondary side controller that controls a secondary side switch of the isolated converter to keep the secondary side switch conducting when the secondary side current is reduced to zero, so that the secondary side current commutation is negative a tail current having a path; when the tail current reaches a peak current peak, the secondary side switch is turned off; The secondary side controller increases the peak value of the tail current when the load is increased, and reduces the peak value of the tail current when the load is reduced. The secondary side controller of claim 22, wherein the secondary side current is turned on when the secondary side current reaches a predetermined current value. The secondary side controller of claim 23, wherein when the output voltage of the isolated converter is higher than a set upper threshold, the secondary side switch is turned off until the output voltage is lower than a setting. The lower threshold is up. The secondary side controller of claim 22, comprising: a secondary side reference voltage generator for receiving an output voltage or current and generating a secondary side reference voltage indicative of a peak current peak; a side first comparator having an inverting input coupled to an output of the secondary side reference voltage generator, receiving the secondary side reference voltage, and a noninverting input coupled to a voltage representative of a negative value of the secondary side current a secondary side second comparator having an inverting input coupled to the secondary side reference trigger voltage, a non-inverting input coupled to the source voltage of the secondary side switch, and a secondary side RS latch to be reset The input end is coupled to the output end of the second side first comparator, and the set input end is coupled to the output end of the second side second comparator, which outputs a gate control signal of the secondary side switch. The secondary side controller of claim 25, wherein the secondary side reference voltage generator receives an output current to generate a secondary side reference voltage that varies in the same direction as the output current. The secondary side controller of claim 25, wherein the secondary side reference voltage generator receives the output voltage to generate a secondary side reference voltage that varies inversely with the output voltage. The secondary side controller of claim 24, comprising: an output voltage detecting circuit for receiving the output voltage and generating a voltage detecting signal proportional to the output voltage; the first comparator The inverting input terminal receives the voltage detection signal, and the non-inverting input terminal receives the reference voltage representing the lower threshold; the second comparator receives the voltage detection signal at the non-inverting input terminal, and the inverting input terminal receives the characteristic a reference voltage of an upper threshold; a third comparator having a non-inverting input receiving a voltage signal proportional to a negative value of the secondary side current, an inverting input receiving a reference voltage indicative of a peak current peak; and a fourth comparator The non-inverting input terminal receives the source voltage of the secondary side switch, and the inverting input terminal receives the secondary side reference trigger voltage; the first RS latch has a reset input end coupled to the output end of the first comparator, The set input terminal is coupled to the output end of the second comparator; the second RS latch is configured to be coupled to the output end of the first comparator, and the reset input end is coupled to the first RS latch Output a third RS latch having a set input coupled to the output of the second RS latch, a reset input coupled to the output of the fourth RS latch, and a fourth RS latch configured to input The end is coupled to the third comparator The output terminal has a reset input coupled to the output of the fourth comparator; a fifth RS latch having a set input coupled to the output of the fourth comparator, the reset input coupled to the first gate An output of the first OR gate, wherein one input is coupled to the output of the first RS latch, and the other input is coupled to the output of the fourth RS latch; The input end is coupled to the output end of the third RS latch, and the other input end is coupled to the output end of the fifth RS latch, which outputs a gate control signal of the secondary side switch. The secondary side controller of claim 28, further comprising an NPN transistor having a base coupled to the output of the first RS latch and having an emitter The system is coupled to the ground, and its collector is coupled to the output of the second OR gate. The secondary side controller of claim 28, wherein the output voltage detecting circuit comprises an error amplifier. A method for controlling an isolated converter, comprising: maintaining a secondary side switch conducting when a secondary side current reaches a zero value, such that the secondary side current is commutated to a negative tail current to have a path; and When the tail current reaches the tail current peak, the secondary side switch is turned off, and a negative primary side coupling current is coupled to the primary side to turn on the primary side switch; wherein the peak current peak changes in the same direction as the load change. The control method of the isolated converter according to claim 31, wherein the negative primary side coupling current is discharged through a capacitor connected in parallel with the primary side switch; when the primary side switch is turned on When the pole voltage is pulled down to zero voltage or close to zero voltage, the primary side switch is turned on. The control method of the isolated converter according to claim 31, wherein the primary side switch is turned off when the positive primary side current reaches the primary side current reference peak. The control method of the isolated converter according to claim 33, wherein the change in the primary side current reference peak is the same as the peak change of the primary side coupling current. The control method of the isolated converter according to claim 33, further comprising detecting a peak of the primary side coupling current and causing the primary side coupling current peak to change in the same direction as the tail current peak. The control method of the isolated converter according to claim 31, wherein when the output voltage of the converter is higher than a set upper threshold, the secondary side switch is turned off until the output voltage is lower than the setting. The lower threshold is up.