TWI445142B - Display apparatus, integrated circuit module and integrated circuit - Google Patents
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本發明係關於一種顯示裝置，特別關於一種顯示裝置、積體電路模組及積體電路。The present invention relates to a display device, and more particularly to a display device, an integrated circuit module, and an integrated circuit.
顯示裝置由早期的陰極射線管(Cathode Ray Tube,CRT)顯示裝置發展至現今的液晶顯示(Liquid Crystal Display,LCD)裝置、有機發光二極體(Organic Light Emitting Diode,OLED)顯示裝置以及場發射顯示(Field Emission Display,FED)裝置，其體積及重量皆大幅的縮小，並廣泛應用於通訊、資訊及消費性電子等產品上。The display device has been developed from an early cathode ray tube (CRT) display device to a current liquid crystal display (LCD) device, an organic light emitting diode (OLED) display device, and field emission. The Field Emission Display (FED) device has been greatly reduced in size and weight, and is widely used in communication, information and consumer electronics.
以液晶顯示裝置為例，其製程可區分為薄膜電晶體製程(TFT Array Process)、濾光基板製程(CF Process)、中段液晶顯示面板製程(Cell Process)及模組化製程(Module Process)。於模組化製程中，將驅動電路與液晶顯示面板接合時，目前已有捲帶式自動接合(Tape Automatic Bonding,TAB)技術、晶粒軟膜接合(Chip On Film,COF)技術及玻璃覆晶接合(Chip On Glass,COG)技術。其中，為使液晶顯示裝置之體積大為縮減，於模組化製程中以玻璃覆晶接合(COG)技術為最可行之製程。在驅動電路於模組化製程中，積體電路與玻璃基板之接合的可靠度會決定液晶顯示裝置之顯示品質。Taking a liquid crystal display device as an example, the process can be divided into a TFT Array Process, a CF Process, a Cell Process, and a Module Process. In the modular process, when the driver circuit is bonded to the liquid crystal display panel, tape automatic bonding (TAB) technology, chip on film (COF) technology, and glass flip chip are currently available. Chip On Glass (COG) technology. Among them, in order to make the volume of the liquid crystal display device greatly reduced, the glass-clad bonding (COG) technology is the most feasible process in the modular process. In the modular process of the driver circuit, the reliability of the bonding of the integrated circuit to the glass substrate determines the display quality of the liquid crystal display device.
請參照圖1所示，習知之一種積體電路模組10包含一積體電路11、11'以及一基板12。積體電路11與另一積體電路11'相鄰設置於基板12上。Referring to FIG. 1 , a conventional integrated circuit module 10 includes an integrated circuit 11 , 11 ′ and a substrate 12 . The integrated circuit 11 is disposed on the substrate 12 adjacent to the other integrated circuit 11'.
積體電路11之一表面S具有二長邊M及兩相對短邊N1、N2，積體電路11具有一第一組接腳G13、G14、一第二組接腳G23、G24及一第三組接腳G33、G34。其中，接腳G13、G14分別設置於短邊N1、N2，並藉由積體電路11之內部線路電性連接；接腳G23、G24分別設置於短邊N1、N2，並藉由積體電路11之內部線路電性連接；接腳G33、G34分別設置於短邊N1、N2，並藉由積體電路11之內部線路電性連接。上述接腳係用以接收電源訊號以使積體電路11作動。One surface S of the integrated circuit 11 has two long sides M and two opposite short sides N1, N2, and the integrated circuit 11 has a first set of pins G13, G14, a second set of pins G23, G24 and a third Group pins G33, G34. The pins G13 and G14 are respectively disposed on the short sides N1 and N2, and are electrically connected by the internal lines of the integrated circuit 11; the pins G23 and G24 are respectively disposed on the short sides N1 and N2, and are integrated circuits. The internal wiring of the 11 is electrically connected; the pins G33 and G34 are respectively disposed on the short sides N1 and N2, and are electrically connected by the internal lines of the integrated circuit 11. The pins are used to receive a power signal to cause the integrated circuit 11 to operate.
基板12係為玻璃基板，並具有一第一組連接墊P13、P14、一第二組連接墊P23、P24及一第三組連接墊P33、P34。其中第一組連接墊P13、P14與第一組接腳G13、G14對應連結；第二組連接墊P23、P24與第一組接腳G23、G24對應連結；第三組連接墊P33、P34與第一組接腳G33、G34對應連結。另一積體電路11'相對應之各組接腳及與基板12之連接墊的連結係與積體電路11相同，於此不再贅述。The substrate 12 is a glass substrate and has a first set of connection pads P13, P14, a second set of connection pads P23, P24 and a third set of connection pads P33, P34. The first group of connection pads P13 and P14 are connected with the first group of pins G13 and G14; the second group of connection pads P23 and P24 are connected with the first group of pins G23 and G24; and the third group of connection pads P33 and P34 are The first set of pins G33 and G34 are correspondingly connected. The connection between the respective sets of pins corresponding to the integrated circuit 11' and the connection pads of the substrate 12 is the same as that of the integrated circuit 11, and will not be described herein.
另外，積體電路11係藉由基板之走線L01、L02、L03而將電源訊號傳送至積體電路11'。然而，由於顯示裝置趨向輕薄化，顯示面板中之玻璃基板於薄型化的情況下，容易產生撓曲的情況，以致於設置於玻璃基板上的積體電路產生接合不良的問題，特別是設置於短邊N1、N2的接腳。一旦積體電路11設置於短邊N2的接腳G14、G24、G34與基板12接合不良，會導致電源訊號無法傳送至積體電路11'，進而使得顯示面板產生暗帶(band mura)，而降低產品良率。Further, the integrated circuit 11 transmits a power signal to the integrated circuit 11' via the substrate traces L01, L02, and L03. However, since the display device tends to be thinner and lighter, the glass substrate in the display panel is likely to be deflected in the case of thinning, so that the integrated circuit provided on the glass substrate causes a problem of poor bonding, in particular, The pins of the short sides N1 and N2. Once the integrated circuit 11 is disposed on the short side N2, the pins G14, G24, and G34 are poorly bonded to the substrate 12, which may cause the power signal to be not transmitted to the integrated circuit 11', thereby causing the display panel to generate a band mura. Reduce product yield.
因此，如何提供一種顯示裝置、積體電路模組及積體電路可增加積體電路與基板之間連結之可靠度，以避免積體電路之接腳與基板之連接墊接合強度不佳而降低產品良率，進而確保顯示品質，已成為重要課題之一。Therefore, how to provide a display device, an integrated circuit module, and an integrated circuit can increase the reliability of the connection between the integrated circuit and the substrate, so as to prevent the bonding strength between the pin of the integrated circuit and the substrate from being poor. Product yield, and thus display quality, has become one of the important topics.
有鑑於上述課題，本發明之目的為提供一種能夠增加積體電路之接腳與基板之連接墊的接合強度，以提升積體電路與基板之間連結之可靠度及產品良率，進而確保顯示品質之顯示裝置、積體電路模組及積體電路。In view of the above problems, an object of the present invention is to provide a joint strength capable of increasing a connection pad between a pin of an integrated circuit and a substrate, thereby improving reliability and product yield of the connection between the integrated circuit and the substrate, thereby ensuring display. Quality display device, integrated circuit module and integrated circuit.
為達上述目的，依據本發明之一種積體電路包含一第一組接腳。第一組接腳設置於積體電路之一表面並經由積體電路之線路而電性連接。表面具有一長邊及一短邊，且短邊較長邊短。第一組接腳之一第一部分設置於長邊，第一組接腳之一第二部分係設置於短邊。其中，第一組接腳之第一部分與第一組接腳之第二部分係經由積體電路之線路而電性連接，以接收與傳送相同的電源訊號。To achieve the above object, an integrated circuit in accordance with the present invention includes a first set of pins. The first set of pins are disposed on a surface of the integrated circuit and electrically connected via a line of the integrated circuit. The surface has a long side and a short side, and the short side is short and long. One of the first set of pins is disposed on the long side, and the second portion of the first set of pins is disposed on the short side. The first portion of the first set of pins and the second portion of the first set of pins are electrically connected via a line of the integrated circuit to receive and transmit the same power signal.
為達上述目的，依據本發明之一種積體電路模組包含一積體電路以及一基板。積體電路具有一第一組接腳設置於積體電路之一表面。表面具有一長邊及一短邊，且短邊較長邊短。第一組接腳之一第一部分係設置於長邊，第一組接腳之一第二部分係設置於短邊並經由積體電路之線路與第一組接腳之一第一部分電性連接。基板係具有一第一組走線及一第一組連接墊。第一組連接墊係藉由第一組走線而電性連接。積體電路設置於基板，且第一組接腳之第一部分與第一組連接墊之一第一部分相互連接。其中，第一組接腳之第一部分與第一組接腳之第二部分係接收與傳送相同的電源訊號。To achieve the above object, an integrated circuit module according to the present invention comprises an integrated circuit and a substrate. The integrated circuit has a first set of pins disposed on a surface of the integrated circuit. The surface has a long side and a short side, and the short side is short and long. The first portion of the first set of pins is disposed on the long side, and the second portion of the first set of pins is disposed on the short side and electrically connected to the first portion of the first set of pins via the line of the integrated circuit . The substrate has a first set of traces and a first set of connection pads. The first set of connection pads are electrically connected by a first set of traces. The integrated circuit is disposed on the substrate, and the first portion of the first set of pins is interconnected with the first portion of the first set of connection pads. The first portion of the first set of pins and the second portion of the first set of pins receive and transmit the same power signal.
為達上述目的，依據本發明之一種顯示裝置包含一驅動模組以及一顯示面板。顯示面板係藉由驅動模組驅動顯示。顯示面板具有一積體電路及一基板。積體電路具有一第一組接腳設置於積體電路之一表面。表面具有一長邊及一短邊，且短邊較長邊短。第一組接腳之一第一部分係設置於長邊，第一組接腳之一第二部分係設置於短邊並經由積體電路之線路與第一組接腳之一第一部分電性連接。基板係具有一第一組走線及一第一組連接墊。第一組連接墊係藉由第一組走線而電性連接。積體電路設置於基板，且第一組接腳之第一部分與第一組連接墊之一第一部分相互連接。其中，第一組接腳之第一部分與第一組接腳之第二部分係接收與傳送相同的電源訊號。To achieve the above object, a display device according to the present invention includes a driving module and a display panel. The display panel drives the display by the drive module. The display panel has an integrated circuit and a substrate. The integrated circuit has a first set of pins disposed on a surface of the integrated circuit. The surface has a long side and a short side, and the short side is short and long. The first portion of the first set of pins is disposed on the long side, and the second portion of the first set of pins is disposed on the short side and electrically connected to the first portion of the first set of pins via the line of the integrated circuit . The substrate has a first set of traces and a first set of connection pads. The first set of connection pads are electrically connected by a first set of traces. The integrated circuit is disposed on the substrate, and the first portion of the first set of pins is interconnected with the first portion of the first set of connection pads. The first portion of the first set of pins and the second portion of the first set of pins receive and transmit the same power signal.
承上所述，依據本發明之一種顯示裝置、積體電路模組及積體電路係將接腳設置於積體電路的長邊及短邊，且該等接腳不僅藉由積體電路之線路而電性連接，更藉由基板之走線而電性連接，以致得到雙重保護。此外，當基板撓曲時，積體電路之長邊所受到的應力較小，可確保接腳與基板之連結可靠度，進而提升產品良率並確保顯示品質。此外，本發明係定義接腳使得第一組接腳之第一部分係位於第二組接腳之第一部分之間，以致基板之走線不會交錯，故走線可佈設於基板之同一層，簡化基板佈線製程。According to the present invention, a display device, an integrated circuit module, and an integrated circuit according to the present invention are provided with pins on the long side and the short side of the integrated circuit, and the pins are not only integrated circuits The circuit is electrically connected, and is electrically connected by the wiring of the substrate, so that double protection is obtained. In addition, when the substrate is deflected, the long side of the integrated circuit is subjected to less stress, which ensures the reliability of the connection between the pin and the substrate, thereby improving product yield and ensuring display quality. In addition, the present invention defines a pin such that the first portion of the first set of pins is located between the first portions of the second set of pins, so that the traces of the substrate are not staggered, so the traces can be disposed on the same layer of the substrate. Simplify the substrate wiring process.
以下將參照相關圖式，說明依據本發明較佳實施例之一種顯示裝置、積體電路模組及積體電路。Hereinafter, a display device, an integrated circuit module, and an integrated circuit according to a preferred embodiment of the present invention will be described with reference to the related drawings.
請參照圖2所示，本發明第一實施例之一種積體電路模組20包含一積體電路21以及一基板22。積體電路21係設置於基板22上，本實施例係以積體電路21與另一積體電路21'相鄰設置為例說明。基板22具有兩個積體電路投影區A及A'用以設置積體電路21及積體電路21'。另外，以下的示意圖皆是從基板22往積體電路21之方向的視角。Referring to FIG. 2, an integrated circuit module 20 according to a first embodiment of the present invention includes an integrated circuit 21 and a substrate 22. The integrated circuit 21 is provided on the substrate 22. This embodiment is described by taking an integrated circuit 21 adjacent to another integrated circuit 21' as an example. The substrate 22 has two integrated circuit projection areas A and A' for setting the integrated circuit 21 and the integrated circuit 21'. In addition, the following schematic views are the viewing angles from the substrate 22 to the integrated circuit 21.
積體電路21具有一第一組接腳G1設置於積體電路21之一表面S並經由積體電路21之線路而電性連接。表面S具有一長邊M及一短邊N1，且短邊N1較長邊M短，本實施例之表面S具有兩相對短邊N1、N2。其中，第一組接腳G1之一第一部分G11、G12係設置於長邊M，因積體電路21之內部線路電性連接而使接腳G11及G12具有相等電位。接腳G11、G12係為導電元件，例如可為導電球，可設置於積體電路21或是基板22。The integrated circuit 21 has a first set of pins G1 disposed on one surface S of the integrated circuit 21 and electrically connected via a line of the integrated circuit 21. The surface S has a long side M and a short side N1, and the short side N1 has a long side M which is short. The surface S of the present embodiment has two opposite short sides N1, N2. The first portions G11 and G12 of the first set of pins G1 are disposed on the long side M, and the internal circuits of the integrated circuit 21 are electrically connected to cause the pins G11 and G12 to have the same potential. The pins G11 and G12 are conductive elements, and may be, for example, conductive balls, and may be disposed on the integrated circuit 21 or the substrate 22.
基板22包含透光材質，其例如但不限為玻璃基板、液晶顯示面板、發光二極體顯示面板或有機電激發光顯示面板。基板22係具有一第一組走線L1及一第一組連接墊P1。其中，第一組連接墊P1係藉由第一組走線L1而電性連接，且第一組接腳G1之第一部分G11、G12與第一組連接墊P1之一第一部分P11、P12相互連接。本實施例中，第一組走線L1之一第二部分係佈線於積體電路投影區A之內而使第一組連接墊P1之第一部分P11、P12電性連接，且通過積體電路投影區A而電性連接另一積體電路21'，並且第一組走線L1可連接設置於短邊之第一組接腳G1之一第二部分而電性連接積體電路21'，由於第一組接腳G1之第二部分在本實施例中係設置於基板22上，故圖2並未繪示。另外，本實施例係以積體電路21與位於其一側之積體電路21'電性連接為例，在其他實施例中，積體電路21可藉由上述技術而與位於其兩側之多個積體電路電性連接。The substrate 22 includes a light transmissive material, such as, but not limited to, a glass substrate, a liquid crystal display panel, a light emitting diode display panel, or an organic electroluminescent display panel. The substrate 22 has a first set of traces L1 and a first set of connection pads P1. The first group of connection pads P1 are electrically connected by the first group of wires L1, and the first portions G11 and G12 of the first group of pins G1 and the first portions P11 and P12 of the first group of connection pads P1 are mutually connected. connection. In this embodiment, the second portion of the first set of traces L1 is wired within the projection area A of the integrated circuit to electrically connect the first portions P11 and P12 of the first set of connection pads P1, and through the integrated circuit. The projection area A is electrically connected to the other integrated circuit 21', and the first group of the wires L1 can be connected to the second portion of the first group of pins G1 disposed on the short side to electrically connect the integrated circuit 21'. Since the second portion of the first set of pins G1 is disposed on the substrate 22 in this embodiment, FIG. 2 is not shown. In addition, in this embodiment, the integrated circuit 21 is electrically connected to the integrated circuit 21' located on one side thereof. In other embodiments, the integrated circuit 21 can be located on both sides by the above technology. A plurality of integrated circuits are electrically connected.
另外，第一組走線L1之第二部分亦可佈線於積體電路投影區A之外而使第一組連接墊P1之第一部分P11、P12電性連接。於本實施例中，第一組連接墊P1之間亦可設置無效連接墊(dummy pad)，另外，無效連接墊可設置於積體電路表面S或基板22。In addition, the second portion of the first set of traces L1 may be routed outside the integrated circuit projection area A to electrically connect the first portions P11 and P12 of the first set of connection pads P1. In this embodiment, an invalid dummy pad may be disposed between the first group of connection pads P1, and the invalid connection pad may be disposed on the integrated circuit surface S or the substrate 22.
於本實施例中，積體電路21更具有一第二組接腳G2設置於表面S並經由積體電路21之線路而電性連接，且與第一組接腳G1電性絕緣。第二組接腳G2之一第一部分G21、G22係設置於長邊M，且第一組接腳G1之第一部分G11、G12係位於第二組接腳G2之第一部分G21、G22之間。基板22係具有一第二組走線L2及一第二組連接墊P2。第二組接腳G2之第一部分G21、G22與第二組連接墊P2之一第一部分P21、P22相互連接。In the embodiment, the integrated circuit 21 has a second set of pins G2 disposed on the surface S and electrically connected via the lines of the integrated circuit 21, and is electrically insulated from the first set of pins G1. The first portions G21, G22 of one of the second set of pins G2 are disposed on the long side M, and the first portions G11, G12 of the first set of pins G1 are located between the first portions G21, G22 of the second set of pins G2. The substrate 22 has a second set of traces L2 and a second set of connection pads P2. The first portions G21, G22 of the second set of pins G2 and the first portions P21, P22 of the second set of connection pads P2 are connected to each other.
於本實施例中，第二組連接墊P2係藉由第二組走線L2而電性連接，第二組走線L2之一第一部分L21係繞設於積體電路投影區A之外而電性連接第二組連接墊P2之第一部分P21、P22。另外，第二組走線L2之一第二部分L22則通過積體電路投影區A以連接兩相鄰之積體電路21、21'之第二組連接墊P2之第一部分P21、P22，並且第二部分L22可連接設置於短邊之第二組接腳G2之一第二部分而電性連接積體電路21'，由於第二組接腳G2之第二部分在本實施例中係設置於基板22上，故圖2並未繪示。In this embodiment, the second group of connection pads P2 are electrically connected by the second group of wires L2, and the first portion L21 of the second group of wires L2 is wound around the projection area A of the integrated circuit. The first portions P21, P22 of the second group of connection pads P2 are electrically connected. In addition, the second portion L22 of one of the second set of traces L2 passes through the integrated circuit projection area A to connect the first portions P21, P22 of the second set of connection pads P2 of the two adjacent integrated circuits 21, 21', and The second portion L22 can be connected to the second portion of the second set of pins G2 disposed on the short side to electrically connect the integrated circuit 21', since the second portion of the second set of pins G2 is set in the embodiment. On the substrate 22, Figure 2 is not shown.
於本實施例中，積體電路21可更具有一第三組接腳G3設置於表面S並經由積體電路21之線路而電性連接且與第一組接腳G1及第二組接腳G2電性絕緣。第三組接腳G3之一第一部分G31、G32係設置於長邊M並比第一組接腳G1之第一部分G11、G12及第二組接腳G2之第一部分G21、G22更靠近短邊N1、N2。在本實施例中，第一組接腳G1、第二組接腳G2及第三組接腳G3係用以接收與傳送電源訊號。In this embodiment, the integrated circuit 21 can have a third set of pins G3 disposed on the surface S and electrically connected via the line of the integrated circuit 21 and coupled to the first set of pins G1 and the second set of pins. G2 is electrically insulated. The first portions G31 and G32 of the third group of pins G3 are disposed on the long side M and are closer to the short side than the first portions G11 and G12 of the first group of pins G1 and the first portions G21 and G22 of the second group of pins G2. N1, N2. In this embodiment, the first group of pins G1, the second group of pins G2, and the third group of pins G3 are used for receiving and transmitting power signals.
基板22更具有一第三組走線L3及一第三組連接墊P3。第三組連接墊P3係藉由第三組走線L3而電性連接。第三組接腳G3之第一部分G31、G32與第三組連接墊P3之一第一部分P31、P32相互連接。與上述相同，於本實施例中，為使第三組連接墊P3電性連接，基板22更具有第三組走線L3之一第一部分L31係繞設於積體電路投影區A之外而電性連接第三組連接墊P3之第一部分P31、P32；第三組走線L3之一第二部分L32則佈線於積體電路投影區A內部以連接兩相鄰之積體電路21、21'之第三組連接墊P3之第一部分P31、P32，並且第二部分L32可連接設置於短邊之第三組接腳G3之一第二部分而電性連接積體電路21'，由於第三組接腳G3之第二部分在本實施例中係設置於基板22上，故圖2並未繪示。The substrate 22 further has a third set of traces L3 and a third set of connection pads P3. The third set of connection pads P3 are electrically connected by a third set of traces L3. The first portions G31, G32 of the third set of pins G3 and the first portions P31, P32 of the third set of connection pads P3 are connected to each other. In the embodiment, in order to electrically connect the third group of connection pads P3, the substrate 22 further has a first portion L31 of the third group of traces L3 wound around the projection area A of the integrated circuit. Electrically connecting the first portion P31, P32 of the third group of connection pads P3; and the second portion L32 of the third group of routing lines L3 is wired inside the integrated circuit projection area A to connect the two adjacent integrated circuits 21, 21 The third group of connection pads P3, P31, P32, and the second portion L32 can be connected to the second portion of the third group of pins G3 disposed on the short side to electrically connect the integrated circuit 21', The second portion of the three sets of pins G3 is disposed on the substrate 22 in this embodiment, so that FIG. 2 is not shown.
於本實施例中，接腳之定義使得第一組接腳之第一部分係位於第二組接腳之第一部分之間，而第三組接腳又位於第一組接腳之第一部分及第二組接腳之第一部分之外，以致基板之走線不會交錯，故走線可佈設於基板之同一層，簡化基板佈線製程。In this embodiment, the pin is defined such that the first portion of the first set of pins is located between the first portions of the second set of pins, and the third set of pins is located between the first portion of the first set of pins and the first portion In addition to the first part of the two sets of pins, the traces of the substrate are not staggered, so the traces can be laid on the same layer of the substrate, simplifying the substrate routing process.
請參照圖3所示，本發明第一實施例之另一種積體電路模組20a包含一積體電路21、21'以及一基板22a。本實施例同樣以積體電路21與另一積體電路21'相鄰設置為例說明。基板22a具有兩個積體電路投影區A及A'用以設置積體電路21及積體電路21'。於本實施例中，積體電路21及積體電路21'之各組接腳設置與上述實施例之第一組接腳G1、第二組接腳G2及第三組接腳G3皆相同。基板22a之各組連接墊與上述實施例之第一組連接墊P1、第二組連接墊P2及第三組連接墊P3皆相同，於此不再贅述。本實施例之基板22a與上述實施例之基板22主要不同之處在於：基板22a更具有第一組走線L1之一第一部分L11係繞設於積體電路投影區A及A'之外而電性連接第一組連接墊P1之第一部分P11、P12，以提升訊號傳送之可靠度。Referring to FIG. 3, another integrated circuit module 20a according to the first embodiment of the present invention includes an integrated circuit 21, 21' and a substrate 22a. This embodiment is also described by taking an example in which the integrated circuit 21 is adjacent to another integrated circuit 21'. The substrate 22a has two integrated circuit projection areas A and A' for providing the integrated circuit 21 and the integrated circuit 21'. In the present embodiment, the set of pins of the integrated circuit 21 and the integrated circuit 21' are the same as those of the first set of pins G1, the second set of pins G2, and the third set of pins G3 of the above embodiment. Each of the connection pads of the substrate 22a is the same as the first group of connection pads P1, the second group of connection pads P2, and the third group of connection pads P3 of the above embodiment, and details are not described herein. The substrate 22a of the present embodiment is mainly different from the substrate 22 of the above embodiment in that the substrate 22a further has a first portion L11 of the first group of traces L1 wound around the projection areas A and A' of the integrated circuit. The first portions P11 and P12 of the first group of connection pads P1 are electrically connected to improve the reliability of signal transmission.
請參照圖4所示，本發明第二實施例之一種積體電路模組30包含一積體電路31、31'以及一基板32。於本實施例中，相鄰而設之積體電路31及31'同樣以玻璃覆晶製程設置於基板32之積體電路投影區A及A'上。Referring to FIG. 4, an integrated circuit module 30 according to a second embodiment of the present invention includes an integrated circuit 31, 31' and a substrate 32. In the present embodiment, the adjacent integrated circuits 31 and 31' are also disposed on the integrated circuit projection areas A and A' of the substrate 32 in a glass flip chip process.
於本實施例中，積體電路31之第一組接腳G1之第一部分G11、G12、第二組接腳G2之第一部分G21、G22及第三組接腳G3之第一部分G31、G32設置於長邊M；且第一組連接墊P1之第一部分P11、P12、第二組連接墊P2之第一部分P21、P22及第三組連接墊P3之第一部分P31、P32設置於長邊M，並與接腳對應連結。於本實施例中，第一組接腳G1之一第二部分G13係設置於短邊N1並與第一組連接墊P1之一第二部分P13連接。第二組接腳G2之一第二部分G23係設置於短邊N1並與第二組連接墊P2之一第二部分P23連接且較第一組接腳G1之第二部分G13更靠近長邊M。另外，本實施例可更具有第三組接腳G3之一第二部分G33係設置於短邊N1並與第三組連接墊P3之一第二部分P33連接。在本實施例中，接腳之第二部分G13、G23、G33係以設置於積體電路31為例。In this embodiment, the first portions G11 and G12 of the first group of pins G1 of the integrated circuit 31, the first portions G21 and G22 of the second group of pins G2, and the first portions G31 and G32 of the third group of pins G3 are disposed. The first portion P11, P12 of the first group of connection pads P1, the first portions P21, P22 of the second group of connection pads P2, and the first portions P31, P32 of the third group of connection pads P3 are disposed on the long side M, And corresponding to the pin. In this embodiment, the second portion G13 of one of the first set of pins G1 is disposed on the short side N1 and connected to the second portion P13 of one of the first set of connection pads P1. The second portion G23 of one of the second set of pins G2 is disposed on the short side N1 and is connected to the second portion P23 of one of the second set of connection pads P2 and closer to the long side than the second portion G13 of the first set of pins G1 M. In addition, the present embodiment may further have a second portion G33 of the third group of pins G3 disposed on the short side N1 and connected to the second portion P33 of one of the third group of connection pads P3. In the present embodiment, the second portions G13, G23, and G33 of the pins are provided in the integrated circuit 31 as an example.
於本實施例中，第一組走線L1之一第二部分L12電性連接第一組連接墊P1之第一部分P11、P12及其第二部分P13；第二組走線L2之一第二部分L22電性連接第二組連接墊P2之第一部分P21及其第二部分P23。另外，本實施例更具有第三組走線L3之一第二部分L32電性連接第三組連接墊P3之第一部分P31及其第二部分P33。In this embodiment, the second portion L12 of the first group of the wires L1 is electrically connected to the first portion P11, P12 and the second portion P13 of the first group of connection pads P1; The portion L22 is electrically connected to the first portion P21 of the second group of connection pads P2 and the second portion P23 thereof. In addition, the second portion L32 of the third group of the connection pads P3 is electrically connected to the first portion P31 of the third group of connection pads P3 and the second portion P33 thereof.
於本實施例中，積體電路31之表面S更具有另一短邊N2，該等短邊N1、N2相對而設。第一組接腳G1之一第三部分G14係設置於另短邊N2並與第一組連接墊P1之一第三部分P14連接。第二組接腳G2之一第三部分G24係設置於另該短邊N2並與第二組連接墊P2之一第三部分P24連接，且較第一組接腳G1之第三部分G14更靠近長邊M。另外，本實施例可更具有第三組接腳G3之一第三部分G34係設置於另該短邊N2並與第三組連接墊P3之一第三部分P34連接，且較第二組接腳G2之第三部分G24更靠近長邊M。In the present embodiment, the surface S of the integrated circuit 31 further has another short side N2, and the short sides N1 and N2 are opposite to each other. The third portion G14 of one of the first set of pins G1 is disposed on the other short side N2 and is connected to the third portion P14 of one of the first set of connection pads P1. The third portion G24 of one of the second set of pins G2 is disposed on the other short side N2 and connected to the third portion P24 of the second set of connection pads P2, and is more than the third portion G14 of the first set of pins G1. Close to the long side M. In addition, the third embodiment G34 of the third group of pins G3 is further disposed on the other short side N2 and connected to the third portion P34 of the third group of connection pads P3, and is connected to the second group. The third portion G24 of the foot G2 is closer to the long side M.
於本實施例中，第一組走線L1之第二部分L12更電性連接第一組連接墊P1之第一部分之連接墊P12及其第三部分P14，第二組走線L2之第二部分L22更電性連接第二組連接墊P2之第一部分P22及其第三部分P24。另外，本實施例之第三組走線L3之第二部分L32更電性連接第三組連接墊P3之第一部分P32及其第二部分P34。In this embodiment, the second portion L12 of the first group of the wires L1 is electrically connected to the connection pad P12 of the first portion of the first group of connection pads P1 and the third portion P14 thereof, and the second group of the second group L2 The portion L22 is more electrically connected to the first portion P22 of the second set of connection pads P2 and its third portion P24. In addition, the second portion L32 of the third group of the traces L3 of the embodiment is electrically connected to the first portion P32 of the third group of connection pads P3 and the second portion P34 thereof.
於本實施例中，第一組走線L1之第一部分L11通過積體電路投影區A而電性連接第一組連接墊之第一部分P11、P12。第二組走線L2之第一部分L21係繞設於積體電路投影區A之外，而電性連接第二組連接墊P2之第一部分P21、P22。第三組走線L3之第一部分L31係繞設於積體電路投影區A之外，而電性連接第三組連接墊P2之第一部分P31、P32。另外，於本實施例中，基板31之第一組走線L1、第二組走線L2及第三組走線L3係通過積體電路投影區A而電性連接另一積體電路31'。In this embodiment, the first portion L11 of the first set of traces L1 is electrically connected to the first portions P11, P12 of the first set of connection pads through the integrated circuit projection area A. The first portion L21 of the second set of traces L2 is disposed outside the integrated circuit projection area A, and is electrically connected to the first portions P21, P22 of the second set of connection pads P2. The first portion L31 of the third group of traces L3 is wound around the projection area A of the integrated circuit, and is electrically connected to the first portions P31, P32 of the third group of connection pads P2. In addition, in the embodiment, the first group of the traces L1, the second group of traces L2, and the third set of traces L3 of the substrate 31 are electrically connected to the other integrated circuit 31' through the integrated circuit projection area A. .
本實施例將接腳設置於積體電路之長邊，當短邊之接腳與基板接合不良時，長邊之接腳仍可藉由走線而將訊號傳送至另一積體電路，進而提升產品良率。In this embodiment, the pin is disposed on the long side of the integrated circuit. When the pin of the short side is not properly bonded to the substrate, the pin of the long side can still transmit the signal to another integrated circuit by routing, and then Improve product yield.
請參照圖5所示，本發明第二實施例之另一種積體電路模組30a包含一積體電路31、31'以及一基板32a。本實施例同樣以積體電路31與另一積體電路31'相鄰設置為例說明。基板32a具有兩個積體電路投影區A及A'用以設置積體電路31及積體電路31'。於本實施例中，積體電路31及積體電路31'之各組接腳設置與上述第二實施例之第一組接腳G1、第二組接腳G2及第三組接腳G3皆相同，於此不再贅述。基板32a之各組連接墊與上述第二實施例之第一組連接墊P1、第二組連接墊P2及第三組連接墊P3皆相同，於此不再贅述。本實施例之基板32a與上述實施例之基板32主要不同之處在於：第一組走線L1之一第一部分L11係繞設於積體電路投影區A之外而電性連接第一組連接墊P1之第一部分P11、P12。Referring to FIG. 5, another integrated circuit module 30a according to the second embodiment of the present invention includes an integrated circuit 31, 31' and a substrate 32a. This embodiment is also described by taking an example in which the integrated circuit 31 is adjacent to another integrated circuit 31'. The substrate 32a has two integrated circuit projection areas A and A' for arranging the integrated circuit 31 and the integrated circuit 31'. In this embodiment, each set of pins of the integrated circuit 31 and the integrated circuit 31' is disposed with the first set of pins G1, the second set of pins G2, and the third set of pins G3 of the second embodiment. The same, no longer repeat here. Each of the connection pads of the substrate 32a is the same as the first group of connection pads P1, the second group of connection pads P2, and the third group of connection pads P3 of the second embodiment, and details are not described herein. The substrate 32a of the present embodiment is mainly different from the substrate 32 of the above embodiment in that a first portion L11 of the first group of traces L1 is wound around the projection area A of the integrated circuit and electrically connected to the first group of connections. The first portions P11, P12 of the pad P1.
請參照圖6所示，本發明第三實施例之一種積體電路模組40包含一積體電路41、41'以及一基板42。於本實施例中，相鄰而設之積體電路41及另一積體電路41'同樣以玻璃覆晶製程設置於基板42之積體電路投影區A及A'上。Referring to FIG. 6, an integrated circuit module 40 according to a third embodiment of the present invention includes an integrated circuit 41, 41' and a substrate 42. In the present embodiment, the adjacent integrated circuit 41 and the other integrated circuit 41' are also disposed on the integrated circuit projection areas A and A' of the substrate 42 by a glass flip chip process.
於本實施例中，第一組接腳G1之一第二部分G13係設置於短邊N1並與第一組連接墊P1之一第二部分P13連接。第三組接腳G3之一第二部分G33係設置於短邊N1並與第三組連接墊P3之一第二部分P33連接，且較第一組接腳G1之第二部分G13更靠近長邊M。另外，於本實施例中，第一組走線L1之一第二部分L12電性連接第一組連接墊P1之第一部分P11及其第二部分P13；第三組走線L3之一第二部分L32電性連接第三組連接墊P3之第一部分P31及其第二部分P33。In this embodiment, the second portion G13 of one of the first set of pins G1 is disposed on the short side N1 and connected to the second portion P13 of one of the first set of connection pads P1. The second portion G33 of one of the third set of pins G3 is disposed on the short side N1 and is connected to the second portion P33 of one of the third set of connection pads P3, and is closer to the second portion G13 than the first set of pins G1. Side M. In addition, in this embodiment, the second portion L12 of the first group of the wires L1 is electrically connected to the first portion P11 of the first group of connection pads P1 and the second portion P13 thereof, and the second portion of the third group of wires L3 is second. The portion L32 is electrically connected to the first portion P31 of the third group of connection pads P3 and the second portion P33 thereof.
於本實施例中，積體電路41之表面S更具有另一短邊N2，該等短邊N1、N2相對而設。第一組接腳G1之一第三部分G14係設置於短邊N2並與第一組連接墊P1之一第三部分P14連接。第三組接腳G3之一第三部分G34係設置於短邊N2並與第三組連接墊P3之一第三部分P34連接，且較第一組接腳G1之第三部分G14更靠近長邊M。In the present embodiment, the surface S of the integrated circuit 41 further has another short side N2, and the short sides N1 and N2 are opposite to each other. The third portion G14 of one of the first set of pins G1 is disposed on the short side N2 and is coupled to the third portion P14 of one of the first set of connection pads P1. The third portion G34 of the third group of pins G3 is disposed on the short side N2 and is connected to the third portion P34 of the third group of connection pads P3, and is closer to the third portion G14 than the first group of pins G1. Side M.
於本實施例中，第一組走線L1之第二部分L12更電性連接第一組連接墊P1之第一部分P12及其第三部分P14，第三組走線L3之第二部分L32更電性連接第三組連接墊P3之第一部分P32及其第二部分P34。In this embodiment, the second portion L12 of the first group of wires L1 is electrically connected to the first portion P12 of the first group of connection pads P1 and the third portion P14 thereof, and the second portion L32 of the third group of wires L3 is further The first portion P32 of the third set of connection pads P3 and its second portion P34 are electrically connected.
本實施例與圖4所示之積體電路模組30之主要不同在於，積體電路41、41'之第二組接腳G2不包含設置於短邊N1、N2的第二部分及第三部分，且基板42之第二組連接墊P2亦無對應的第二部分及第三部分。另外，本實施例係藉由第二組走線L2之第二部分L22將積體電路41之第二組接腳G2與積體電路41'之第二組接腳電性連接。The main difference between the present embodiment and the integrated circuit module 30 shown in FIG. 4 is that the second set of pins G2 of the integrated circuits 41, 41' does not include the second portion and the third portion disposed on the short sides N1, N2. In part, the second set of connection pads P2 of the substrate 42 also has no corresponding second part and third part. In addition, in this embodiment, the second set of pins G2 of the integrated circuit 41 and the second set of pins of the integrated circuit 41' are electrically connected by the second portion L22 of the second set of traces L2.
請參照圖7所示，本發明第三實施例之另一種積體電路模組40a包含一積體電路41、41'以及一基板42a。本實施例同樣以積體電路41與另一積體電路41'相鄰設置為例說明。基板42a具有兩個積體電路投影區A及A'用以設置積體電路41及積體電路41'。於本實施例中，積體電路41及積體電路41'之各組接腳G1、G2、G3於長邊M及短邊N1、N2之配置與上述第三實施例之各組接腳設置皆相同，於此不再贅述。同樣地，基板42a之各組連接墊P1、P2、P3於長邊M及短邊N1、N2之配置與上述第三實施例之各組連接墊P1、P2、P3皆相同，於此不再贅述。本實施例之基板42a與上述實施例之基板42不同之處在於：第一組走線L1之一第一部分L11係繞設於積體電路投影區A、A'之外而電性連接第一組連接墊P1之第一部分P11及P12。Referring to FIG. 7, another integrated circuit module 40a according to a third embodiment of the present invention includes an integrated circuit 41, 41' and a substrate 42a. This embodiment is also described by taking an example in which the integrated circuit 41 is adjacent to another integrated circuit 41'. The substrate 42a has two integrated circuit projection areas A and A' for arranging the integrated circuit 41 and the integrated circuit 41'. In the present embodiment, the arrangement of the sets of pins G1, G2, and G3 of the integrated circuit 41 and the integrated circuit 41' on the long side M and the short sides N1, N2 and the set of pins of the third embodiment described above are set. All are the same and will not be described here. Similarly, the arrangement of the respective sets of connection pads P1, P2, P3 of the substrate 42a on the long side M and the short sides N1, N2 is the same as that of the respective sets of connection pads P1, P2, P3 of the third embodiment, and no longer Narration. The substrate 42a of the present embodiment is different from the substrate 42 of the above embodiment in that a first portion L11 of the first set of traces L1 is wound around the projection areas A, A' of the integrated circuit and electrically connected first. The group connects the first portions P11 and P12 of the pad P1.
請參照圖8所示，本發明較佳實施例之一種顯示裝置2包含一驅動模組23以及一顯示面板20'。顯示面板20'係藉由驅動模組23驅動顯示。顯示面板20'具有一積體電路21及一基板22。積體電路21及基板22之構造、材質及配置已於上述第一實施例之積體電路模組20詳述，於此不再贅述，其中積體電路可為資料驅動電路或掃描驅動電路。需注意的是，顯示面板20'之構成，亦可應用上述各實施例之積體電路模組20a、積體電路模組30、積體電路模組30a、積體電路模組40、積體電路模組40a或其組合，使顯示裝置2可提升積體電路與基板之間電性連接之可靠度以及產品良率，並確保顯示裝置之顯示品質。Referring to FIG. 8 , a display device 2 according to a preferred embodiment of the present invention includes a driving module 23 and a display panel 20 ′. The display panel 20' is driven to be displayed by the drive module 23. The display panel 20' has an integrated circuit 21 and a substrate 22. The structure, material, and arrangement of the integrated circuit 21 and the substrate 22 are described in detail in the integrated circuit module 20 of the first embodiment, and will not be described herein. The integrated circuit may be a data driving circuit or a scanning driving circuit. It should be noted that the integrated circuit module 20a, the integrated circuit module 30, the integrated circuit module 30a, the integrated circuit module 40, and the integrated body of the above embodiments can also be applied to the display panel 20'. The circuit module 40a or a combination thereof enables the display device 2 to improve the reliability of the electrical connection between the integrated circuit and the substrate and the product yield, and to ensure the display quality of the display device.
另外，驅動模組23包含一控制電路板B，藉由一軟性基板231與顯示面板20'電性連接以驅動顯示面板20'顯示影像。In addition, the driving module 23 includes a control circuit board B electrically connected to the display panel 20 ′ by a flexible substrate 231 to drive the display panel 20 ′ to display images.
綜上所述，依據本發明之一種顯示裝置、積體電路模組及積體電路係將接腳設置於積體電路的長邊及短邊，且該等接腳不僅藉由積體電路之線路而電性連接，更藉由基板之走線而電性連接，以致得到雙重保護。此外，當基板撓曲時，積體電路之長邊所受到的應力較小，可確保接腳與基板之連結可靠度，進而提升產品良率並確保顯示品質。此外，本發明係定義接腳使得第一組接腳之第一部分係位於第二組接腳之第一部分之間，以致基板之走線不會交錯，故走線可佈設於基板之同一層，簡化基板佈線製程。In summary, a display device, an integrated circuit module, and an integrated circuit according to the present invention have pins disposed on the long side and the short side of the integrated circuit, and the pins are not only integrated circuits The circuit is electrically connected, and is electrically connected by the wiring of the substrate, so that double protection is obtained. In addition, when the substrate is deflected, the long side of the integrated circuit is subjected to less stress, which ensures the reliability of the connection between the pin and the substrate, thereby improving product yield and ensuring display quality. In addition, the present invention defines a pin such that the first portion of the first set of pins is located between the first portions of the second set of pins, so that the traces of the substrate are not staggered, so the traces can be disposed on the same layer of the substrate. Simplify the substrate wiring process.
以上所述僅為舉例性，而非為限制性者。任何未脫離本發明之精神與範疇，而對其進行之等效修改或變更，均應包含於後附之申請專利範圍中。The above is intended to be illustrative only and not limiting. Any equivalent modifications or alterations to the spirit and scope of the invention are intended to be included in the scope of the appended claims.
10、20、20'、20a、30、30a、40、40a．．．積體電路模組10, 20, 20', 20a, 30, 30a, 40, 40a. . . Integrated circuit module
11、11'、21、21'、31、31'、41、41'．．．積體電路11, 11', 21, 21', 31, 31', 41, 41'. . . Integrated circuit
12、22、22a、32、32a、42、42a．．．基板12, 22, 22a, 32, 32a, 42, 42a. . . Substrate
2．．．顯示裝置2. . . Display device
23．．．驅動模組twenty three. . . Drive module
231．．．軟性基板231. . . Flexible substrate
A、A'．．．投影區A, A'. . . Projection area
B．．．控制電路板B. . . Control board
G1．．．第一組接腳G1. . . First set of pins
G11、G12．．．第一組接腳之第一部分G11, G12. . . The first part of the first set of pins
G13．．．第一組接腳之第二部分G13. . . The second part of the first set of pins
G14．．．第一組接腳之第三部分G14. . . The third part of the first set of pins
G2．．．第二組接腳G2. . . Second set of pins
G21、G22．．．第二組接腳之第一部分G21, G22. . . The first part of the second set of pins
G23．．．第二組接腳之第二部分G23. . . The second part of the second set of pins
G24．．．第二組接腳之第三部分G24. . . The third part of the second set of pins
G3．．．第三組接腳G3. . . Third set of pins
G31、G32．．．第三組接腳之第一部分G31, G32. . . The first part of the third set of pins
G33．．．第三組接腳之第二部分G33. . . The second part of the third set of pins
G34．．．第三組接腳之第三部分G34. . . The third part of the third set of pins
L01、L02、L03．．．走線L01, L02, L03. . . Traces
L1．．．第一組走線L1. . . First set of traces
L11．．．第一組走線之第一部分L11. . . The first part of the first set of traces
L12．．．第一組走線之第二部分L12. . . The second part of the first set of traces
L2．．．第二組走線L2. . . Second set of traces
L21．．．第二組走線之第一部分L21. . . The first part of the second set of traces
L22．．．第二組走線之第二部分L22. . . The second part of the second set of traces
L3．．．第三組走線L3. . . Third set of traces
L31．．．第三組走線之第一部分L31. . . The first part of the third set of traces
L32．．．第三組走線之第二部分L32. . . The second part of the third set of traces
M、M'．．．長邊M, M'. . . The long side
N1、N2．．．短邊N1, N2. . . Short side
P1．．．第一組連接墊P1. . . First set of connection pads
P11、P12．．．第一組連接墊之第一部分P11, P12. . . The first part of the first set of connection pads
P13．．．第一組連接墊之第二部分P13. . . The second part of the first set of connection pads
P14．．．第一組連接墊之第三部分P14. . . The third part of the first set of connection pads
P2．．．第二組連接墊P2. . . Second set of connection pads
P21、P22．．．第二組連接墊之第一部分P21, P22. . . The first part of the second set of connection pads
P23．．．第二組連接墊之第二部分P23. . . The second part of the second set of connection pads
P24．．．第二組連接墊之第三部分P24. . . The third part of the second set of connection pads
P3．．．第三組連接墊P3. . . Third set of connection pads
P31、P32．．．第三組連接墊之第一部分P31, P32. . . The first part of the third set of connection pads
P33．．．第三組連接墊之第二部分P33. . . The second part of the third set of connection pads
P34．．．第三組連接墊之第三部分P34. . . The third part of the third set of connection pads
S、S'．．．表面S, S'. . . surface
圖1為習知之一種積體電路模組的示意圖；1 is a schematic view of a conventional integrated circuit module;
圖2為依據本發明第一實施例之一種積體電路模組的示意圖；2 is a schematic diagram of an integrated circuit module according to a first embodiment of the present invention;
圖3為依據本發明第一實施例之另一種積體電路模組的示意圖；3 is a schematic diagram of another integrated circuit module according to a first embodiment of the present invention;
圖4為依據本發明第二實施例之一種積體電路模組的示意圖；4 is a schematic diagram of an integrated circuit module according to a second embodiment of the present invention;
圖5為依據本發明第二實施例之另一種積體電路模組的示意圖；FIG. 5 is a schematic diagram of another integrated circuit module according to a second embodiment of the present invention; FIG.
圖6為依據本發明第三實施例之一種積體電路模組的示意圖；6 is a schematic diagram of an integrated circuit module according to a third embodiment of the present invention;
圖7為依據本發明第三實施例之另一種積體電路模組的示意圖；以及7 is a schematic diagram of another integrated circuit module according to a third embodiment of the present invention;
圖8為依據本發明較佳實施例之一種顯示裝置的示意圖。FIG. 8 is a schematic diagram of a display device in accordance with a preferred embodiment of the present invention.
20．．．積體電路模組20. . . Integrated circuit module
21、21'．．．積體電路21, 21'. . . Integrated circuit
22．．．基板twenty two. . . Substrate
A、A'．．．投影區A, A'. . . Projection area
G1．．．第一組接腳G1. . . First set of pins
G11、G12．．．第一組接腳之第一部分G11, G12. . . The first part of the first set of pins
G2．．．第二組接腳G2. . . Second set of pins
G21、G22．．．第二組接腳之第一部分G21, G22. . . The first part of the second set of pins
G3．．．第三組接腳G3. . . Third set of pins
G31、G32．．．第三組接腳之第一部分G31, G32. . . The first part of the third set of pins
L1．．．第一組走線L1. . . First set of traces
L12．．．第一組走線之第二部分L12. . . The second part of the first set of traces
L2．．．第二組走線L2. . . Second set of traces
L21．．．第二組走線之第一部分L21. . . The first part of the second set of traces
L22．．．第二組走線之第二部分L22. . . The second part of the second set of traces
L3．．．第三組走線L3. . . Third set of traces
L31．．．第三組走線之第一部分L31. . . The first part of the third set of traces
L32．．．第三組走線之第二部分L32. . . The second part of the third set of traces
M、M'．．．長邊M, M'. . . The long side
N1、N2．．．短邊N1, N2. . . Short side
P1．．．第一組連接墊P1. . . First set of connection pads
P11、P12．．．第一組連接墊之第一部分P11, P12. . . The first part of the first set of connection pads
P2．．．第二組連接墊P2. . . Second set of connection pads
P21、P22．．．第二組連接墊之第一部分P21, P22. . . The first part of the second set of connection pads
P3．．．第三組連接墊P3. . . Third set of connection pads
P31、P32．．．第三組連接墊之第一部分P31, P32. . . The first part of the third set of connection pads
S、S'．．．表面S, S'. . . surface
Claims (32)
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