TWI445012B - Memory circuit - Google Patents

Description

Memory circuit Cross-reference to related applications

This application is related to U.S. Patent Application Serial No. 11/396,114 , entitled "Multi-Write Memory Circuit with Multiple Data Inputs" by R. Masleid et al., 2006/03/31 . The multiple-input memory circuit of the multiple data input, the agent's case number TRAN-P491, is assigned to the assignee of the present invention, and the full text of them is incorporated into this specification by reference.

Field of invention

The embodiments described in this specification relate to electronic circuits, particularly memory circuits. This written document reveals at least some of the multiple write memory circuits with one data input and one clock input.

Background of the invention

In general, a memory circuit is a type of circuit whose output depends on both the input to the circuit and the previous state of the circuit (the state before the input). A state storage feedback loop contained in a memory circuit that allows a previous input, together with a current input, to affect the current output. It would be advantageous to have a memory circuit that shortens the time required to ensure a new state in the feedback loop described above.

Summary of invention

The embodiments described in this specification are related to different types of memory Road related. In one embodiment, a memory circuit has a state storage feedback loop coupled to a clock input and a data input. The data input is introduced into the feedback loop at multiple points of focus, and is propagated in parallel from the points to other points within the feedback loop.

Broadly speaking, this written document is disclosed below. Various types of memory circuits are illustrated. A memory circuit may contain a state storage feedback loop coupled to a clock input and a data input. The data input is introduced into the feedback loop at multiple points of focus, and is propagated in parallel from the points to other points within the feedback loop.

Simple illustration

BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, which are incorporated in FIG Drawings referenced in this description are not to be construed as being drawn to scale unless otherwise specified.

1 and 2 illustrate an embodiment of a memory circuit in accordance with the present invention having a data input and a clock input, and having a reduced minimum holding voltage; FIGS. 3 and 4 illustrate a third embodiment in accordance with the present invention. Embodiments of the state inverter; Figures 5, 6, 7, and 8 illustrate an embodiment of a multiple write memory circuit in accordance with the present invention having a data input and a clock input, and having a reduced Minimum holding voltage; Figures 9 and 10 illustrate an embodiment of a memory circuit in accordance with the present invention having first and second data inputs and having a reduced minimum holding voltage; 11, 12, 13, 14 15, and 16 are diagrams illustrating an embodiment of a multiple write memory circuit in accordance with the present invention having first and second data inputs and having a reduced minimum holding voltage; FIG. 17 is a diagram in accordance with the present invention A flowchart of a method for writing a state to a memory circuit having a data input and a clock input and having a reduced minimum hold voltage; and Figure 18 Department of one embodiment for writing a state having a first and a second input and having minimum data flowchart of a method of reducing the memory circuit in accordance with one of the holding voltage of the present invention.

Detailed description of the preferred embodiment

Various embodiments of the invention are discussed in detail, and examples thereof are illustrated in the accompanying drawings. While the invention has been described with respect to the embodiments, it is understood that the invention is not intended to limit the invention. Rather, the invention is intended to cover alternatives, modifications, and equivalents, and may be included within the spirit and scope of the invention as defined by the appended claims. In addition, in the following detailed description of the invention, the invention However, it will be understood by one of ordinary skill in the art that the present invention may not require such specific details. In other instances, some of the methods, procedures, components, and circuits have not been described in detail so as not to unnecessarily obscure the features of the present invention.

Some memory circuits in accordance with the present invention may be implemented as logic latches or flip-flops. In general, the memory circuit described in this specification is a device that can store one bit.

Reduced Vmin circuit with one data input and one clock input

1 is a schematic diagram of a memory circuit 10 in accordance with an embodiment of the present invention having a data input D, a control input (eg, clock input clk), and an output Q-bar. In contrast to a conventional memory circuit, the state of the circuit 10 described above stores the feedback loop 14 and includes some additional components; these additional components may collectively be referred to as a redundant component. In particular, the feedback loop 14 includes inverters 16 and 17 in addition to the inverter 15 and the tri-state inverter 18. These inverters 16 and 17 can affect the statistical and electrical behavior of the above-described circuits, and in particular statistically reduce the minimum holding voltage (Vmin) of the above-described circuit 10, wherein Vmin is a memory such as a circuit 10 The body circuit can successfully maintain the minimum voltage at which the state is located. Reducing Vmin can also reduce the standby voltage and, as a result, reduce the standby leakage current and standby voltage. Furthermore, lowering Vmin may reduce the sensitivity of the above described circuit 10, which may cause transistor mismatch during manufacturing. Moreover, the circuit 10 advantageously has a larger static noise margin (SNM) than a conventional memory circuit.

2 is a schematic diagram of a memory circuit 20 in accordance with another embodiment of the present invention having a data input D, a clock input clk, and an output terminal Q-bar. In contrast to the feedback loop 14 of Figure 1, the state of the circuit 20 stores the feedback loop 27, which includes additional components. In other words, in addition to the inverter 21 and the tristate inverter 26, the feedback loop 27 includes inverters 21, 22, 23, and 24. The lengthening of the feedback loop 27 described above relative to the feedback loop 14 enhances the advantages mentioned above.

Figure 3 is a schematic illustration of an embodiment of a three state inverter 30 in accordance with the present invention. Such a tri-state inverter 30 includes multiple p-type devices and multiple n-type devices (transistors). The p-type devices are configured to boost the output (moderately), and the n-type device configurations depressurize the output. As a result, the driving ability of the tri-state inverter 30 is lower than that of a conventional inverter.

In the example of FIG. 3, the tri-state inverter 30 includes two p-type devices 32 and 33 and two n-type devices 34 and 35. The gates of the devices 32 and 35 are coupled to the input. The gate of device 33 described above is coupled to the input. The gate of device 33 is coupled to an output of an inverter 31 which receives an enable signal and the gate of device 34 and is coupled to the enable input. In the example of Figure 3, when the enable signal is at a high logic level, its output is driven.

Figure 4 is a schematic illustration of a tri-state inverter 40 in accordance with another embodiment of the present invention. In the example of Figure 4, the tri-state inverter 40 includes two p-type devices 42 and 43 and two n-type devices 44 and 45. The gates of the devices 42 and 45 are coupled to the input. The gate of device 44 is coupled to an output of an inverter 41 which receives a de-energized signal and the gate of device 43 and is coupled to the de-energized input. In the example of Figure 4, when the dissolvable signal is at a low logic level, its output is driven.

Multiple write reduced Vmin circuit with one data input and one clock input

Figure 5 is a schematic diagram of a multiple write memory circuit 50 having a data input D, a clock input clk, and an output Q-bar. The state of the circuit 50 stores the feedback loop 51, which includes an inverter 52 coupled in series, a tristate inverter 53, an inverter 54, and a tristate inverter 55. The inverters 54 and the three-state inverters 55 constitute a redundant component that reduces the minimum holding voltage of the circuit 50 described above. This circuit 50 may be referred to as a multiple write quad Vmin logic latch.

The tristate inverters 53 and 55, each having a clock input, in the embodiment of Fig. 5, provide a dissolving signal to the tristate inverters 53 and 55. The data input of the tristate inverter 53 is coupled to the output of the inverter 52, and the data input of the tristate inverter 55 is coupled to the output of the inverter 54. The three-state inverters 53 and 55 buffer the states received from the inverters 52 and 54 respectively according to the state of a clock signal.

In one embodiment, a tri-state inverter 56 is coupled between the data input D and the inverter 54, and a tri-state inverter 57 coupled to the data input D and inverted. Between the 52. The three-state inverters 56 and 57 each have a clock input which, in the embodiment of Fig. 5, provides an enable signal to the three-state inverters 56 and 57.

Importantly, in accordance with the current embodiment of the present invention, the data input signal D is sensed in parallel by the inverters 52 and inverters 54. That is, in accordance with the current embodiment of the present invention, the data input D is written at a plurality of points marked A and B, rather than at only one point, enabling parallel writing (or driving or loading). This feedback loop 51 is inside. The update of the remainder of the feedback loop 51 described above proceeds in parallel from each of points A and B.

The feedback loop 14 of the above circuit 10 (Fig. 1) is similar to the feedback loop 51 of Fig. 5. However, contrary to circuit 50, the data is only at one point, so that the time required to write to feedback loop 14 of circuit 10 described above, and thus the update feedback loop 14, is essentially an input signal wraparound. The time it takes to pass the loop 14 to propagate. The feedback loop 14 described above is updated in four reversals, and the feedback loop 51 is updated in two reversals. As a result, the time to update the feedback loop 51 is approximately the time required to update the feedback loop 14; it should be recognized that due to the increased parasitic lateral load, in a longer feedback loop, it is possible Some speed will be lost.

In general, in accordance with an embodiment of the present invention, a state-return feedback loop that reduces the Vmin-type memory circuit can be updated in less time. Thus, in accordance with an embodiment of the present invention, the time required to ensure a new state within the memory circuit (e.g., hold time, build time, or some other measure) is reduced, thereby relying on this point To improve the performance of these reduced Vmin memory circuits.

Figures 6, 7, and 8 are schematic views of other embodiments of a multi-write memory circuit in accordance with the present invention having a data input and a clock input, and having a reduced minimum hold voltage. In Fig. 6, a state of the memory circuit 60 stores the feedback loop 61, which includes a series coupled inverter 62, a tristate inverter 63, an inverter 64, a tristate inverter 65, and a counter. A phaser 66, and a tri-state inverter 67. These inverters 64, tristate inverters 65, inverters 66, and tristate inverters 67 form a redundant component that reduces the minimum holding voltage of the circuit 60. This circuit 60 may be referred to as a multiple write six-link Vmin logic latch.

The three-state inverters 63, 65, and 67 each have a clock input which, in the embodiment of Fig. 6, provides a dissolvable signal to the three-state inverters 63, 65, and 67. The data input of the tristate inverter 63 is coupled to the output of the inverter 62. The data input of the tristate inverter 65 is coupled to the output of the inverter 64, and the three-state inversion. The data input of the device 67 is coupled to the output of the inverter 66 described above. The inverters 62, 64, and 66 buffer the states received from the three-state inverters 63, 65, and 67, respectively, depending on the state of a clock signal.

In one embodiment, a tri-state inverter 68 is coupled between the data input D and the inverter 64, and a tri-state inverter 69 is coupled to the data input D and the inverter. Between 62, and a tri-state inverter 601 are coupled between the data input D and the inverter 66. The three-state inverters 68, 69, and 601 each have a clock input. In the embodiment of FIG. 6, an enable signal can be provided to the three-state inverters 68, 69, And 601.

In accordance with the current embodiment of the present invention, the data input D is written in parallel to the feedback loop 61 at points that are labeled A, B, and C, rather than at only one point. The update of the remainder of the feedback loop 61 described above proceeds in parallel from the focus of each of points A, B, and C. Therefore, similar to the circuit 51 in Fig. 5, the feedback loop 61 is updated in two inversions, even though the feedback loop 61 has an extended length relative to the feedback loop 51.

In FIG. 7, a state of the memory circuit 80 stores a feedback loop 81, which includes a series coupled inverter 82, a tristate inverter 83, an inverter 84, and a tristate inverter 85. An inverter 86, and a tri-state inverter 87. The inverter 84, the tristate inverter 85, the inverter 86, and the tristate inverter 87 constitute a redundant element that reduces the minimum holding voltage of the circuit 80 described above. This circuit 80 may be referred to as a multiple write series six-connected Vmin logic latch.

The three-state inverters 83, 85, and 87 each have a clock input. In the embodiment of FIG. 7, a de-energizing signal can be provided to the three-state inverters 83, 85, And 87. The data input of the tristate inverter 83 is coupled to the output of the inverter 82. The data input of the tristate inverter 85 is coupled to the output of the inverter 84, and the three-state inversion. The data input of the device 87 is coupled to the output of the inverter 86 described above. The inverters 82, 84, and 86 buffer the states received from the three-state inverters 83, 85, and 87, respectively, depending on the state of a clock signal.

In one embodiment, a tri-state inverter 88 is coupled between the data input D and the inverter 84. A tri-state inverter 89 is coupled to the data input D and the inverter. Between 82, and a tri-state inverter 801 are coupled between the data input D and the inverter 86. The three-state inverters 88, 89, and 801 each have a clock input. In the embodiment of FIG. 7, an enable signal can be provided to the three-state inverters 88, 89, And 801.

In accordance with the current embodiment of the present invention, the data input D is written in parallel to the feedback loop 81 at points that are labeled A, B, and C, rather than at only one point. The update of the remainder of the feedback loop 81 described above proceeds in parallel from the focus of each of points A, B, and C. Thus, as in the above example, the feedback loop 81 is updated in two inversions, even though the feedback loop 81 has an extended length relative to some of these examples.

In Fig. 8, a state of the memory circuit 100 stores the feedback loop 101, which includes a series coupled inverter 102, a tristate inverter 103, an inverter 104, and a tristate inverter 105. . The inverters 104 and the tri-state inverters 105 constitute a redundant component that reduces the minimum holding voltage of the circuit 100 described above. This circuit 100 may be referred to as a multiple write series inverting Vmin logic latch.

The tristate inverters 103 and 105 each have a clock input which, in the embodiment of Fig. 8, provides a dissolving signal to the tristate inverters 103 and 105. The data input of the tristate inverter 103 is coupled to the output of the inverter 102, and the data input of the tristate inverter 105 is coupled to the output of the inverter 104. The three-state inverters 103 and 105 buffer the states received from the three-state inverters 102 and 104, respectively, according to the state of a clock signal.

In one embodiment, a tri-state inverter 106 is coupled between the data input D and the inverter 102, and a tri-state inverter 107 coupled to the data input D and inverted. Between the devices 104. The three-state inverters 106 and 107, each having a clock input, in the embodiment of Figure 8, provide an enable signal to the three-state inverters 106 and 107.

In accordance with the current embodiment of the present invention, the data input D is written in parallel to the feedback loop 101 at points that are labeled A and B, rather than at only one point. The update of the remainder of the feedback loop 101 described above proceeds in parallel from each of the write points A and B. Therefore, similar to the above example, the feedback loop 101 is updated in two reversals.

Some embodiments in accordance with the present invention are not limited to the examples illustrated above by Figures 5-8. In general, in accordance with embodiments of the present invention, a data input can be directed into a multi-point of focus storage loop. Therefore, a feedback loop of any length can be updated in as few as two inversions depending on the number of such write points.

In one embodiment, the feedback loop includes an even number of circuit elements coupled in series (eg, an inverter and a tri-state inverter). In one such embodiment, the feedback loop includes an equal number of alternating series coupled inverters and tristate inverters. Using the circuit 50 of FIG. 5 as an example, the feedback loop 51 includes, in order, an inverter 52, a tristate inverter 53, an inverter 54, and a tristate inverter 55. The data input is introduced into the feedback loop 51 at the inputs of the inverters 52 and 54. The inverters 52 and 54 are alternately arranged in the feedback loop 51 with the three-state inverters 53 and 55, and the three-state inverters 53 and 55 can be based on a clock signal elk. The buffer stores the states output by the inverters 52 and 54.

From another point of view, this state stores the feedback loop and can be considered to have many stages. Wherein, in one embodiment, each stage includes a first component (eg, an inverter) and a second component (eg, a tri-state inverter) coupled in series. In one such embodiment, each stage has a clock input and a data input, wherein the status on the data input is written in parallel for each stage.

The multiple write reduction Vmin circuit of Figures 5-8 can be used in conjunction with the reduced Vmin circuit of Figures 1-2. Since a multiple write Vmin circuit may have a larger data and clock input capacitance than a reduced Vmin circuit, and thus may cause a slight increase in power dissipation within the feedback loop, then at an important path (speed) In related), it may be appropriate to use a multiple write to reduce the Vmin type circuit and a non-critical path (to save power) using a reduced Vmin type circuit.

Reduced Vmin circuit with first and second data inputs

Figure 9 is a schematic diagram of a memory circuit 110 having a first data input inversion setting (SET-BAR) and a second data input inversion reset (RESET-BAR) in accordance with an embodiment of the present invention. , a first output Q, and a second output Q-bar. The state of the circuit 110 stores the feedback loop 111 as compared to a conventional memory circuit, which includes additional components (which may collectively be referred to as a redundant component). In particular, in addition to NAND (reverse) logic gates 112 and 113, the feedback loop 111 includes inverters 114 and 115. The inverters 114 and 115 affect the statistical and electrical behavior of the above-described circuits and, in particular, statistically reduce the Vmin of the above-described circuit 110. As mentioned earlier in this specification, lowering Vmin can also reduce the standby voltage and, as a result, reduce standby leakage current and standby voltage. Moreover, lowering Vmin may reduce the sensitivity of the above described circuit 110 to transistor mismatch that may occur during fabrication. Moreover, the circuit 110 advantageously has a larger SNM than a conventional memory circuit.

Figure 10 is a schematic diagram of a memory circuit 120 in accordance with another embodiment of the present invention having a first data input setting (SET), a second data input reset (RESET), and a first output Q. And a second output Q-bar. In contrast to the feedback loop 111 of Figure 9, the state of the circuit 120 is fed back to the circuit 121 and includes additional components. In particular, in addition to NAND (reverse) logic gates 122 and 123, the feedback loop 121 includes inverters 124, 125, 126, and 126. The lengthening of the feedback loop 121 described above relative to the feedback loop 111 enhances the advantages mentioned above.

Multiple write reduction Vmin circuit with first and second data inputs

Figure 11 is a schematic diagram of a multiple write memory circuit 130 having a first data input inversion setting (SET-bar) and a second data input inversion reset in accordance with another embodiment of the present invention. (RESET-bar), a first output Q, and a second output Q-bar. This circuit 130 may be referred to as a multiple write reduction Vmin setting-reset logic latch.

The state of the circuit 130 stores the feedback loop 131 and includes a number of NAND (reverse) logic gates 132, 133, 134, and 135 coupled in series. The NAND (reverse) logic gates 134 and 135 form a redundant component that reduces the minimum holding voltage of the circuit 130 described above.

In particular, in accordance with the current embodiment of the present invention, the data input signal (SET-bar is sensed in parallel by NAND (reverse) logic gate 133 and NAND (reverse) logic gate 135, and the data input Signal RESET-bar (inverted reset) is sensed in parallel by NAND (reverse) logic gate 132 and NAND (reverse) logic gate 134. That is, in accordance with the current embodiment of the present invention, the SET- The bar (inverted set) signal is written at multiple points marked A and B, not just at one point, written in parallel to the feedback loop 131, and the RESET-bar (inverted reset) The signal, in the multiple points marked C and D, rather than at only one point, is written in parallel to the feedback loop 131. The signal is from each of the write points A, B, C, and At D, it proceeds in parallel through the feedback loop 131.

Therefore, the time required to update the feedback loop 131 is less than the time required to propagate around a conventional feedback loop (i.e., a feedback loop having only a single write point). The feedback loop 131 is updated in two reversals; if there is only one single write point, the feedback loop is updated and four reversals will occur.

In general, in accordance with an embodiment of the present invention, a state-return feedback loop of a reduced Vmin-type memory circuit is updated less than the time spent propagating around the feedback loop. Thus, in accordance with an embodiment of the present invention, the time required to ensure a new state within the memory circuit (e.g., hold time, build time, or some other measure) is reduced, thereby promoting These reduce the performance of the Vmin-type memory circuit.

Figures 12, 13, 14, 15, and 16 are schematic illustrations of other embodiments of a multiple write memory circuit in accordance with the present invention having first and second data inputs and having a reduced minimum hold voltage. In Fig. 12, the state of the circuit 140 stores the feedback loop 141, which includes an inverter 142 coupled in series, an OR containing an OR (or) logic gate 143 and a NAND (reverse) logic gate 144. An AND inverter (OAI) stage, an inverter 145, and another OAI stage containing an OR (or) logic gate 146 and a NAND (reverse) logic gate 147. The inverters 145, logic or gates 146 and NAND (reverse) logic gates 147 form a redundant component that reduces the minimum holding voltage of the circuitry 140 described above. This circuit 140 may be referred to as a quad-reverse OAI multiple write Vmin set-reset logic latch.

According to the current embodiment of the present invention, the data input signal SET-bar (inverted setting) is sensed in parallel by both the NAND (reverse) logic gate 144 and the NAND (reverse) logic gate 147, and The data input signal RESET is sensed in parallel by both the OR logic gate 143 and the OR logic gate 146. That is, in accordance with the current embodiment of the present invention, the SET-bar (inverted setting) signal is written at multiple points in the points A and B, rather than at one point, so that the writes are fed back in parallel. The loop 141, and the RESET signal, are written in the feedback loop 141 in parallel, at the point of being marked C and D, rather than at only one point. The signal is passed through the feedback loop 141 in parallel from each of the write points A, B, C, and D. Therefore, the feedback loop 141 is updated in two inversions even though redundant elements are present.

In Fig. 13, the state of the circuit 150 stores the feedback loop 151, which includes an inverter 152 coupled in series, an AND with an AND gate 153 and a NOR logic gate 154. An OR inverter stage (AOI) stage, an inverter 155, and another AOI stage segment containing an AND logic gate 156 and a NOR logic gate 157. The inverters 155, AND logic gates 156 and NOR logic gates 157 form a redundant component that reduces the minimum holding voltage of the circuit 150 described above. This circuit 150 may be referred to as a quad-reverse AOI multiple write Vmin set-reset logic latch.

According to the current embodiment of the present invention, the data input signal SET-bar (inverted setting) is sensed in parallel by both the AND logic gate 153 and the AND logic gate 156, and the data input Signal RESET is sensed in parallel by both NOR (reverse) logic gate 154 and NOR (reverse) logic gate 157. That is, in accordance with the current embodiment of the present invention, the SET-bar (inverted setting) signal is written at multiple points in the points A and B, rather than at one point, so that the writes are fed back in parallel. The loop 151, and the RESET signal, are written in the feedback loop 151 in parallel, at the point indicated by C and D, rather than at only one point. The signal is passed through the feedback loop 151 in parallel from each of the write points A, B, C, and D. Therefore, the feedback loop 151 is updated in two inversions even though redundant elements exist.

In Fig. 14, the state of the circuit 160 stores the feedback loop 161, which includes NAND (reverse) logic gates 162, 163, 164, 165, 166, and 167 coupled in series. The NAND (reverse) logic gates 164, 165, 166, and 167 constitute a redundant component that reduces the minimum holding voltage of the circuit 160 described above. This circuit 160 may be referred to as a six-join NAND (reverse) multiple write Vmin set-reset logic latch.

According to the current embodiment of the present invention, the data input signal SET-bar (inverted setting) is sensed in parallel by NAND (reverse) logic gates 163, 165, and 167, and the data input signal RESET-bar (Inverted reset) is sensed in parallel by NAND (reverse) logic gates 162, 164, and 166. That is, in accordance with the current embodiment of the present invention, the SET-bar (inverted setting) signal is written in parallel at multiple points marked A, B, and C, rather than at only one point. Into the feedback loop 161, and the RESET-bar (inverted reset) signal, at the multiple points marked as D, E, and F, rather than at only one point, writes back in parallel In the loop 161. The signal is advanced through the feedback loop 161 in parallel from each of the write points A, B, C, D, E, and F. Therefore, the feedback loop 161 is updated in two inversions even though redundant elements exist.

In Fig. 15, the state of the circuit 170 stores the feedback loop 171, which includes an inverter 172 coupled in series, an OAI stage including an OR (or) logic gate 173 and a NAND (reverse) logic gate 174. A segment, an inverter 175, an OAI stage including an OR (or) logic gate 176 and a NAND (reverse) logic gate 177, an inverter 178, and an internal OR gate 179 and NAND (reverse) logic gate 1701 OAI stage. The inverters 175 and 178, the OR logic gates 176 and 179, and the NAND logic gates 177 and 1701 constitute a redundant component that reduces the minimum holding voltage of the circuit 170 described above. This circuit 170 may be referred to as a six-inverted OAI multiple write Vmin set-reset logic latch.

According to the current embodiment of the present invention, the data input signal SET-bar (inverted setting) is sensed in parallel by NAND (reverse) logic gates 174, 177, and 1701, and the data input signal RESET (heavy) It is sensed in parallel by OR logic gates 173, 176, and 179. That is, in accordance with the current embodiment of the present invention, the SET-bar (inverted setting) signal is written in parallel at multiple points marked A, B, and C, rather than at only one point. Into the feedback loop 171, and the RESET signal is written in the feedback loop 171 in parallel at multiple points marked D, E, and F, rather than at only one point. . The signal is passed through the feedback loop 171 in parallel from each of the write points A, B, C, D, E, and F. Therefore, the feedback loop 171 is updated in two inversions even though redundant elements exist.

In Fig. 16, the state of the circuit 180 stores the feedback loop 181, which includes an inverter 182 coupled in series, an AOI stage including an AND gate 183 and a NOR logic gate 184. A segment, an inverter 185, an AOI stage including an AND gate 186 and a NOR logic gate 187, an inverter 188, and an AND gate 189 and NOR (reverse) logic gate 1801 AOI stage. The inverters 185 and 188, the AND logic gates 186 and 189, and the NOR logic gates 187 and 1801 form a redundant component that reduces the minimum holding voltage of the circuit 180 described above. This circuit 180 may be referred to as a six-inverted OAI multiple write Vmin set-reset logic latch.

According to the current embodiment of the present invention, the data input signal SET-bar (inverted setting) is sensed in parallel by NAND (reverse) logic gates 183, 186, and 189, and the data input signal RESET (heavy) Set), sensed in parallel by NOR (reverse OR) logic gates 184, 187, and 1801. That is, in accordance with the current embodiment of the present invention, the SET-bar (inverted setting) signal is written in parallel at multiple points marked A, B, and C, rather than at only one point. Into the feedback loop 181, and the RESET signal is written in the feedback loop 181 in parallel at multiple points marked D, E, and F, rather than at only one point. . The signal is passed through the feedback loop 181 in parallel from each of the write points A, B, C, D, E, and F. Therefore, the feedback loop 181 is updated in two inversions even though redundant elements are present.

They are not limited by the examples illustrated in Figures 11-16 in accordance with embodiments of the present invention. In general, in accordance with an embodiment of the present invention, the first and second data are entered into a multi-focus on a state storage feedback loop. Therefore, a feedback loop of any length can be updated in as few as two inversions depending on the number of such write points.

In one embodiment, the feedback loop includes an even number of circuit elements (eg, logic gates) coupled in series. In one embodiment, there is a first data input that is introduced into the feedback loop at an input of an alternating circuit component (eg, an input of every other logic gate in the feedback loop). And a second data input is introduced into the feedback loop at the circuit component between the alternate circuit components.

In another aspect, the state stores a feedback loop that can be considered to have a number of stages, wherein the first data input is written in parallel for each stage, and the second data input , also written in parallel for each stage.

The multiple write reduction Vmin circuit of Figures 11-16 can be used with the reduced Vmin circuit of Figure 9-10. Since a multiple write Vmin circuit may have a larger data and clock input capacitance than a reduced Vmin circuit, and thus may cause a slight increase in power dissipation within the feedback loop, then at an important path (speed) In related), it may be appropriate to use a multiple write to reduce the Vmin type circuit and a non-critical path (to save power) using a reduced Vmin type circuit.

Method of writing a state to a memory circuit

Figure 17 is a diagram of an embodiment of the present invention for writing a state to a memory circuit having a data input and a clock input and having a reduced minimum holding voltage (e.g., circuits of Figures 5-8). Flowchart of the method 1900. Although in flowchart 1900, some specific steps are disclosed, such steps are exemplary. That is, some embodiments in accordance with the present invention are particularly suitable for performing various other steps or variations of the steps recited in flowchart 1900. It should be understood that the steps in flowchart 1900 may be performed in a different order than that presented, and the steps in flow table 1900 are not necessarily in the order illustrated.

In step 1910 of Figure 17, a clock input is received at a first set of multi-emphasis locations within a state stored in a memory circuit.

In step 1920, a data entry is received at a second set of multiple points within the feedback loop. In one embodiment, the data input is received at alternating circuit elements of the feedback loop. For example, the feedback loop may include an equal number of alternating series coupled inverters and tristate inverters. The data input is received at the input of the inverters.

In step 1930, the data entry is propagated from the second set of multiple priorities to other points within the feedback loop.

Figure 18 is a diagram of an embodiment of the present invention for writing a state to a memory circuit having first and second data inputs and having a reduced minimum holding voltage (e.g., circuits of Figures 11-16). Method flow chart 2000. Although in Flowchart 2000, some specific steps are disclosed, such steps are exemplary. That is, some embodiments in accordance with the present invention are particularly suitable for performing various other steps or variations of the steps recited in flowchart 2000. It should be understood that the steps in flowchart 2000 may be performed in a different order than that presented, and the steps in flow table 2000 are not necessarily in the order illustrated.

In step 2010 of Fig. 18, a first data input is received at a first set of multiple points in a state store feedback loop of a memory circuit.

In step 2020, a second data input is received at a second set of multiple points within the feedback loop.

In step 2030, the first and second data inputs are propagated from the first and second sets of multi-points to other points within the feedback loop.

In summary, some embodiments in accordance with the present invention may reduce the time required to ensure a new state within the memory circuit.

Some of the embodiments have been described in accordance with the present invention. While the present invention has been described in terms of specific embodiments, it is understood that the invention should not be construed as being limited to the embodiments.

10. . . Memory circuit

30. . . Tristate inverter

14. . . State storage feedback loop

31. . . inverter

15. . . inverter

32,33. . . P-type device

16,17. . . inverter

34,35. . . N-type device

18. . . Tristate inverter

40. . . Tristate inverter

20. . . Memory circuit

41. . . inverter

21,22,23,24. . . inverter

42,43. . . P-type device

26. . . Tristate inverter

44,45. . . N-type device

27. . . State storage feedback loop

50. . . Multiple write memory circuit

51. . . State storage feedback loop

86. . . inverter

52. . . inverter

87. . . Tristate inverter

53. . . Tristate inverter

88. . . Tristate inverter

54. . . inverter

89. . . Tristate inverter

55. . . Tristate inverter

801. . . Tristate inverter

56. . . Tristate inverter

100. . . Memory circuit

57. . . Tristate inverter

101. . . State storage feedback loop

60. . . Memory circuit

102. . . inverter

61. . . State storage feedback loop

103. . . Tristate inverter

62. . . inverter

104. . . inverter

63. . . Tristate inverter

105. . . Tristate inverter

64. . . inverter

106. . . Tristate inverter

65. . . Tristate inverter

107. . . Tristate inverter

66. . . inverter

110. . . Memory circuit

67. . . Tristate inverter

111. . . State storage feedback loop

68. . . Tristate inverter

112,113. . . NAND (reverse) logic gate

69. . . Tristate inverter

114,115. . . inverter

601. . . Tristate inverter

120. . . Memory circuit

80. . . Memory circuit

121. . . State feedback loop

81. . . State storage feedback loop

122,123. . . NAND (reverse) logic gate

82. . . inverter

124,125,126,126. . . inverter

83. . . Tristate inverter

130. . . Multiple write memory circuit

84. . . inverter

131. . . State storage feedback loop

85. . . Tristate inverter

132,133,134,135. . . NAND (reverse) logic gate

173. . . OR (or) logic gate

140. . . Circuit

174. . . NAND (reverse) logic gate

141. . . State storage feedback loop

175. . . inverter

142. . . inverter

176. . . OR (or) logic gate

143. . . OR (or) logic gate

177. . . NAND (reverse) logic gate

144. . . NAND (reverse) logic gate

178. . . inverter

145. . . inverter

179. . . OR (or) logic gate

146. . . OR (or) logic gate

1701. . . NAND (reverse) logic gate

147. . . NAND (reverse) logic gate

180. . . Circuit

150. . . Circuit

181. . . State storage feedback loop

151. . . State storage feedback loop

182. . . inverter

152. . . inverter

183. . . AND logic gate

153. . . AND logic gate

184. . . NOR (reverse OR) logic gate

154. . . NOR (reverse OR) logic gate

185. . . inverter

155. . . inverter

186. . . AND logic gate

156. . . AND logic gate

187. . . NOR (reverse OR) logic gate

157. . . NOR (reverse OR) logic gate

188. . . inverter

160. . . Circuit

189. . . AND logic gate

161. . . State storage feedback loop

1801. . . NOR (reverse OR) logic gate

162,163,164,165,166,167. . . NAND (reverse) logic gate

1900. . . flow chart

1910, 1920, 1930. . . step

170. . . Circuit

2000. . . flow chart

171. . . State storage feedback loop

2010, 2020, 2030. . . step

172. . . inverter

1 and 2 illustrate an embodiment of a memory circuit in accordance with the present invention having a data input and a clock input, and having a reduced minimum holding voltage; FIGS. 3 and 4 illustrate a third embodiment in accordance with the present invention. Embodiments of the state inverter; Figures 5, 6, 7, and 8 illustrate an embodiment of a multiple write memory circuit in accordance with the present invention having a data input and a clock input, and having a reduced Minimum holding voltage; Figures 9 and 10 illustrate an embodiment of a memory circuit in accordance with the present invention having first and second data inputs and having a reduced minimum holding voltage; 11, 12, 13, 14 15, and 16 are diagrams illustrating an embodiment of a multiple write memory circuit in accordance with the present invention having first and second data inputs and having a reduced minimum holding voltage; FIG. 17 is a diagram in accordance with the present invention A flowchart of a method for writing a state to a memory circuit having a data input and a clock input and having a reduced minimum hold voltage; and Figure 18 Department of one embodiment for writing a state having a first and a second input and having minimum data flowchart of a method of reducing the memory circuit in accordance with one of the holding voltage of the present invention.

14. . . State storage feedback loop

15. . . inverter

16,17. . . inverter

18. . . Tristate inverter

Claims (25)

A memory circuit includes: a state storage feedback loop having a clock input and a data input, wherein the memory circuit is configured to store a plurality of focus points of the feedback loop in the state, and simultaneously import one The same data input values are sent to the state storage feedback loop, wherein the multiple emphasis corresponds to the input of the selected plurality of circuit elements in the state storage feedback loop. The memory circuit of claim 1, wherein the state storage feedback circuit comprises an even number of circuit elements coupled in series, wherein the multiple focus corresponds to a plurality of points between each of the other circuit elements. . A memory circuit as in claim 2, wherein each circuit element between each of the other circuit elements is configured to receive the clock input. The memory circuit of claim 1, wherein the state storage feedback loop includes a plurality of inverters of the same number and a plurality of three-state inverters, wherein the inverters and the inverters The tri-state inverters are alternately coupled in series such that a first inverter drives a first tri-state inverter, and the first tri-state inverter drives a second inverter, the second inverter A second three-state inverter is driven. The memory circuit of claim 4, wherein the multiple emphasis corresponds to an input of the inverters. A memory circuit as in claim 4, wherein each of the tristate inverters is configured to receive the clock input. Such as the memory circuit of claim 4, wherein the state is stored The memory feedback loop system includes at least two inverters and at least two three-state inverters. The memory circuit of claim 1, wherein the memory circuit further comprises a plurality of tristate inverters, wherein a tristate inverter of the plurality of tristate inverters is coupled to the data input Between each and more emphasis. The memory circuit of claim 8, wherein each of the three-state inverters comprises an inverter, a first p-type device, a second p-type device, a first n-type device, and a The second n-type device. A memory circuit includes: a clock input coupled to a state storage feedback loop having a plurality of stages; a data input coupled to the level segment, wherein the memory circuit is configured such that: the data The input has an identical state, the same state is written to the level segment; and the same state entered in the data is simultaneously written to the level segment of the input of a component in a stage; and a coupling to the level segment The output, wherein a first state of the data input, and a second state after the data input and after the first state are configured to affect a state at the output. The memory circuit of claim 10, wherein the level segment is coupled in series, wherein the level segment comprises a segment having a first component and a second component coupled in series, wherein The information The input state is configured to be input to the first component, and wherein the second component is configured to receive the clock input and a state output from the first component. The memory circuit of claim 10, wherein the level segment comprises a stage having one of a series coupled inverter and a three-state inverter. A memory circuit as in claim 12, wherein the state of the data input is configured to be input to the inverter in the stage. A memory circuit as in claim 12, wherein the tristate inverter in the stage is configured to receive the clock input and a state from the inverter in the stage. The memory circuit of claim 12, wherein, in each of the stages, the tristate inverter comprises an inverter, a first p-type device, a second p-type device, A first n-type device and a second n-type device. The memory circuit of claim 10, further comprising a plurality of tristate inverters, wherein a tristate inverter of the tristate inverters is coupled to the data input and the level Between segments. A method for writing a state to a memory circuit, the method comprising the steps of: storing a clock input at a first multi-focus of the feedback loop in a state of the memory circuit; Receiving a data input at one of the second multi-focus points on the storage feedback loop, wherein the data input has an associated with it a value, and wherein an identical value of the data input is simultaneously sensed at each second multi-focus, wherein each of the second multi-focus corresponds to an input of a circuit component of the state storage feedback loop And inputting the data from the second multi-focus to other points in the state storage feedback loop. The method of claim 17, further comprising the step of: receiving the data input at a plurality of alternating circuit elements storing the feedback loop in the state. The method of claim 18, further comprising the steps of: receiving the clock input at a plurality of circuit elements between the alternating circuit elements; and receiving the alternation from the alternating circuit elements One of the states of the circuit elements between the circuit elements. The method of claim 17, wherein the state storage feedback loop system comprises a plurality of identical plurality of inverters and a plurality of three-state inverters, wherein the inverters and the three states are The inverters are alternately coupled in series such that a first inverter drives a first three-state inverter, the first three-state inverter drives a second inverter, and the second inverter drives a second inverter The second tri-state inverter. The method of claim 20, further comprising the step of: receiving the data input at an input of the inverters. The method of claim 20, further comprising the steps of: receiving a state and a clock input at the three-state inverters In. The method of claim 20, wherein the state storage feedback loop comprises at least two inverters and at least two three-state inverters. The method of claim 17, wherein the memory circuit further comprises a plurality of tristate inverters, wherein a tristate inverter of the plurality of tristate inverters is coupled A data input of the memory circuit is between each point of the second multi-focus. The method of claim 24, wherein each of the three-state inverters comprises an inverter, a first p-type device, a second p-type device, a first n-type device, and a second N type device.