TWI443779B - Semiconductor device and method for making the same - Google Patents

Description

Semiconductor component and method of manufacturing same

The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a semiconductor device having a pillar array and a metal bit line, each bit line being connected to a slanted bit line contact of a straight line, and Extending in a direction oblique to the row direction of the column array and a course direction.

A dynamic random access memory (DRAM) component is a short-lived memory component for storing data or information, comprising an array of transistors and capacitors, a plurality of sources or drains ( Drain) an electrically coupled bit line and a plurality of word lines electrically coupled to the gates of the transistors. Industrial developments in DRAM components have focused on reducing the size of DRAM wafers. One method of reducing the size of a DRAM wafer is by forming a deep trench on the germanium substrate, and the smaller the width of the trench, the smaller the size of the DRAM wafer. However, reducing the width of the trench from the current DRAM generation (with a trench width of about 60 nm) to the next DRAM generation (with a trench width of about 20-40 nm) is a big challenge.

1A and 1B illustrate a conventional 4F ² vertical cell type DRAM device comprising: a substrate 1 having a substrate 11 and a pillar 12 extending upward from the substrate 11 a column array; a plurality of buried bit lines 13 embedded in the substrate 11 are disposed under and connected to the respective straight columns 12 of the column array; a word line 14, each word line 14 is connected to an intermediate portion of the column 12 of the respective row in the column array; a filling of the columns 12, the buried bit lines 13 and the An insulating material (not shown) of the gap between the word lines 14 and a plurality of capacitors 15 respectively disposed on and electrically connected to the pillars 12.

1C through 1H illustrate successive steps of a conventional method of fabricating a 4F ² DRAM device. The method comprises: forming a bit line trench 10 on a semiconductor substrate 1 such that the substrate 1 forms a substrate 11 and an elongated strip 121 extending upward from the substrate 11 (see FIG. 1C); A liner layer 131 is formed on the opposite strip walls of the trench 10 (see FIG. 1D); an N+ dopant ion (eg, phosphorus, arsenic, and N is implanted in the bottom of each of the bit trenches 10 in the substrate 11). a type of ion), followed by analing or thermal diffusion to form a doped region 133 therein (see FIG. 1E); deepen each bit line trench 10 by dry etching to incorporate each The impurity region is cut into two separate half regions 133a and 133b to form a separate buried bit line 13 (see FIG. 1F); the spacer trench 10 is filled with a gap filling material 151 (see FIG. 1G); A plurality of word line trenches 16 are formed, and each of the word line trenches 16 is disposed on the buried bit lines 13 and intersects the buried bit lines 13 such that each of the elongated strips 121 forms a continuous row of pillars The body 12 (see FIG. 1H), the columns 12 formed from the elongated strips 121 collectively form an array of columns arranged in a row; a gate is formed on the side of each of the columns 12. a gate oxide layer (not shown); a plurality of word lines 14 are formed, each word line 14 being formed on a gate oxide layer on a side of the pillar 12 of the respective row in the column array Filling the word line trench (not shown) with an insulating material; and forming a plurality of capacitors (not shown) disposed on and electrically connected to the pillars 12.

A disadvantage of the above conventional method is that since the doped region 133 formed in the depth direction is relatively thick, the equipotential trench 10 needs to be further deepened (for example, about 200 nm) to be sufficient to cut through the doping. Area 133, this The steps are very difficult to implement in the narrow space of the bit line trench 10, and since each buried bit line 13 is made from a dopant having a relatively low conductivity and has the same high resistance, The miniaturization of DRAM components can adversely affect and hinder the integration of high density memory cells into each buried bit line 13. Further, in order to reduce the resistance of each buried bit line 13, a pick up contact or a deep position metal silicidate contact is formed on the buried bit line 13. Relatively difficult.

Accordingly, it is an object of the present invention to provide a semiconductor device and a method of fabricating the same that overcome the above-described disadvantages of the prior art.

Accordingly, the present invention provides a semiconductor device comprising: a substrate comprising a substrate and an array of pillars, the pillar array having a plurality of pillars extending upward from the substrate and arranged in a row, each of the pillar arrays The columns of the rows are arranged along the direction of the row; a plurality of buried bit lines, each of the buried bit lines extending along the straight direction, and disposed in two adjacent columns of the column array Between each of the plurality of word lines, each of the word lines extending along a course transverse to the straight direction and electrically connected to the corresponding columns of the columns in the column array; and a contact array , including a plurality of bit line line contacts arranged in rows and columns. The bit line contacts of each of the row arrays are disposed along the straight direction and are buried in the substrate and electrically connected to the respective buried bit lines. Each of the bit line contacts in each of the arrays of the contacts is interleaved with the respective buried bit lines and extends and electrically connected between two adjacent columns.

Another object of the present invention is to provide a method of fabricating a semiconductor device. The method comprises: (a) forming a plurality of twisted first trenches on a substrate And a plurality of parallel second trenches, the second trenches being staggered with the first trenches such that the substrate forms a lower branch and an array of poles, the pole array having a plurality of upwardly extending from the lower branch And a column arranged in a row, each pole in the array of rods is arranged in a twisting manner along a straight line direction; (b) filling the first groove and the first in the substrate with an insulating material a second trench; (c) forming a plurality of bit line trenches, each bit line trench extending in a straight direction through the corresponding straight column of the pole array, such that each pole forms a base and a pair of cylinders extending upward from the base and separated by a corresponding pole, the pillars formed from the pillars collectively forming an array of columns arranged in a row; (d) forming an array of contacts, The contact array has a plurality of bit line line contacts arranged in rows and columns, and each bit line contact in each of the series of rows in the contact array is embedded in a respective base formed by the poles and extends And electrically connected between two adjacent columns extending upward from the respective bases; (e) forming a plurality of In place bit line, each buried bit line is disposed in a respective bit line groove and extending along the same and electrically connected to respective straight rows in the contact array; and (f) forming a plurality of word lines Each word line extends along a course direction transverse to the straight direction and is electrically connected to a respective row of the column array.

The invention is further described in the following examples, but it should be understood that these examples are for illustrative purposes only and are not to be construed as limiting.

As shown in FIGS. 2 to 3, the semiconductor device 100 of the first preferred embodiment of the present invention can be further fabricated into a memory cell such as a 4F ² vertical cell type DRAM.

The semiconductor device 100 includes a substrate 2 including a substrate 21 and a column array having a plurality of pillars 22 extending upward from the substrate 21 and arranged in a row and column, each row of the column array The column 22 is disposed along the line direction (X); a plurality of buried bit lines 23, each of the buried bit lines 23 extending along the straight direction (X), and disposed adjacent to the line Between the straight columns 22 in the column array; a plurality of word lines 24, each word line 24 extending along a course (Y) transverse to the straight direction (X), and the column Corresponding pillars 22 in the array are electrically connected; a plurality of capacitors 26 respectively disposed on and electrically connected to the top ends of the pillars 22; and a contact array including a plurality of rows and columns of bit rows arranged Point 25. The bit line contacts 25 of each of the row arrays are disposed along the straight direction (X) and are buried in the substrate 21 and electrically connected to the respective buried bit lines 23. Each of the bit line contacts 25 in each of the arrays of the contacts is interleaved with the respective buried bit lines 23, and extends and is electrically connected between the two adjacent and beveled columns 22. That is, two adjacent pillars 22 are respectively seated between two adjacent rows and two adjacent straight rows of the pillar array, and are connected to the corresponding word line 24.

Each of the pillars 22 has a source region, a drain region and a conduction channel region (not shown).

An insulator (not shown) is filled in the gap between the pillars 12, the buried bit lines 13 and the word lines 14.

In this embodiment, each bit line contact 25 of each row in the contact array is along a length direction inclined in the straight direction (X) and the course direction (Y). (U, V) extends between two adjacent cylinders. The length direction (U) of each bit line contact 25 of each line in the contact array and an adjacent bit line contact 25 of each line in the contact array The length direction (V) crosses.

Each of the buried bit lines 23 is made of a conductive material containing a metal, a nitride of the metal, and a telluride of the metal. The metal is preferably selected from the group consisting of titanium, tungsten, nickel and cobalt.

Each of the bit line contacts 25 contains implanted ions selected from the group consisting of: arsenic, phosphorus, and N-type ions.

Preferably, the substrate 2 is a p-type or n-type germanium wafer.

Figure 4 illustrates a semiconductor device 100 in accordance with a second preferred embodiment of the present invention. The second preferred embodiment is different from the previous preferred embodiment in that the length direction of each bit line contact 25 of each line in the contact array and one of each line in the contact array Adjacent bit line contacts 25 are parallel in the longitudinal direction.

5A to 5W illustrate successive steps of a method of fabricating the semiconductor device 100 of the first preferred embodiment of the present invention. The method comprises the steps of: providing a substrate 2 (see FIG. 5A); forming a first hard mask layer 31 on the top surface of the substrate 2 (see FIG. 5A); a twisted path 301 (each path having a saw-like appearance) and subsequently etching the first hard mask layer 31 along a non-twisted path (straight path) 302 interleaved with the twisted paths 301, the first A hard mask layer 31 is double patterned (see FIG. 5A) to form a plurality of first groove portions 306 and a plurality of second groove portions 307 to collectively expose the exposed surface on the top surface of the substrate 2. Exposing (see FIG. 5B); etching the substrate 2 from an exposed area on the top surface of the substrate 2 to form a plurality of twisted first trenches 201 and a plurality of parallel second trenches 202 The second trenches 202 are interleaved with the first trenches 201 such that the substrate 2 forms a lower branch portion 203 and an array of pillars (See FIG. 5C and FIG. 5D), the pole array has a plurality of poles 205 extending upwardly from the lower branch 203 and arranged in rows and columns. Each of the poles 205 in the array of poles is along a twisted manner. a row direction (X) setting (each row of the pole array has a shape similar to a saw-like dashed line); formed on the first trench 201 and the trench walls of the second trenches 202 a first pad (not shown); the first trench 201 of the substrate 2 and the second trenches 202 are filled with an insulating material 41 (see FIG. 5E); the insulating material 41 is polished. And removing the first hard mask layer 31 (not shown); forming a second hard mask layer 32 on the insulating material 41 (see FIG. 5F); A direction (X) extending bit line path (not shown) etches the second hard mask layer 32, and the second hard mask layer 32 is patterned to form a plurality of mask trench portions 308, together An exposed portion of the insulating material 41 and an exposed portion of each of the posts 205 are exposed (see FIGS. 5G and 5H); an exposed portion from the insulating material 41 and each of the posts 205 The insulating material 41 and the pillars 205 are partially etched to form a plurality of bit line trenches 211 (see FIGS. 5H to 5J), and each of the bit line trenches 211 extends through the straight direction (X). The pole arrays of the pole arrays correspond to the straight poles 205 such that each pole 205 forms a base 206 and a pair of cylinders 22 extending upwardly from the base 206 and separated by a corresponding bit line groove 211. The columns 22 formed by the poles 205 together form an array of columns arranged in a row, each of the bit line grooves 211 has a groove wall 212 having a corresponding column 22 and a portion defined by the corresponding base portion 206; a second liner layer 42 is formed on the trench wall 212 of each of the bit line trenches 211 and etched back to expose each of the base portions 206 (see FIG. 5K); Ion implanting a dopant in each of the bases 206, followed by annealing to the dopant Thermal diffusion is performed toward two adjacent pillars 22 to form a contact array including a plurality of bit line contacts 25 arranged in rows and columns (see FIGS. 5L and 5M), each of which is in a row array Each of the wire bonds 25 is embedded in a respective base 206 and extends and electrically connected between two adjacent columns 22 extending upwardly from the respective bases 206; A metal-containing material is deposited in 211 to form a plurality of buried bit lines 23 (see FIGS. 5N and 5O), and each buried bit line 23 is disposed in a respective bit line trench 211 and along The extension is electrically connected and staggered with respective straight row line contacts 25 in the array of contacts, and each buried bit line 23 is formed on the second pad layer 42 such that the column Two adjacent pillars 22 in the array are insulated by the second liner layer 42; a gap of the spacer trenches 211 is filled with a first gap filling material 43 and then in the second hard mask layer 32. And forming a third hard mask layer 33 on the first gap filling material 43 and extending along a parallel direction (Y) parallel to the straight line direction (X) The second hard mask layer 32 and the third hard mask layer 33 are patterned by a word line path (not shown), and the second hard mask layer 32 and the third hard mask layer 33 are patterned. Forming a plurality of mask trenches (not shown) for exposing the opposite ends of each of the pillars 22 and one of the first gap-filling materials 43; from the exposed end of each pillar 22 and the first A portion of the gap filling material 43 is etched to form a plurality of word line trenches 221 (see FIGS. 5P and 5Q), and each word line trench 221 is spaced apart from the buried bit line 23 and The buried bit lines 23 are crossed, and each word line groove 221 extends along the course direction (Y) to expose the opposite sides of each of the columns 22; in each word line groove 221 A gate oxide layer 45 is formed such that the gate oxide layer 45 is formed on the side of each pillar 22 (see FIG. 5R and FIG. 5S); A conductive material is deposited in 221, and then etched back to form a plurality of conductive strips 240 (see FIGS. 5R and 5S), each conductive strip 240 extending along the course direction (Y), and each conductive strip 240 is formed on the gate oxide layer 45; an insulating oxide material 46 is deposited in each of the word line trenches 221, and then the upper portion of the oxide material 46 and each of the conductive strips 240 are removed by etching. The upper portion is such that the conductive strips 240 form a plurality of word lines 24 (see FIGS. 5T and 5U), each word line 24 being opposite to the second side of the column 22 of the respective row in the column array. Electrically connected; the word trench 221 is filled with a second gap filling material 47, and then a plurality of capacitors 26 (see FIGS. 5V and 5W) are formed. Each capacitor 26 is disposed and electrically connected to a respective pillar. On body 22. Since the formation of the capacitors 26 can be implemented in a conventional manner, it will not be described in detail herein for the sake of brevity.

Preferably, the first hard mask layer 31, the second hard mask layer 32 and the third hard mask layer 33 are made of a material selected from the group consisting of: SiN and SiO ₂ or by High-density plasma (HDP) oxide deposition or by chemical vapor deposition using tetraethyl orthosilicate (TEOS) as a precursor.

Preferably, the first liner layer and the second liner layer 42 are made of a material selected from the group consisting of: SiN and SiO ₂ , or deposited by high-density plasma oxide or by utilizing positive Tetraethyl phthalate is formed as a precursor by chemical vapor deposition.

Preferably, the insulating material 41 is selected from the group consisting of: SiN and SiO ₂ , or formed by high-density plasma oxide deposition or by chemical vapor deposition using tetraethyl orthosilicate as a precursor.

Preferably, the first gap filling material 43 and the second gap filling material 47 are selected from: SiN and SiO ₂ , or deposited by high-density plasma oxide, or by using tetraethyl ortho-ruthenate It is formed as a precursor by chemical vapor deposition or by a spin-on dielectric (SOD) process.

Preferably, the word lines 24 are made of a conductive material selected from the group consisting of: TiN, tungsten, and aluminum.

In summary, since the present invention is formed by extending and electrically connecting the bit line contacts 25 between two adjacent columns 22, each bit line contact 25 is separated from and adjacent to each other. The word lines 24 are connected, and by forming the buried bit lines 23 made of the metal-containing material, each of the buried bit lines 23 is connected to each of the respective straight lines of the contact array. 25 interlaced, thus overcoming the shortcomings encountered by the above-mentioned prior art.

The above is only the preferred embodiment and the specific examples of the present invention, and the scope of the invention is not limited thereto, that is, the simple equivalent change according to the scope of the invention and the description of the invention. And modifications are still within the scope of the invention patent.

1‧‧‧Substrate

10‧‧‧ bit line trench

11‧‧‧Base

12‧‧‧Cylinder

121‧‧‧Stretching strip

13‧‧‧ buried in the bit line

131‧‧‧ liner

133‧‧‧Doped area

14‧‧‧Word line

15‧‧‧ capacitor

151‧‧‧Gap filling material

16‧‧‧Word line trench

100‧‧‧Semiconductor components

2‧‧‧Substrate

201‧‧‧First trench

202‧‧‧Second trench

203‧‧‧ Lower branch

205‧‧‧ pole

206‧‧‧ base

21‧‧‧Base

211‧‧‧ bit line trench

212‧‧‧Ditch wall

22‧‧‧Cylinder

221‧‧‧ word line trench

23‧‧‧ buried in the bit line

24‧‧‧ word line

240‧‧‧ Conductive tape

25‧‧‧ bit line contacts

26‧‧‧ Capacitors

301‧‧‧distorted path

302‧‧‧ Non-distorted path

306‧‧‧First groove

307‧‧‧Second trough

308‧‧‧Mask groove

31‧‧‧First hard mask layer

32‧‧‧Second hard mask layer

33‧‧‧ Third hard mask layer

41‧‧‧Insulation materials

42‧‧‧Second lining

43‧‧‧First gap filling material

45‧‧‧ gate oxide layer

46‧‧‧Oxide materials

47‧‧‧Second gap filling material

X‧‧‧Direct direction

Y‧‧‧ direction

U‧‧‧ Length direction

V‧‧‧ length direction

1A-1H are schematic views showing a continuous step of a conventional method of fabricating a semiconductor device; and Fig. 2 is a perspective perspective view showing the structure of a semiconductor device according to a first preferred embodiment of the present invention; and Fig. 3 is a top plan view. The structure of the first preferred embodiment; FIG. 4 is a top plan view showing the structure of a semiconductor device according to a second preferred embodiment of the present invention; and 5A-5W are schematic views showing successive steps of a method of fabricating the semiconductor device of the first preferred embodiment of the present invention.

100‧‧‧Semiconductor components

2‧‧‧Substrate

21‧‧‧Base

22‧‧‧Cylinder

23‧‧‧ buried in the bit line

24‧‧‧ word line

25‧‧‧ bit line contacts

26‧‧‧ Capacitors

X‧‧‧Direct direction

Y‧‧‧ direction

Claims (12)

A semiconductor component comprising: a substrate comprising a substrate and an array of pillars, the pillar array having a plurality of pillars extending upwardly from the substrate and arranged in a row, the column of each row in the array of pillars is a plurality of buried bit lines extending along the straight direction and disposed between two adjacent columns in the array of the columns; a word line, each word line extending along a course transverse to the straight direction and electrically connected to a corresponding column of the column in the column array; and a contact array comprising a plurality of rows and columns Arranging bit line contacts, each bit line contact in the array of contacts is disposed along the straight direction, and is buried in the substrate and electrically connected to the respective buried bit line Each of the bit line contacts in each of the arrays of the contacts is interleaved with the respective buried bit lines and extends and electrically connected between two adjacent columns. The semiconductor device according to claim 1, further comprising a plurality of capacitors disposed on and electrically connected to the pillars. The semiconductor device according to claim 1, wherein each of the bit line contacts in each of the contact arrays extends along a length direction between two adjacent columns, the connection The length direction of each bit line contact of each row in the dot array intersects with the length direction of an adjacent bit line contact of each of the consecutive rows in the array of contacts. The semiconductor device according to claim 1, wherein each of the bit line contacts in each of the contact arrays extends along a length direction between two adjacent columns, the connection The length direction of each bit line contact in each row of the dot array is adjacent to each of the consecutive rows in the contact array The length direction of the bit line contacts is parallel. The semiconductor device according to claim 1, wherein each of the buried bit lines is made of a conductive material containing a metal telluride selected from the group consisting of: Titanium, tungsten, nickel and cobalt. The semiconductor device of claim 1, wherein each of the bit line contacts comprises implanted ions selected from the group consisting of: arsenic, phosphorus, and N-type ions. The semiconductor device according to claim 1, wherein the substrate is a p-type or n-type germanium wafer. A method of fabricating a semiconductor device, comprising: (a) forming a plurality of twisted first trenches and a plurality of parallel second trenches on a substrate, the second trenches being interleaved with the first trenches So that the substrate forms a lower branch and an array of poles, the pole array having a plurality of poles extending upwardly from the lower branch and arranged in a row, the poles of each row in the array of poles being twisted (b) filling the first trench and the second trench in the substrate with an insulating material; (c) forming a plurality of bit line trenches, each bit line trench is a straight direction extending through the corresponding straight rows of the pole arrays such that each pole forms a base and a pair of cylinders extending upwardly from the base and separated by a corresponding bit line groove, The pillars formed by the poles collectively form an array of pillars arranged in a row; (d) forming a grid of contacts having a plurality of row-line contacts arranged in rows and columns, each of the arrays of the arrays Every bit line that has been going The contacts are embedded in a respective base formed by the poles and extend and electrically connected between two adjacent cylinders extending upward from the respective bases; (e) forming a plurality of buried positions a line, each buried bit line is disposed in a respective bit line trench and extending along the line and electrically connected to respective straight rows in the array of contacts; and (f) forming a plurality of word lines, each A word line extends in a course direction transverse to the straight direction and is electrically connected to respective courses in the column array. According to the method of claim 8, further comprising the following steps performed between the steps (c) and (d): forming a liner layer of an insulating material on each of the pillars so as to be formed in the step ( Each of the buried bit lines in e) is insulated by two adjacent straight rows of the column array. According to the method of claim 8, further comprising the following steps performed between the steps (e) and (f): filling the equipotential trench with a gap filling material to form a plurality of word line trenches, Each word line trench is disposed on the buried bit line and intersects the buried bit line, and each word line groove extends along the course direction such that the opposite of each column The side is exposed, and a gate oxide layer is formed in each word line trench, so that the gate oxide layer is formed on the side of each pillar, so that each word line formed in step (f) is formed. On the gate oxide layer. The method of claim 8, wherein the array of contacts formed in step (d) is achieved by ion implantation and subsequent thermal diffusion. The method of claim 8, wherein the substrate is a p Type 矽 wafer or an n-type 矽 wafer.