TWI442567B - Charged balanced devices with shielded gate trench - Google Patents

Description

Charge balancing device with a masked gate channel

The present invention relates to a vertical semiconductor power device, and more particularly to a single thin epitaxial layer, which is realized by advanced manufacturing, and can be used for preparing various sizes of vertical power with a super junction structure and a charge balance of a gate channel. The device is suitable for different breakdown voltages through a simple and flexible manufacturing process.

Conventional manufacturing techniques and device structures, while reducing the breakdown voltage while reducing the series resistance, still face many technical challenges. Due to the structural characteristics of conventional high-power devices, multiple time-consuming, complicated, and expensive fabrication processes are often required, so the practical application and practicality of high-voltage semiconductor power devices are limited. As will be discussed below, high voltage power devices are complicated to manufacture and have low yields and benefits. In addition, semiconductor power devices are typically fabricated without the use of an original semiconductor wafer, but with a pre-processed wafer with an epitaxial layer. This undoubtedly increases the manufacturing cost of the semiconductor power device. Moreover, its functional and performance characteristics also depend on the process parameters used to form the epitaxial layer. Thus, for power devices that rely on the original pre-processed wafer, the use of such pre-processed wafers further limits the manufacturability and flexibility of production of these power devices.
Compared with the conventional process, the super junction technology has the advantages of obtaining a higher breakdown voltage while increasing the drain-source resistance Rdson. For standard power transistor cells, the breakdown voltage is highly dependent on the low doped drift layer. Therefore, the thicker the drift layer, the higher the rated voltage that can withstand, but the drain-source resistance Rdson increases significantly. In the conventional power device, the drain-source resistance Rdson and the breakdown voltage BV are approximately combined with the following functional relationship:
Rdson BV2.5
In contrast, charge balancing is achieved in the drift zone of a device with a superjunction structure. The drain-source resistance Rdson is combined with the breakdown voltage BV to be a more convenient functional relationship, namely:
Rdson BV
Therefore, in high voltage device applications, it is necessary to design and produce a semiconductor power device with a super junction structure in order to reduce the drain-source resistance Rdson while achieving a high breakdown voltage and improving device performance. The area near the channel in the drift zone has the opposite conductivity type. As long as the region near the channel is also doped with the opposite conductivity type, the relative doping concentration of the drift region will be higher. In the off state, the charges in these two regions cancel each other out, and the drift region is depleted and can withstand high voltage, which is called super junction effect. In the on state, since the doping concentration of the drift region is high, the drain-source resistance Rdson is relatively low.
However, in the manufacture of power devices, the traditional super junction technology still encounters many technical problems and limitations. Rather, multiple epitaxial layers and/or buried layers are required in some conventional structures. According to previous manufacturing processes, many device structures require multiple back etching and chemical mechanical polishing (CMP) processes. Moreover, these processes for fabricating process devices sometimes do not conform to standard casting processes. For example, some standard high-volume semiconductor foundries have oxide chemical mechanical polishing (CMP), but some of the super-junction techniques require hydrazine chemical mechanical polishing (CMP). Therefore, the structural characteristics and manufacturing process of these devices are determined, and they are not suitable for device applications from low pressure to high pressure. In other words, some processes are too costly and/or the process is too long and complicated to be suitable for high voltage rated device applications. As will be discussed further below, these conventional devices, which have different structural features and are manufactured by various processes, have difficulties and limitations that hinder the practical application of these devices in market demand.
Since the standard VDMOS does not have the functional characteristics of charge balancing, the conventional type of semiconductor power device suitable for high voltage includes a device having a standard structure as shown in Fig. 1A. According to the IV (current-voltage) performance test, and the simulation analysis of this type of device further confirms that it is for this reason that the breakdown voltage does not exceed the one-dimensional quality factor, the Jensen limit. In order to meet the high breakdown voltage requirements, devices with such a structure typically have a lower doping concentration in the drain drift region, resulting in a relatively higher on-resistance. In order to reduce the on-resistance, the wafer size of such devices is usually large. In view of the above disadvantages: the cost of the wafer is too high (the number of wafers on each wafer is too small) and is not suitable for the larger wafers in the standard package, although the manufacturing process of the device is simple and the production cost is not High, however, they are not satisfactory for high current, low impedance applications in standard packages.
The second type of semiconductor power device is a two-dimensional charge-balanced structure that achieves a breakdown voltage above the Jensen limit for a given impedance, or for a given breakdown voltage. Resistivity below the Jensen limit (on-resistance Rdson x device area). This type of device structure is commonly referred to as a superjunction technology device. In a superjunction structure, based on the PN junction and electrostatic field electrification technique in an oxide bypass device, in a drifting drain region of a vertical device, parallel to the charge balance in the direction of the current, the device can be obtained Higher breakdown voltage.
Figure 1B is a cross-sectional view of a device with a super junction. By increasing the drain doping concentration in the drift region, the resistivity of the device is reduced while maintaining the breakdown voltage (Rsp = impedance × Source area). By forming a P-type (for an n-channel device) vertical pillar in the drain, the drain is completely depleted in the horizontal direction at high voltage, and the channel is pinched and masked from the drain high voltage at the N+ substrate. Thereby achieving charge balance. This technique has been mentioned in the European Patent No. 0 053 854 (1982) and in the U.S. Patent No. 4,754,310, the entire disclosure of which is incorporated herein by reference. In the previous publications, the vertical superjunctions are vertical columns as N and P type dopants. In a vertical DMOS device, as shown in the drawing, one of the doped pillars is formed by doping a structure with sidewalls to obtain a vertical charge balance. In addition to doping columns, U.S. Patent No. 4,134,123 and U.S. Patent No. 6,037,632 also teach the use of doped floating islands to increase the breakdown voltage or reduce the resistance. This device structure of the super junction still passes through the depletion of the P-region, shielding the gate/channel from the drain. However, due to problems such as charge storage and conversion, this floating island structure is still limited by many technical problems.
For the super junction device described above, the preparation of such a device is generally complicated, expensive, and requires a long processing time due to the numerous processes, slow progress, and low yield. Specifically, these processes include a plurality of epitaxial layers and buried layers. Part of the structure even requires that the channel depth pass through the entire drift zone, and most processes require back etching or chemical mechanical polishing. In summary, these traditional structures and fabrication methods are slow and expensive to manufacture, are not economical, and are not suitable for a wide range of applications.
This patent application is a continuation-in-part of U.S. Patent Application Serial No. 12/005,878, the entire disclosure of which is incorporated herein by reference. A trench metal oxide semiconductor field effect transistor (MOSFET) is formed in the top epitaxial layer above the deep trench and the region around the deep trench. However, the electric field of the channel gate of such a device is high and is easily damaged by voltage breakdown.
Therefore, in addition to improving the structure and fabrication process of such a superjunction device, it is also necessary to mask the sensitive gate of the active cell during breakdown. Figures 1C-1 through 1C-3 show a device with a P-floating island 1 in most of the layers of the epitaxial layer described in U.S. Patent No. 6,635,906. However, these floating islands cannot self-align to the gate or the channel, and do not effectively protect the sensitive channel gate during voltage breakdown. Takaya et al. presented a "Floating Island and Thick Bottom Oxide Channel Gate Metal Oxide Semiconductor Field Effect Transistor (FITMOS)" at the 17th International Forum on Power Semiconductor Devices & Integrated Circuits, held in 2005. The structure, as shown in FIG. 1D, shows that the floating P-region implanted in order to achieve charge balance at the drain and the P-region at the bottom of the trench gate can be used to remove the gate from the P-region. Separated in the middle. However, since these P-emitter regions under the gate of the trench are in contact with the gate channel with a thick bottom oxide, the amount of current passing through the open circuit may be reduced.
Therefore, in the design and manufacturing process of power semiconductor devices, in order to solve the above difficulties and limitations, it is necessary to find a new power device structure and manufacturing method.

One aspect of the present invention is to provide a newly improved device structure and fabrication method for forming a doped column in a drift region to achieve charge balance by a simple and convenient fabrication process. No need for back etching or chemical mechanical polishing, the processing steps are simplified, only a single thin epitaxial layer is formed, and the epitaxial layer is simultaneously grown in the deep trench and over the deep trench, and on the top surface of the region around the deep trench to form a super junction structure. . An epitaxial pillar is formed in the epitaxial layer portion of the channel. A thin top epitaxial layer is formed over the deep trench and over the epitaxial layer portion above the surface of the deep trench region, and a trench metal oxide semiconductor field effect transistor cell is formed in this top epitaxial layer. The two epitaxial layers can be grown simultaneously as a single epitaxial layer. The trench gate of the transistor unit is further masked, and once a voltage breakdown occurs, the doped mask region is implanted through the trench gate into the drift region under the gate to form a self-calibrated doped mask region. Thus masking the sensitive gate solves the above difficulties and limitations. The doped mask region reduces the peak electric field at the gate of the trench; it also slows down the impact ionization rate and increases the breakdown voltage. The final structure improves the reliability and stability of the electrical parameters. The doped mask region is formed below the accumulation region below the trench gate and does not contact the trench gate. There is an additional doped layer under the gate channel, the conductivity type and the conductivity type of the accumulation region are the same, the doped layer can ensure that the doped mask region does not contact the gate channel, so that when the device is turned on The current passed is more.
Another aspect of the present invention is that the super junction structure and shape of the present invention can be used to flexibly adjust the range of breakdown voltages required. The manufacturing process is simple and can be conveniently prepared through standard processes using standard processing modules and equipment. Since the transistor portion of this structure, such as a trench gate double-diffused metal oxide semiconductor (DMOS), is self-calibrating, the fabrication process can be further simplified. The above technical problems and limitations will be solved.
Specifically, one aspect of the present invention is to provide a new and improved device structure and fabrication method for forming an epitaxial layer in a deep trench, and the epitaxial layer has a thin top epitaxial layer portion overlying the device. On the surface. Further, a part of the extension layer also serves as a body region of a metal oxide semiconductor field effect transistor (p-type in the case of an n-channel metal oxide semiconductor field effect transistor). Further, the metal oxide semiconductor field effect transistor unit formed in this top thin epitaxial layer is a channel metal oxide semiconductor field effect transistor. The trench gate is opened through a thin epitaxial layer with an optional trench sidewall and a trench bottom doped implant region to eliminate channels that may be affected by the depth of the trench gate and the doping concentration of the epitaxial layer Sensitivity to performance. A plurality of doped mask regions are implanted into the drift region below the gate through the gate trench prior to filling the gate trench with the gate polysilicon layer. The conductivity type of the doped mask region is the same as that of the body region of the MOSFET, and the doped mask region also functions as a gate mask doping region and self-aligns with the gate channel. The doped mask region can be a floating island or an epitaxial layer that is connected (biased) into the deep trench and thus connected to the body region. In particular, the situation of the floating island is not ideal because the floating traps the charge and causes the device to drift; the trapped charge takes time to diffuse out, which slows down the electrical conversion. The performance of the transistor unit can be controlled and adjusted by a simple and convenient manufacturing process. The super junction structure of the present invention can be applied to a wider range of fields by further improvement.
Another aspect of the present invention is to provide a new and improved apparatus structure and method for forming a transistor unit on a thin top layer, wherein a thin top layer is overlying the deep trench as an epitaxial layer, and around the deep trench and On the top surface above the deep channel. Ion implantation through the deep trench sidewalls (using ions of opposite conductivity types to fill the deep trench epitaxial layer) can adjust the doping concentration of the drift region around the deep trench to adjust and control including charge balance, drain-source resistance Rdson, and blow Device performance parameters including voltage. Thus, ion implantation provides a method of charge control that can further tune and tune the performance of semiconductor power devices for use in different types of applications.
Another aspect of the present invention is to provide a new and improved device structure and fabrication method for forming a power transistor unit with a shallow trench gate on a thin top P- epitaxial layer, wherein the thin top The P- epitaxial layer is located on the area around the top surface above the vertical channel and overlies the vertical channel. By channel doping implantation and sidewall doping implantation, the performance of the device channel can be flexibly adjusted. Sidewall doping implants and channel bottom doping implants are used to compensate for P- epitaxy and to protect proper accumulation and channel regions. Ion implantation is performed through the bottom surface of the gate trench before filling the gate trench with the polysilicon gate layer. A vertical mask is used to form a gate mask doped region to mask the sensitive trench gate during voltage breakdown.
Another aspect of the present invention is to provide a new and improved apparatus structure and method for forming a power transistor unit with a deep trench gate in a thin top layer, wherein the thin top layer serves as a The epitaxial layer is located on the area around the top surface above the epitaxial column and covers the top of the epitaxial column. The trench gate passes through the top thin epitaxial layer and extends to the substrate region, thus eliminating the need for doping of the bottom of the trench for the connection of the accumulation region. The gate mask doped regions implanted through the bottom surface of the gate trench form a calibrated doped region that still masks the trench gate for masking the sensitive trench gate during voltage breakdown. The trench bottom doping implant can still be used to ensure that the gate mask doped regions do not contact the gate trench.
A preferred embodiment of the invention briefly illustrates a semiconductor power device including a semiconductor substrate with a plurality of deep trenches. The deep trench is filled with an epitaxial layer; the epitaxial layer further includes a simultaneously grown top epitaxial layer overlying the top surface of the deep trench and over the semiconductor substrate. The conductivity type of the epitaxial layer is opposite to that of the semiconductor substrate. In the top epitaxial layer, a plurality of trench metal oxide semiconductor field effect transistor cells are formed, the top epitaxial layer is used as a body region, and the semiconductor substrate is used as a drain region, between the epitaxial layer in the deep trench and the region in the semiconductor substrate The charge balance is obtained to obtain a super junction effect. Each trench MOSFET unit further includes a trench gate disposed below and a gate mask doped region, self-aligned with each trench gate, and each channel metal oxide The semiconductor field effect transistor unit masks the trench gate during voltage breakdown. In a typical embodiment, each of the trench gates of the trench MOSFET is opened through the top epitaxial layer and filled with a gate dielectric material and a gate conductive material. In another exemplary embodiment, each trench gate of the trench MOSFET passes through the top epitaxial layer into the top of the semiconductor substrate with a gate trench in the semiconductor substrate The depth is greater than or equal to the thickness of the top epitaxial layer and is filled with a gate dielectric material and a gate conductive material. In another exemplary embodiment, the trench gate further includes a gate sidewall doped region around the trench gate sidewall and a gate-bottom doped region under the gate trench, wherein the gate sidewall doping The conductivity type of the region and the gate-bottom doping region is identical to the conductivity type in the semiconductor substrate. In another exemplary embodiment, the semiconductor substrate further includes a region around the deep trench whose doping concentration gradient is laterally distributed, and the doping concentration gradually decreases from the surrounding region, and the concentration rapidly decreases near the sidewall of the deep trench. In another exemplary embodiment, each MOSFET transistor cell has a gate sidewall around the sidewall of the trench gate and the gate-bottom doping region below the trench gate. The doped region, wherein the gate sidewall doped region and the gate-bottom doped region have the same conductivity type as in the semiconductor substrate. In another exemplary embodiment, the deep trench is near the bottom surface of the semiconductor substrate and the drain contact doped region surrounds the bottom of the deep trench for connecting the drain electrode. In another exemplary embodiment, the semiconductor power device further includes a bottom metal layer that forms a drain electrode that contacts the drain junction doped region. In another exemplary embodiment, the channel gate and deep trench of the trench metal oxide field effect transistor cell are filled with an epitaxial layer and the epitaxial layer is further processed into stripes with a gate mask doped region. As a floating doped region, it is disposed under the stripe of the trench gate. In another exemplary embodiment, the trench gate of the trench metal oxide field effect transistor cell is also processed into stripes with misaligned projections that extend alternately to the trench gate toward deep trenches filled with epitaxial layers. The opposite side of the pole is such that under the extended trench gate, the gate mask doped region is electrically connected to the body region of the transistor unit by an epitaxial layer disposed in the deep trench.
The present invention also provides a method of fabricating a semiconductor power device on a semiconductor substrate. The method comprises the steps of: a) preparing a semiconductor substrate; b) opening a plurality of deep trenches on the semiconductor substrate, and growing an epitaxial layer to fill the deep trenches, and covering the top surface of the semiconductor substrate with the top epitaxial layer, wherein the epitaxial deep trenches The epitaxial layer portion and the top epitaxial layer in the track are single layers grown simultaneously, wherein the epitaxial layer has the same conductivity type as the semiconductor substrate; c) a plurality of channel metal oxide semiconductor field effect transistors are formed in the top epitaxial layer a cell, by opening a plurality of trench gates, implanting a plurality of gate mask doping regions under the trench gates to mask a trench gate of the transistor unit when the voltage breakdowns the semiconductor power device, top The epitaxial layer functions as a body region, the semiconductor substrate functions as a drain region, and a superjunction effect is obtained by charge balance between the epitaxial layer portion in the deep trench and the substrate portion of the lateral deep trench in the semiconductor substrate. In a typical embodiment, the method further includes forming a level concentration gradient in the semiconductor substrate region between the deep trenches by deep channel sidewall implants with dopants of the first conductivity type, and adjusting the deep channel Sidewall implantation changes the performance of semiconductor power devices. In another exemplary embodiment, the method further includes implanting a dopant of the same conductivity type as the semiconductor substrate to the sidewalls and bottom of the gate trench. In another exemplary embodiment, the process of preparing a semiconductor substrate includes preparing a single layer semiconductor substrate, wherein the step of opening a plurality of deep trenches includes opening a plurality of deep trenches in the single layer semiconductor substrate. In another exemplary embodiment, the process of preparing a semiconductor substrate includes preparing a bottom substrate, and growing a top substrate layer on the underlying substrate, the top substrate layer having the same conductivity type as the underlying substrate. In another exemplary embodiment, the method further includes heavily doping at the bottom of the deep trench to form a drain contact region prior to growing the epitaxial layer; grinding the back of the substrate to expose the drain contact region. In another exemplary embodiment, the method further includes partially chemical mechanical polishing the top surface of the epitaxial layer to smooth it prior to forming the plurality of trench metal oxide semiconductor field effect transistor cells.

Referring to the cross-sectional view of the metal oxide semiconductor field effect transistor device 100 shown in Fig. 2, a new idea of the structure and manufacturing of the present invention is proposed. A detailed description of the metal oxide semiconductor field effect transistor device 100 will be described later in FIG. The metal oxide semiconductor field effect transistor device 100 is disposed on a substrate 105 having an N+ doped bottom region 120 therein functioning as a drain contact region through a deep trench 130 filled with an epitaxial layer (as shown in FIG. 3) Shown by back grinding). The substrate 105 also contains a top portion 125 in which the deep trench 130 is formed. For example, for an n-channel MOSFET, the substrate 105 is n-type and the epitaxial layer in the deep trench is p-type. The metal oxide semiconductor field effect transistor transistor unit is located on a single thin epitaxial layer, fills the epitaxial pillar channel 130, and covers the top surface around the P-epitaxial pillar, and fills the P- epitaxial filler in the pillar channel. A thin portion of the P- epitaxial layer above the top surface also serves as a body region surrounding the trench gate 145 filled with gate polysilicon. The P-body region 150 also surrounds the source region 155 located around the trench gate 145. The trench gate 145 is padded with a gate oxide layer 140, filled with a polysilicon, and covered by an insulating layer 160 with a contact opening to connect the source-body between the trench gates 145 through the source contact metal region. The trench gate 145 is masked by a gate-mask doping region 144 that is implanted through the gate trench before filling the trench with a gate polysilicon. Thus, the gate-mask doping region 144 and the trench gate 145 are self-aligned. The conductivity type of the gate-mask region 144 is the same as the conductivity type of the epitaxial layer filled in the epitaxial pillar channel 130.
The device as shown in Figure 2 has a single thin epitaxial layer to form a trench gate in which the channel of the trench gate is filled with gate polysilicon and through which openings are formed. This new structure achieves the performance requirements of the super junction, such as not exceeding the "Jensen limit", the breakdown voltage does not vary with the thickness of the epitaxial layer grown on the starting substrate, and the like. The absolute breakdown voltage is due to the depth of the channel in the semiconductor substrate and the charge balance in the epitaxial column channel between the substrate regions. The thickness of the epitaxial germanium growth is only a function of the deep trench width etched in the germanium substrate. Conventional devices must grow the epitaxial layer as a drift region, the thickness of which is proportional to the required breakdown voltage, so conventional devices do not have the flexibility described above.
The structure shown in the figure is flexible in size and can be produced by a simple manufacturing method. For example, to create a device that is below Jensen's limit, low resistivity, and wide range of breakdown voltages (eg, 200V to 900V), can be etched to a desired depth by a single epitaxial layer of a few microns. A single channel etch with a proportional voltage (>200V approximately 10-15 microns, >600V approximately 40-50 microns, >900V approximately 70-90 microns). In addition, the structure of the transistor portion on the top of the epitaxial layer 130 is based on the channel gate double-diffused metal oxide semiconductor device, wherein the device structure is self-aligned, and the fabrication method is convenient and simple. The sensitive channel gate 145 portion of the device is remote from the seam above the channel 130, which also increases the reliability of the device and eliminates unnecessary chemical mechanical polishing processes.
Referring to Fig. 3, a cross-sectional view of the MOSFET device 100 is fabricated according to the process described in Figs. 13A through 13N, depending on the novel design concept and the basic structure shown in Fig. 2. The MOSFET device 100 is located on an N-type substrate and includes an N+ doped bottom region 120 as a drain contact region over which the top drain electrode 110 is in direct contact. The drain contact region 120 is doped through a deep channel containing epitaxial layer 130. Each deep trench is filled with a P- epitaxial layer and covers the top surface around the trench and above the trench. The metal oxide semiconductor field effect transistor transistor unit is on a single thin P- epitaxial layer, and a single thin P- epitaxial layer is filled in the epitaxial pillar channel 130 and overlying the top surface around the P-extension pillar. A thin P- epitaxial layer above the top surface is formed by a P-body region 150 around the trench gate 145, a trench gate 145 with a gate polysilicon is filled in the trench, and the trench is opened through the top epitaxial layer 130. The P-body region also surrounds the source region 155 around the trench gate 145. The trench gate 145 is filled with a gate oxide layer 160, and the trench gate 145 is covered with an insulating layer 160 having a tab opening such that the source contact metal 170 over the metal barrier layer 165 contacts the trench gate 145. Source-body area. The p-type gate mask doping region 144 further masks the trench gate 145 and is implanted into the N-substrate region 125 through the gate trench before the gate polysilicon fills the gate trench. The gate mask doping region 144 protects the sensitive gate 145 when a voltage breakdown occurs in the MOSFET device. The N substrate region 125 around the P-epitaxial pillar 130 can be implanted through the sidewall of the deep trench 130 with an N-dopant to obtain a level doping concentration gradient and control the N-column charge.
A superjunction effect or charge balance is obtained by balancing the charge of the P- epitaxial layer filled in the channel in the horizontal direction, that is, a leak in the n-type drift region 125 perpendicular to the vertical metal oxide semiconductor field effect transistor structure. The polar current flows to obtain charge balance, and when the metal oxide semiconductor field effect transistor is in an off state, the drain current is depleted. In other words, the amount of charge of the P- epitaxial layer filled in the channel is substantially equal to the amount of charge of the N-drift region near the N substrate, within the manufacturing tolerances. The control and regulation of the charge in the N-drift zone can be by doping the N-substrate, or doping the N-substrate with any other N-doped ions implanted in the deep channel sidewalls. For ideal conditions, the target charge is P = N = 1E12 atoms per square centimeter. In the manufacturing process, the power control is more flexible by the implantation concentration, implantation annealing, substrate doping concentration, epitaxial doping concentration, channel depth, width and shape, and other processing parameters, and the device structure is more flexible. Optimized for easy tuning to achieve lower resistivity at a given breakdown voltage.
The metal oxide semiconductor field effect transistor transistor unit further includes an N-type doped implant region 135-S along the gate sidewall and an N-type doped implant region 135-B under the bottom of the gate trench. The sidewall and bottom doped implant regions surrounding the gate 145 can be used to eliminate metal oxide semiconductor FET device channels, sensitivity to channel depth and P- epitaxial doping concentration. Embodiments of this novel structure are contemplated to be based on the formation of a high performance metal oxide semiconductor field effect transistor structure in a P- epitaxial layer. The epitaxial layer grows with the smallest or no back-etched P- epitaxial layer. To operate a metal-oxide-semiconductor field effect transistor, the source conductivity type must be consistent with the drain, opposite the body, and an accumulation region connects the channel to the drain. After the trench gate vertical metal oxide semiconductor field effect transistor structure is realized, the source is at the top, and the channel is along the sidewall of the gate channel, and is formed in the body region below the source. The accumulation region must be formed between the body region and the drain. For the novel high voltage device of the present invention, when the P-epitaxial growth on the top level surface of the N substrate is thick, it is difficult to form a high performance vertical channel gate metal oxide semiconductor field effect transistor. If the P- epitaxial layer is thick, the gate trench must be deep in order to pass through the N-drift drain region. The combination of the deep channel and the thick P body region causes the channel to become longer and the channel resistance to increase, eventually resulting in a decrease in the performance of the vertical double-diffused metal oxide semiconductor structure. Therefore, in the embodiment of the present invention, in the case of the P- epitaxial layer, additional dopants are implanted in the sidewalls and the bottom of the gate trench so that the thickness of the gate trench is generally 0.8 to 1.5 μm. Typical gate channel thickness in the range is 1 to 3 microns thick. These additional doped implants are used to compensate for the P-epitaxial regions in the accumulation and drain regions near the gate channel in order to obtain a high performance, short channel vertical channel double diffused metal oxide semiconductor device. . Therefore, prior to processing the MOSFET device, implanting additional tilted and non-tilted implants in the gate trench will result in a high performance trench gate MOSFET device, It is again dependent on the P- epitaxial layer thickness and doping concentration in these regions. The n-type dopant implant 135-B at the bottom of the gate trench can also be used to protect the gate mask region 144 from contact with the gate channel 145.
It should be noted that the embodiment in Figure 3 shows a gate channel through the P- epitaxial layer, as well as additional N-type implants 135-S, 135-B, which can be used to optimize metal oxides. The performance of the semiconductor FET without completely compensating for the P-doped region, ie the P- epitaxial layer on the sidewall of the gate trench. The implant is preferably phosphorus and arsenic or antimony. The energy should be in the range of 50 KeV to 200 KeV. The angle of inclination with the bottom implant should be zero degrees and the angle of inclination with the sidewall implants is +/- 5 to 15 degrees. The implant dose should be in the range of 1E11 to 1E13. An additional P-type body implant can be used to form the body region 150 and maintain the channel region in a direction along the sidewalls of the trench gate 145.
Figure 4 is a cross-sectional view showing an alternative embodiment of a metal oxide semiconductor field effect transistor device similar to that shown in Figure 3, except that the sidewalls of the N-substrate region 125' are not implanted. N dopants to achieve charge control functions through the fabrication process. Since it is assumed that the doping concentration of the initial N-substrate is sufficiently large to achieve charge balance with the P-type epitaxial layer grown in the deep channel, this embodiment does not require introduction of an additional N-doped region into the sidewall of the deep trench. in. When the actual value of the doping concentration can reach the desired charge balance, that is, the absolute value of the N charge = P charge = 1E12 particles / cm2, the doping concentration of the initial N-substrate is sufficient. When the substrate concentration can achieve charge balance within the required tolerance limits (for example, when the repeatability of the N-substrate with sufficient doping concentration is greater than +/- 10%), it is not necessary to Charge control is achieved by doping the implant.
Figure 5 is a cross-sectional view showing an alternative embodiment of a MOSFET device similar to that shown in Figure 3, except that the MOSFET device does not include sidewalls. And the channel bottom doping implant regions 135-B and 135-S shown in FIG. When the depth of the trench gate 145 is large and extends below the epitaxial layer 130 into the substrate region 125, it is no longer necessary to use the trench sidewall and the trench bottom doped implant region to eliminate the channel-to-channel. Sensitivity of gate depth.
Figure 6 is a cross-sectional view showing an alternative embodiment of a metal oxide semiconductor field effect transistor device similar to that shown in Figure 3, except that the trench of the metal oxide semiconductor field effect transistor device The depth of the pole is shallower than the depth of the epitaxial layer. The metal oxide semiconductor field effect transistor device includes a gate trench sidewall and a gate trench bottom doped implant region 135-S and 135-B for respectively compensating the P- epitaxial layer 130 and ensuring that the device has appropriate Accumulation zone and channel zone. This embodiment is based on the structure that the metal oxide semiconductor field effect transistor device has a thick P- epitaxial layer or a shallow gate channel, or both. The gate channel does not reach the N drain region. In order to ensure proper and efficient operation of the transistor, the lower portion of the gate trench must be doped as an N-doped region 135-B to form an active trench in the body region along the sidewall of the gate trench. The channel is connected to the drain.
Conventional wafers have heavily doped substrates, as well as lightly doped top layers. However, the device shown in Figures 2 through 6 made of a conventional wafer does not have an epitaxial layer at first. Although this can save a lot of wafer cost, it has an extra process of bottom doping through deep trench and back grinding of the wafer. In addition, the apparatus shown in Figures 7 through 8 uses a conventional wafer with a heavily doped N+ underlying substrate 121, and a sub-heavy doped N-type top substrate layer 126 grown over the N+ underlying substrate 121. . In a conventional wafer, such an N-type top substrate layer 126 is generally considered to be an epitaxial layer, and in this patent, to avoid confusion, it is referred to as a top substrate layer. Figure 7 is a cross-sectional view showing an alternative embodiment of a MOSFET device similar to that shown in Figure 3, except that the deep trench 130 filled with the epitaxial layer is now located at the top lining The bottom layer 126 extends into the heavily doped underlying substrate region 121. It is no longer necessary to form the individual drain contact regions 120 as shown in FIG. 3 by a separate doping implantation process. In contrast, in the present embodiment, one heavily doped N+ underlying substrate region 121 serves as a drain junction, and an N-type top substrate layer 126 is grown on top of the N+ underlying substrate region 121. In order to save cost, the thickness of the top substrate region is generally small compared to conventional wafers. This embodiment does not necessarily require back grinding. Metal drain electrode 110 may be formed under heavily doped underlying substrate region 121.
The drain contact doping implantation process at the bottom of the deep trench can be omitted, thus greatly simplifying the fabrication process.
Figure 8 is a cross-sectional view showing an alternative embodiment of a metal oxide semiconductor field effect transistor device similar to that shown in Figure 7, except that the thickness of the deep trench 130 filled with the P- epitaxial layer Less than the N+ underlying substrate 121.
Fig. 9 is a plan view showing the strip structure of the semiconductor power device of the present invention. The epitaxial deep channel grown with the epitaxial layer 130 forms a strip structure. The outline of the epitaxial deep trench 130 is indicated by a chain line. The channel gate 145 included in the transistor unit also forms a linear strip structure, and the trench gate 145 is filled with the gate oxide layer 140 around the source region 155 and surrounded by the body region 150. A self-calibrated gate mask doped region (not explicitly shown) is also formed as a floating strip under the trench gate 145.
Figure 10 shows an alternative embodiment of another different transistor unit structure. The gate mask P-doped region 144 should be extended to the P-column 130 region of a portion of the transistor unit as shown in FIG. 10 by using the trench gate 145 as a cross-channel gate, connected to the body region. The gate mask doping region 144 is processed into a floating region on the P-doped epitaxial pillar 130 below 150 instead of below the trench gate 145. Figure 11 is a similar embodiment except that the extended trench gate 145 is provided with misalignment projections 145-TB to reduce the drain-source on-resistance Rdson, improving the manufacturability of the device (in filling ten When the glyph gate channel is used, a hole problem may occur). Fig. 12 shows the same structure as Fig. 11, explaining how the gate mask doped region protrusions 144-TB are self-aligned under the gate trenches 145, and how the P-doped pillars 150 are contacted by diffusion. . A gate mask doping region 144 is implanted under the main gate strips 145 and below the gate bumps 145-TB perpendicular to the main gate strips. The P-mask doped region 144 is electrically contacted to the p-body 150 region by interposing a contact region between the gate mask doped region protrusion 144-TB and the p-extension pillar 130. The misalignment structure reduces the effect on the channel width. As long as current flows through the other side of the channel gate projections 145-TB, the misalignment projections can also obtain a better distributed current.
Referring to a series of side cross-sectional views of Figures 13A through 13N, the fabrication steps of the charge balancing semiconductor power device as shown in Figure 3 are illustrated. Figure 13A shows that the initial germanium substrate comprises a substrate 205 having an impedance of about 10 ohm/cm. Substrate 205 does not initially have an epitaxial layer. A hard mask oxide layer 212 having a thickness of about 0.1 to 1.5 microns is disposed or thermally grown. An oxide etch is then performed using a trench mask (not shown) having a critical dimension in the range of 1 to 5 microns, opening a plurality of channel etch windows, and then removing the photoresist. With germanium etching, a deep trench 214 having a depth of about 40 to 50 microns is turned on for a device operating at about 650 volts. Depending on the type of etcher and the etch chemistry, a photoresist mask can also be used to form the etch pattern and turn on the trench without the use of a hard mask oxide layer 212 as shown. The channel opening can be in the range of 1 to 5 microns, but 3 micron is preferred in most device applications (the channel opening is determined by the previously mentioned channel mask). Wafer cleaning is then performed. In Fig. 13B, a positively projected oxide layer 215 is formed by an oxide setting or a thermal growth process. If the oxide layer on the bottom surface is thicker, then an anisotropic etch of the optional reactive ion etch is used to remove oxide from the bottom surface of the trench. If an optional reactive ion etching process is not employed, the thickness of the oxide layer 215 is between 0.015 and 0.1 microns. If an alternative reactive ion etching process is employed, the thickness of the oxide layer 215 is between 0.0151 and 0.4. Between microns. In order to form the drain contact region 220 directly under the deep trench 214, the drain contact implant is performed, that is, the N+ ion is implanted in a direction perpendicular to the tilt angle of the trench sidewall, that is, the vertical implant is implanted at a dose greater than 1E15. . The drain contact region 220 is implanted with an N-type ion such as phosphorus or arsenic. The oxide layer 215 is oriented along the sidewalls to protect the sidewalls from high doses of drain contact implants.
In Fig. 13C, N-type ions such as phosphorus are implanted into the channel sidewalls to set the doping concentration in the N region. Depending on the depth of the channel, the tilt implant is tilted with an implant dose of 5E11 to 2E13 and a tilt angle of 5 to 15 degrees to form an N region 225 in the channel. In Figure 13D, annealing at a high temperature of 1050 to 1200 degrees Celsius for 30 to 60 minutes in a very low oxygen and/or nitrogen atmosphere allows the N+ drain contact region 220 to diffuse and the sidewall implant N-zone 225 level diffusion. The N-zone 225 forms a level N-type concentration gradient with a concentration that is greatest near the sidewalls of the deep trench. To achieve charge balance (super junction effect), along with the P- epitaxial layer 230 (to be grown), the N-type concentration of the region beside the deep channel in the substrate 205 can be adjusted by sidewall implantation. Alternatively, for sidewall implantation, substrate 205 is initially formed with the desired N-type concentration to achieve a superjunction effect. In Fig. 13E, the oxide layers 212 and 215 are etched away, and a P- epitaxial layer 230 is grown in which the P doping concentration is 1E15 to 1E16 or even higher. The thickness of the P- epitaxial layer 230 is sufficient to fill the trench 214. Channel 214 is about 3 microns wide and epitaxial layer 230 over the top of N-region 225 has a thickness of about 1.5 to 2.0 microns. In Fig. 13F, an oxide layer having a thickness of about 0.5 to 1.5 μm is provided as a hard mask layer 228, and a hard mask oxide layer 228 is etched by a gate trench mask (not shown) and then removed. Photoresist. The width of the gate channel is typically in the range of 0.4 to 1.5 microns. The trench gate opening 232 is etched through the P- epitaxial layer 230 by a germanium etch, with a channel depth of about 1 to 2.5 microns, possibly passing through the P- epitaxial layer 230 into the channel 212. An N-doped region 225 between the epitaxial pillars 230. Wafer cleaning followed by a circular hole etch to smooth the gate trench structure and then clean the next wafer.
In Fig. 13G, the oxidized hard mask 228 is removed, and then a thin screen layer 234 is provided covering the sidewalls and bottom surface of the gate trench 232. Deep P-type implanted with boron ion (B11), energy between 200 and 600 KeV, dose between 1E12 and 1E13, implanted at zero tilt angle for under gate channel 232 in N-doped column 225 A gate mask P-doped region 244 is formed. In Figure 13H, an N-type gate channel sidewall implant can be selected with a tilt angle (implant angle) between +/- 5 and 7 degrees to compensate for the P- epitaxial layer 230 if the gate trench If the track 232 is too shallow, the bottom of the n-type gate trench with a zero tilt angle is implanted to compensate for the P- epitaxial layer 230, or to ensure that the gate mask P-doped region 244 does not contact the gate trench 232. The implant enters the sidewalls and the bottom surface of the gate trench to form sidewall and bottom doped regions 235-S and 235-B, respectively, eliminating the channel of the MOSFET device for the channel gate depth and P-epitaxial The sensitivity of the doping concentration/thickness of layer 230. In Fig. 13I, the gate oxide layer 234 is removed, and a gate oxide layer 240 having a thickness of between 0.01 and 0.1 micrometers is grown, the thickness of which depends on the rated voltage of the device. A gate polysilicon layer 245 is disposed in the gate trench 232. The gate polysilicon layer 245 is preferably doped by in-situ N+; if in-situ doping is not used, the polysilicon layer 245 is doped by ion implantation or diffusion. The gate polysilicon layer 245 is back etched from the top surface around the trench gate 245.
In Fig. 13J, a bulk mask (not shown) can be used, the body is implanted with boron at a dose between 3E12 and 1E14, and then bulk driven at 1000 to 1500 degrees Celsius, around the trench gate 245. In the epitaxial layer 230, a P-body region 250 is formed. The body implant can form a good contact with the body region and also ensure that the metal oxide semiconductor field effect transistor channel region is always above the gate sidewall implant 235-S. Figure 13K shows the source doping implant. A source implant mask (not shown) can be used to protect this location from forming a P-body contact. The source is implanted with a source-doped ion such as arsenic ion at a potential of about 70 KeV, a dose of about 4E15, and a zero-degree tilt angle, and then a source annealing operation is performed at 800 to 950 degrees Celsius to diffuse the source region 255. . In Fig. 13L, a dielectric layer 260 formed by a low temperature oxide arrangement (LTO) and a beryllium glass (BPSG) layer 260 containing boric acid are formed on the top surface, and then a bismuth glass flow operation containing boric acid is performed. An etch mask is performed using a contact mask (not shown) to etch the contact opening through a bismuth glass layer 260 containing boric acid. P+ body contact implantation is optional and then reflows after body contact implantation. In Fig. 13M, a barrier metal is provided covering the top surface of the barrier metal layer 265, and then a thick metal is formed to form the source metal layer 270. A metal mask (not shown) is used to etch the source metal 260 and the gate metal (not shown) and form a pattern. The dielectric layer is provided to passivate the surface of the device, and the pattern of the passivation layer is used to form the opening of the bonding region (not shown), the entire process is completed, and the final casting is completed. For the sake of simplicity, the production process of these standards is not detailed here. In Fig. 13N, the low doped portion of the substrate 205 is removed from the bottom surface of the substrate by back grinding, and then the back metal layer 210 is formed to contact the drain region 220 when the doping concentration is high. The back metal layer 210 can be formed by directly providing a TiNiAg layer on the back surface of the wafer. The thickness of the back grinding process can be controlled to a few microns or even 1 micron, enabling reliable back contact to form the drain electrode layer 210 to contact the N+ drain contact region 220.
Although the present invention has been presented in its preferred embodiments, these disclosures are not intended to be limiting. Those skilled in the art will be able to grasp various other changes and modifications after reading the above description. For example, although the above embodiment uses an n-channel device, the present invention can be applied to a p-channel device by changing the conductivity type of the semiconductor region. All changes and modifications that come within the scope of the appended claims are therefore intended to be
Although the present invention has been described in detail by the preferred embodiments thereof, it should be understood that the foregoing description should not be construed as limiting. Various modifications and alterations of the present invention will be apparent to those skilled in the art. Therefore, the scope of the invention should be limited by the scope of the appended claims.

100‧‧‧Metal Oxide Semiconductor Field Effect Device
105‧‧‧Substrate
110‧‧‧Metal drain electrode
120‧‧‧N+ doped bottom region
121‧‧‧N+ bottom substrate
125‧‧‧Top part, N-substrate area, n-type drifting area
126‧‧‧N-type top substrate layer
130‧‧‧deep channel, epitaxial layer
135-S‧‧‧N type doping implant area
135-B‧‧‧N type doping implanted area
140‧‧‧Gate oxide layer
144‧‧‧Gate-mask doped area
145‧‧‧channel gate
145-TB, 144-TB‧‧‧ bulging
150‧‧‧ body area
155‧‧‧ source area
160‧‧‧Insulation
165‧‧‧Metal barrier
170‧‧‧Source is attached to metal
205‧‧‧Substrate
210‧‧‧Back metal layer, drain electrode layer
212‧‧‧ Hard mask oxide
214‧‧‧deep channel
215‧‧‧Oxide layer
220‧‧‧Drain region, N+ drain contact region
225‧‧‧N-doped region, N-doped column
228‧‧‧hard mask layer
230‧‧‧P-epitaxial layer
232‧‧‧Gate channel
234‧‧‧ Thin screen layer
235-S‧‧‧ side wall
235-B‧‧‧Bottom doped area
240‧‧‧ gate oxide
244‧‧‧P-doped zone
245‧‧‧Gate polysilicon layer
250‧‧‧P-body area
255‧‧‧ source area
260‧‧‧Medium layer, glass layer
270‧‧‧ source metal layer

1A to 1B are cross-sectional views showing the structure of a conventional vertical power device fabricated by a conventional method;
1C-1 through 1C-3 illustrate cross-sectional views of floating islands formed in a bulk epitaxial layer not aligned with gate and gate trenches;
1D is a cross-sectional view showing a doped region under the gate channel connecting the trenches;
2 to 8 are cross-sectional views of a high voltage power device with a super junction structure in accordance with various embodiments of the present invention;
9 through 12 are plan views showing various layout structures for arranging channel mask doped regions;
13A through 13N are cross-sectional views showing the processing steps of the present invention for fabricating a high voltage power device similar to that shown in Fig. 3, with a super junction structure and a self-aligning channel mask. Doped area.

100‧‧‧Metal Oxide Semiconductor Field Effect Device

110‧‧‧Metal drain electrode

120‧‧‧N+ doped bottom region

125‧‧‧Top part, N-substrate area, n-type drifting area

130‧‧‧deep channel, epitaxial layer

135-S‧‧‧N type doping implant area

135-B‧‧‧N type doping implanted area

140‧‧‧Gate oxide layer

144‧‧‧Gate-mask doped area

145‧‧‧channel gate

150‧‧‧ body area

155‧‧‧ source area

160‧‧‧Insulation

165‧‧‧Metal barrier

170‧‧‧Source is attached to metal

Claims (29)

A semiconductor power device, comprising:
a semiconductor substrate having a plurality of deep trenches;
An epitaxial layer filled in said deep trench, said epitaxial layer comprising a simultaneously grown top epitaxial layer covering a region on said top surface of said deep trench, and said semiconductor substrate, wherein said epitaxial layer has a conductivity type and The semiconductor substrate is reversed;
a plurality of channel metal oxide semiconductor field effect transistor cells disposed in said top epitaxial layer, a top epitaxial layer as a body region, a semiconductor substrate as a drain region, an epitaxial layer in a deep trench, and a side semiconductor substrate a charge balance between the regions in the middle, obtaining a superjunction effect; and each of the plurality of channel metal oxide semiconductor FET cells further includes a trench gate and a subsurface disposed therewith and each trench The channel gate of the MOSFET has a substantially calibrated gate mask doped region to mask the trench gate during voltage breakdown, wherein the conductivity type of the gate mask doped region Contrary to the substrate. The semiconductor power device according to claim 1, wherein
The gate mask doping region is disposed at a distance from the bottom surface of the trench gate and does not contact the trench gate. The semiconductor power device of claim 1, further comprising:
The gate bottom doped region is disposed under each trench gate and is implanted with the same dopant as the substrate of the conductivity type, which is over the gate mask doped region. The semiconductor power device according to claim 1, wherein
The trench gate is located within the top epitaxial layer, between the deep trenches. The semiconductor power device according to claim 1, wherein
The channel gate of each of the channel metal oxide semiconductor field effect transistor cells extends through the top epitaxial layer, and the depth of the gate channel is less than or equal to the top epitaxial layer thickness of. The semiconductor power device according to claim 1, wherein
Each of the channel gates extends through the top epitaxial layer and into the top of the semiconductor substrate. The semiconductor power device according to claim 1, wherein
The trench gate further includes a gate sidewall doped region surrounding the trench gate sidewall, and a gate bottom doped region under the trench gate, wherein the gate sidewall doping The conductivity type of the region and the bottom doped region of the gate is the same as the conductivity type of the semiconductor substrate. The semiconductor power device according to claim 1, wherein
The semiconductor substrate further includes a region surrounding the deep trench having a level doping concentration gradient that gradually decreases from a region immediately adjacent to the deep trench sidewall. The semiconductor power device according to claim 2, characterized in that
Each of the MOS field effect transistor units further includes a gate sidewall doped region surrounding the trench gate sidewall, and a gate bottom doped region under the trench gate The conductivity type of the gate sidewall doping region and the gate bottom doping region is the same as the conductivity type of the semiconductor substrate. The semiconductor power device of claim 1, further comprising:
A drain adjacent the bottom surface of the semiconductor substrate surrounding the bottom of the deep trench contacts the doped region. The semiconductor power device according to claim 1, wherein
The gate mask doped regions constitute a floating island. The semiconductor power device according to claim 1, wherein
The gate mask doped region is electrically connected to the body region of the metal oxide semiconductor field effect transistor unit. The semiconductor power device according to claim 1, wherein
Said channel gate of said channel metal oxide semiconductor field effect transistor unit, and said deep channel filled with said epitaxial layer, in the form of stripes, said gate mask doping The impurity region is disposed under the stripe of the channel gate as a floating doping region. The semiconductor power device according to claim 1, wherein
The trench gate of the channel metal oxide semiconductor field effect transistor unit is in the form of a stripe having a protrusion toward the portion filled with the epitaxial layer The deep channel direction extends to electrically connect the gate mask doping region under the bump channel gate to the epitaxial layer filled in the deep trench On the body region of the transistor unit. The semiconductor power device according to claim 1, wherein
The channel gate of the channel metal oxide semiconductor field effect transistor unit is also in the form of a stripe with a dislocation protrusion, the dislocation protrusion being at the channel gate On the opposite side, alternately extending toward the deep trench filled with the epitaxial layer to fill the gate mask doped region under the trench gate protrusion by filling in the deep trench The epitaxial layer in the track is electrically connected to the body region of the transistor unit. The semiconductor power device according to claim 1, wherein
The semiconductor substrate further includes a heavily doped underlying substrate and a lightly doped top substrate grown over the underlying substrate, wherein the deep trench is formed primarily in the top substrate. The semiconductor power device according to claim 12, characterized in that
The deep channel extends to the underlying substrate. The semiconductor power device according to claim 12, characterized in that
The deep channel extends into the top of the substrate but does not touch the bottom of the substrate. A semiconductor power device, comprising:
a semiconductor substrate comprising a deep trench;
a single epitaxial layer filling the deep trench and covering the top surface of the semiconductor substrate; and a plurality of trench metal oxide semiconductor field effect transistor cells formed in the top of the epitaxial layer over the semiconductor surface, wherein a portion of the semiconductor beside the deep trench a substrate, which functions as a drift layer of the channel metal oxide semiconductor field effect transistor unit, and wherein the trench gate of the channel metal oxide semiconductor field effect transistor unit forms a drift between the deep trenches a portion of the epitaxial layer above the region, and through the charge balance between the drift region and the epitaxial layer portion of the deep trench, the semiconductor power device obtains a super junction effect; and a gate mask doped region is disposed in each channel Below the gate, and substantially aligned with each of the trench gates, the trench gate is masked when a voltage breakdown occurs in each of the trench MOSFETs. The semiconductor power device according to claim 19, characterized in that
The gate mask doping region is disposed at a distance from the bottom surface of the trench gate and does not contact the trench gate. A method of forming a semiconductor power device on a semiconductor substrate, comprising:
Preparing a semiconductor substrate;
Opening a plurality of deep trenches in the semiconductor substrate, growing a top epitaxial layer, filling the deep trenches therewith, covering a top surface of the semiconductor substrate, wherein a portion of the epitaxial layer in the deep trench and the top epitaxial layer Both are grown simultaneously as a single layer, wherein the conductivity type of the epitaxial layer is opposite to that of the semiconductor substrate; and in the top epitaxial layer, by opening a plurality of gate channels, and in the gate trench A plurality of gate mask doped regions are implanted under the track to form a plurality of channel metal oxide semiconductor field effect transistor cells to mask the transistor unit when voltage breakdown occurs in the semiconductor power device The trench gate, the top epitaxial layer acts as a body region, and the semiconductor substrate acts as a drain region, wherein a charge balance is achieved between a portion of the epitaxial layer in the deep trench and a portion of the semiconductor substrate next to the deep trench to obtain a super Junction effect. The method for forming a semiconductor power device on a semiconductor substrate according to claim 21, further comprising:
A dopant having a first conductivity type is implanted through a sidewall of the deep trench to form a level concentration gradient in a region between the deep trenches in the semiconductor substrate, and by adjusting a deep trench sidewall implant Into, adjusting the device performance of the semiconductor power device. A method of forming a semiconductor power device on a semiconductor substrate as described in claim 21, characterized in that
The step of implanting a plurality of gate mask doping regions under the gate channel further includes implanting the plurality of locations below a bottom surface of the gate channel A gate mask doped region, wherein the gate mask doped region does not contact the trench gate. The method for forming a semiconductor power device on a semiconductor substrate according to claim 21, further comprising:
A doped region of the same conductivity type as the substrate is implanted through the bottom of the gate trench. The method for forming a semiconductor power device on a semiconductor substrate according to claim 21, further comprising:
A dopant of the same conductivity type as the substrate is implanted into the sidewalls and bottom of the gate trench. The method for forming a semiconductor power device on a semiconductor substrate according to claim 21, further comprising:
The step of preparing a semiconductor substrate includes preparing a single-layer semiconductor substrate, and wherein the step of opening a plurality of deep trenches includes opening a plurality of deep trenches in the single-layer semiconductor substrate. The method for forming a semiconductor power device on a semiconductor substrate according to claim 21, further comprising:
The step of preparing a semiconductor substrate further includes preparing a heavily doped underlying substrate and growing a top substrate layer over the underlying substrate, wherein the top substrate layer has the same conductivity type as the bottom substrate. The method for forming a semiconductor power device on a semiconductor substrate according to claim 26, further comprising:
The deep trench bottom is heavily doped to form a drain contact region before the epitaxial layer is grown; and the substrate is back ground to expose the drain contact region. The method for forming a semiconductor power device on a semiconductor substrate according to claim 21, further comprising:
Prior to the step of forming the plurality of trench metal oxide semiconductor field effect transistor cells, a partial chemical mechanical polishing of the top surface of the epitaxial layer is performed to smooth the top surface.