TWI439188B - Printed circuit board - Google Patents
Printed circuit board Download PDFInfo
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- TWI439188B TWI439188B TW98143479A TW98143479A TWI439188B TW I439188 B TWI439188 B TW I439188B TW 98143479 A TW98143479 A TW 98143479A TW 98143479 A TW98143479 A TW 98143479A TW I439188 B TWI439188 B TW I439188B
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- printed circuit
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- transmission line
- hollowed out
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Description
本發明係關於一種印刷電路板。This invention relates to a printed circuit board.
在高速電路中,為了消除直流訊號對接收端參考電平的影響,經常採用電容對高速訊號進行隔離直流,耦合交流。常見的方法是採用電容直接連接到訊號線上,電容參考層是完整的平面,返回訊號可以直接從電容下方的參考層回流。請參考圖1的時域反射波形圖,其為以0402封裝的電容為例做訊號仿真,仿真時焊盤寬度為20密爾,傳輸線的寬度為5密爾,且波形圖中橫坐標表示訊號傳輸時間,縱坐標表示阻抗值,其中,在時間20.95ns至21.4ns之間為高速訊號經過電容時的阻抗變化。這是由於電容焊盤的寬度遠大於傳輸線的寬度,特徵阻抗在傳輸線和電容焊盤之間發生了突變,從而使高速訊號從高阻抗路徑進入到低阻路徑。由於阻抗的不匹配,高速訊號會產生反射,影響訊號完整性。In high-speed circuits, in order to eliminate the influence of the DC signal on the reference level of the receiving end, the capacitor is often used to isolate the DC signal from the high-speed signal and to couple the AC. A common method is to connect the capacitor directly to the signal line. The capacitor reference layer is a complete plane, and the return signal can be directly reflowed from the reference layer below the capacitor. Please refer to the time domain reflection waveform diagram of FIG. 1 , which is a signal simulation of a capacitor of 0402 package. The pad width is 20 mils during simulation, the width of the transmission line is 5 mils, and the abscissa indicates the signal in the waveform diagram. The transmission time, the ordinate represents the impedance value, wherein the impedance changes when the high-speed signal passes through the capacitor between 20.95 ns and 21.4 ns. This is because the width of the capacitor pad is much larger than the width of the transmission line, and the characteristic impedance is abruptly changed between the transmission line and the capacitor pad, so that the high-speed signal enters the low-impedance path from the high-impedance path. Due to the impedance mismatch, high-speed signals can cause reflections that affect signal integrity.
鑒於以上內容,有必要提供一種印刷電路板,可儘量滿足傳輸線和電容焊盤之間阻抗匹配,使高速訊號傳輸時儘量避免產生反射現象,從而提高高速訊號的完整性。In view of the above, it is necessary to provide a printed circuit board that satisfies the impedance matching between the transmission line and the capacitor pad as much as possible, so as to avoid reflection phenomenon when transmitting high-speed signals, thereby improving the integrity of the high-speed signal.
一種印刷電路板,包括一介質層及一設置在該介質層下方的參考層,該介質層上設置有傳輸線及連接該傳輸線的用於焊接一電子元件的焊盤,該參考層上對應該電子元件的位置開設有一週邊輪廓呈平滑曲線的挖空區域,該挖空區域呈中心對稱,其中心對應該電子元件的中心,該挖空區域的垂直於該兩段傳輸線方向的最長距離的長度為: ,其中為該焊盤的寬度;為該兩段傳輸線的寬度;T為該焊盤的厚度。A printed circuit board comprising a dielectric layer and a reference layer disposed under the dielectric layer, the dielectric layer being provided with a transmission line and a pad for soldering an electronic component connected to the transmission line, the reference layer corresponding to the electron The position of the component is provided with a hollowed out area with a smooth curved contour. The hollowed out area is centrally symmetrical, and its center corresponds to the center of the electronic component. The length of the hollowed out area perpendicular to the length of the two sections of the transmission line is : ,among them The width of the pad; The width of the two transmission lines; T is the thickness of the pad.
上述印刷電路板透過增加在其參考層上對應該焊盤的位置開設有一週邊輪廓呈平滑曲線的挖空區域來增加該焊盤的阻抗來儘量匹配該傳輸線的阻抗,從而大大減少了該印刷電路板上傳輸訊號時產生的反射現象,進而提高了訊號的完整性。The printed circuit board increases the impedance of the pad by maximizing the impedance of the pad by increasing the impedance of the pad by adding a hollowed out area with a smooth outline of the peripheral profile on the reference layer corresponding to the pad, thereby greatly reducing the impedance of the printed circuit. The reflection phenomenon generated when the signal is transmitted on the board, thereby improving the integrity of the signal.
請一併參考圖2及圖3,本發明印刷電路板1的較佳實施方式包括一介質層10及一設置在該介質層10下方的參考層20。該介質層10上設有兩段傳輸線12、13及兩個分別連接該兩段傳輸線12及13的焊盤14及15。該兩焊盤14及15用於焊接一電子元件如一電容30。該參考層20為流經該兩段傳輸線12、13及該電容30的高速訊號提供回流路經。該參考層20上對應該電容30的位置處開設有一挖空區域22,該挖空區域22的中心對應該電容30的中心,且其週邊輪廓呈平滑曲線以避免產生反射現象,在本實施方式中,該挖空區域22為橢圓形的挖空區域。Referring to FIG. 2 and FIG. 3 together, a preferred embodiment of the printed circuit board 1 of the present invention includes a dielectric layer 10 and a reference layer 20 disposed under the dielectric layer 10. The dielectric layer 10 is provided with two sections of transmission lines 12, 13 and two pads 14 and 15 respectively connecting the two sections of transmission lines 12 and 13. The two pads 14 and 15 are used to solder an electronic component such as a capacitor 30. The reference layer 20 provides a return path for the high speed signals flowing through the two sections of transmission lines 12, 13 and the capacitor 30. A hollowed out area 22 is defined in the reference layer 20 at a position corresponding to the capacitor 30. The center of the hollowed out area 22 corresponds to the center of the capacitor 30, and the peripheral contour thereof has a smooth curve to avoid a reflection phenomenon. In this embodiment, The hollowed out area 22 is an elliptical hollowed out area.
在高速訊號傳輸時為了消除直流訊號對訊號接收端參考電平的影響,將該電容30焊接在該兩焊盤14及15上來進行隔離直流,耦合交流。由於該參考層20對應該電容30的位置處開設有該挖空區域22,則使高速訊號回流經過該挖空區域22處時沿著該挖空區域22的橢圓形周邊傳輸,這樣增加了訊號回流路徑的長度(見回流路徑24),根據增大訊號的返回路徑,阻抗會增大的特性原理,該焊盤14的阻抗增加,當其增加到可以匹配該傳輸線12的阻抗時,即該焊盤14的阻抗等於該傳輸線12阻抗時,該訊號傳輸不會發生反射現象,從而可以保持高速訊號的完整性。In order to eliminate the influence of the DC signal on the reference level of the signal receiving end during high-speed signal transmission, the capacitor 30 is soldered to the two pads 14 and 15 for isolated DC and coupled to communicate. Since the reference layer 20 is provided with the hollowed-out area 22 at the position corresponding to the capacitor 30, the high-speed signal is transmitted back through the hollowed-out area of the hollowed-out area 22 when the high-speed signal is recirculated, thereby increasing the signal. The length of the return path (see the return path 24), the impedance of the pad 14 increases according to the characteristic principle of increasing the return path of the signal, and when it is increased to match the impedance of the transmission line 12, When the impedance of the pad 14 is equal to the impedance of the transmission line 12, the signal transmission does not reflect, so that the integrity of the high-speed signal can be maintained.
請一併參考圖4及圖1,為了提高高速訊號的完整性,應儘量保持該傳輸線12與該焊盤14的阻抗匹配。根據微帶線的阻抗Referring to FIG. 4 and FIG. 1 together, in order to improve the integrity of the high-speed signal, the impedance of the transmission line 12 and the pad 14 should be kept as close as possible. According to the impedance of the microstrip line
計算公式:,為了使,即,也即,其中為焊盤14的阻抗,為傳輸線的阻抗,H1假定該焊盤14底部到其下方參考層的距離;H為該兩傳輸線12及13到其下方參考層20的距離,即該介質層10的厚度;T為該焊盤14的厚度;為該兩焊盤14及15整體的寬度;為該傳輸線12的寬度。而H1與該挖空區域22大小有直接關係,假設,其中為一係數,為該橢圓形挖空區域22沿垂直於該傳輸線12及13方向的短軸的長度。由此得到:透過仿真得到,故得到:假設,其中為該橢圓形挖空區域22沿該傳輸線12及13方向的長軸的長度。透過仿真得到。透過長度及即可確定該橢圓形挖空區域22的尺寸。Calculation formula: ,because , which is , ie ,among them For the impedance of pad 14, For the impedance of the transmission line, H1 assumes the distance from the bottom of the pad 14 to the underlying reference layer; H is the distance between the two transmission lines 12 and 13 to the underlying reference layer 20, ie the thickness of the dielectric layer 10; T is the pad Thickness of 14; The width of the two pads 14 and 15 as a whole; Is the width of the transmission line 12. H1 is directly related to the size of the hollowed out area 22, assuming ,among them As a coefficient, The length of the elliptical hollowed out region 22 along the minor axis perpendicular to the direction of the transmission lines 12 and 13. This gives you: Obtained through simulation So get: Hypothesis ,among them The length of the major axis of the elliptical hollowed out region 22 along the direction of the transmission lines 12 and 13. Obtained through simulation . Through length and The size of the elliptical hollowed out area 22 can be determined.
請繼續參考圖5,其為本發明印刷電路板的時域反射波形圖,其為以0402封裝的電容為例做高速訊號仿真,仿真時該兩焊盤14及15整體的寬度為20密爾,該兩傳輸線12及13的寬度為5密爾,該挖空區域22垂直於該傳輸線12及13方向的短軸的長度W1及沿該兩傳輸線12及13方向的長軸的長度分別為30密爾及51密爾,且波形圖中橫坐標表示訊號傳輸時間T(ns),縱坐標表示阻抗值Z0(ohm),其中,在時間20.95ns至21.4ns之間為高速訊號經過該電容30時的阻抗變化。從圖5中可以看到,特徵阻抗曲線40在傳輸線和電容焊盤之間僅有不到1歐姆的變化,相較於圖1,圖5本發明印刷電路板上高速訊號經過該電容30時並未發生突變,而只是微小變化,從而表明該焊盤14的阻抗與該兩傳輸線12及13的阻抗近乎匹配,從而大大減少了反射現象,進而提高了訊號的完整性。Please refer to FIG. 5 , which is a time domain reflection waveform diagram of the printed circuit board of the present invention. The high frequency signal simulation is performed by using a capacitor of 0402 package as an example. The width of the two pads 14 and 15 as a whole is 20 mils during simulation. The widths of the two transmission lines 12 and 13 are 5 mils, and the length W1 of the hollow area 22 perpendicular to the transmission line 12 and 13 and the length of the long axis along the two transmission lines 12 and 13 are 30 respectively. Mill and 51 mil, and the abscissa in the waveform diagram represents the signal transmission time T (ns), and the ordinate represents the impedance value Z0 (ohm), wherein the high-speed signal passes through the capacitor 30 between time 20.95 ns and 21.4 ns. The impedance change at the time. As can be seen from FIG. 5, the characteristic impedance curve 40 has a variation of less than 1 ohm between the transmission line and the capacitor pad. Compared with FIG. 1, FIG. 5 shows that the high-speed signal on the printed circuit board of the present invention passes through the capacitor 30. No mutation occurs, but only a small change, indicating that the impedance of the pad 14 closely matches the impedance of the two transmission lines 12 and 13, thereby greatly reducing the reflection phenomenon, thereby improving the signal integrity.
綜上所述,本發明符合發明專利要件,爰依法提出專利申請。惟,以上所述者僅為本發明之較佳實施例,舉凡熟悉本案技藝之人士,在爰依本發明精神所作之等效修飾或變化,皆應涵蓋於以下之申請專利範圍內。In summary, the present invention complies with the requirements of the invention patent and submits a patent application according to law. The above description is only the preferred embodiment of the present invention, and equivalent modifications or variations made by those skilled in the art will be included in the following claims.
1‧‧‧印刷電路板1‧‧‧Printed circuit board
10‧‧‧介質層10‧‧‧ dielectric layer
12、13‧‧‧傳輸線12, 13‧‧‧ transmission line
14、15‧‧‧焊盤14, 15‧‧‧ pads
20‧‧‧參考層20‧‧‧ reference layer
22‧‧‧挖空區域22‧‧‧Knockout area
24‧‧‧回流路徑24‧‧‧Return path
30‧‧‧電容30‧‧‧ Capacitance
圖1係習知的印刷電路板的時域反射波形圖。Figure 1 is a diagram showing the time domain reflection waveform of a conventional printed circuit board.
圖2係本發明印刷電路板的較佳實施方式的立體示意圖。2 is a perspective view of a preferred embodiment of a printed circuit board of the present invention.
圖3係本發明印刷電路板較佳實施方式的參考層的俯視圖。3 is a top plan view of a reference layer of a preferred embodiment of the printed circuit board of the present invention.
圖4係本發明印刷電路板較佳實施方式的縱截面示意圖。4 is a schematic longitudinal cross-sectional view showing a preferred embodiment of the printed circuit board of the present invention.
圖5係本發明印刷電路板較佳實施方式的時域反射波形圖。Figure 5 is a time domain reflectance waveform diagram of a preferred embodiment of the printed circuit board of the present invention.
1‧‧‧印刷電路板 1‧‧‧Printed circuit board
10‧‧‧介質層 10‧‧‧ dielectric layer
12、13‧‧‧傳輸線 12, 13‧‧‧ transmission line
14、15‧‧‧焊盤 14, 15‧‧‧ pads
20‧‧‧參考層 20‧‧‧ reference layer
22‧‧‧挖空區域 22‧‧‧Knockout area
24‧‧‧回流路徑 24‧‧‧Return path
30‧‧‧電容 30‧‧‧ Capacitance
Claims (5)
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TW98143479A TWI439188B (en) | 2009-12-17 | 2009-12-17 | Printed circuit board |
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TW98143479A TWI439188B (en) | 2009-12-17 | 2009-12-17 | Printed circuit board |
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TW201124002A TW201124002A (en) | 2011-07-01 |
TWI439188B true TWI439188B (en) | 2014-05-21 |
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