TWI438877B - Heat dissipation plate and semiconductor device - Google Patents

Heat dissipation plate and semiconductor device Download PDF

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TWI438877B
TWI438877B TW097124724A TW97124724A TWI438877B TW I438877 B TWI438877 B TW I438877B TW 097124724 A TW097124724 A TW 097124724A TW 97124724 A TW97124724 A TW 97124724A TW I438877 B TWI438877 B TW I438877B
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layer
laminate
layers
copper
semiconductor
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TW097124724A
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TW200917435A (en
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Tsuyoshi Hasegawa
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Toshiba Kk
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3736—Metallic materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
    • Y10T156/10—Methods of surface bonding and/or assembly therefor
    • Y10T156/1052—Methods of surface bonding and/or assembly therefor with cutting, punching, tearing or severing
    • Y10T156/1056—Perforating lamina
    • Y10T156/1057—Subsequent to assembly of laminae

Description

半導體封裝用散熱板及半導體裝置Heat sink and semiconductor device for semiconductor package 相關申請案之相互參照Cross-reference to related applications

本案係基於且請求2007年7月5日申請之先前日本專利申請案編號2007-177636的優先權利益，在此以引用方式將其全文併入本文。The present application is based on and claims the benefit of priority of Japanese Patent Application No. 2007- 177 636 filed on

本發明係有關一種收納配置例如各種LSI、IC等半導體元件之半導體封裝用散熱板及使用該散熱板之半導體裝置。The present invention relates to a heat sink for semiconductor package in which semiconductor elements such as various LSIs and ICs are housed, and a semiconductor device using the heat sink.

一般而言，半導體元件係由於大容量化而使發熱量增大，為了維持半導體元件的性能，半導體封裝用散熱板係採用了各種構造。In general, the semiconductor element has a large amount of heat generation due to the increase in capacity, and the heat dissipation plate for semiconductor package has various structures in order to maintain the performance of the semiconductor element.

例如在日本特開2001-144237號公報中，揭示了將比金屬材料熱傳導特性優的石墨板與金屬薄板組合之石墨板層疊熱傳導體，並提出使用該石墨板層疊熱傳導體進行電子機器的散熱。For example, Japanese Laid-Open Patent Publication No. 2001-144237 discloses a graphite plate-laminated heat conductor in which a graphite plate and a metal plate having superior heat conduction characteristics of a metal material are laminated, and it is proposed to use the graphite plate-laminated heat conductor to dissipate heat from an electronic device.

然而，上述石墨板層疊熱傳導體雖然可以得到高的熱傳導特性，但是例如在構成搭載了陶瓷基板之半導體封裝的情況下，由於其熱膨脹係數與陶瓷基板的熱膨脹係數大不相同，而有根據熱變形而使與陶瓷基板的接合部位有所損傷之問題。However, although the above-described graphite sheet-laminated heat conductor can obtain high heat conduction characteristics, for example, in the case of constituting a semiconductor package on which a ceramic substrate is mounted, the coefficient of thermal expansion is greatly different from the coefficient of thermal expansion of the ceramic substrate, and is thermally deformed. There is a problem that the joint portion with the ceramic substrate is damaged.

一方面，在日本專利第3862737號公報中，也提出交互層疊銅層與鉬層，使熱膨脹係數接近構成半導體元件之陶瓷基板的熱膨脹係數之散熱基板用材料。On the other hand, Japanese Patent No. 3862737 proposes a material for a heat dissipation substrate in which a copper layer and a molybdenum layer are alternately laminated so that a thermal expansion coefficient is close to a thermal expansion coefficient of a ceramic substrate constituting a semiconductor element.

然而，在上述散熱基板用材料中，無法滿足熱傳導效率。隨著半導體元件的大容量化，進一步增加熱量時，有所謂若不增加散熱面積，要對應熱量增加為困難的問題。However, in the above material for a heat dissipation substrate, heat conduction efficiency cannot be satisfied. When the capacity of the semiconductor element is increased and the amount of heat is further increased, there is a problem that it is difficult to increase the amount of heat unless the heat dissipation area is increased.

本發明係以提供能夠實現高熱傳導效率，且能夠實現熱膨脹係數的調整之半導體封裝用散熱板及半導體裝置為目的。The present invention has an object of providing a heat dissipation plate for a semiconductor package and a semiconductor device capable of achieving high heat conduction efficiency and capable of adjusting a thermal expansion coefficient.

若是根據本發明的實施例，係提供具有：銅層、石墨層與鉬層的層疊體；及設置在層疊體兩面的外部銅層之半導體封裝用散熱板。According to an embodiment of the present invention, a laminate having a copper layer, a graphite layer and a molybdenum layer, and a heat dissipation plate for a semiconductor package provided on both surfaces of the laminate are provided.

又若是根據本發明之另一實施例，係提供具有：銅層、石墨層與鉬層的層疊體；及設置在層疊體兩面的外部銅層之半導體封裝用散熱板；搭載在散熱板上之利用半導體晶片與基板所形成之半導體元件；具有開口，且設置外部連接端子之框材，並設置在散熱板上，包圍半導體元件之框材；黏附框材的開口之蓋體；及電氣連接半導體元件與外部連接端子之導體的半導體裝置。According to still another embodiment of the present invention, there is provided a laminate comprising: a copper layer, a graphite layer and a molybdenum layer; and a heat dissipation plate for semiconductor package provided on the outer copper layer on both surfaces of the laminate; and mounted on the heat dissipation plate a semiconductor element formed by using a semiconductor wafer and a substrate; a frame material having an opening and provided with an external connection terminal, and disposed on the heat dissipation plate to surround the frame member of the semiconductor element; a cover body for adhering the opening of the frame material; and an electrical connection semiconductor A semiconductor device in which a component and a conductor of an external connection terminal are connected.

針對關於實施例的半導體封裝用散熱板及半導體裝置，參照圖面加以詳細說明。The heat sink and the semiconductor device for a semiconductor package according to the embodiment will be described in detail with reference to the drawings.

實施例的半導體封裝用散熱板係具有：銅層、石墨層與鉬層的層疊體；及設置在層疊體兩面的外部銅層。The heat dissipation plate for semiconductor package of the embodiment has a copper layer, a laminate of a graphite layer and a molybdenum layer, and an outer copper layer provided on both surfaces of the laminate.

第1及2圖係顯示關於第1實施例之半導體封裝用散熱板。第1圖係為顯示搭載半導體元件14的散熱板10。散熱板10係具有在其兩面有外部銅層11a、11b之平板狀的板構造。在外部銅層11a、11b之間係將依序層疊例如在面方向熱傳導性優之石墨12、鉬層13、石墨層12、在面垂直方向熱傳導性優之銅層11c、石墨層12、銅層11c的6層並進行二次重疊，再將石墨層12、鉬層13及石墨層12依序層疊在第二次的銅層11c。換言之，使銅層11c、石墨層12及鉬層13相互層疊複數層，並在其層疊體的兩面16a、16b設置外部銅層11a、11b。Figs. 1 and 2 show a heat dissipation plate for a semiconductor package according to the first embodiment. The first drawing shows the heat sink 10 on which the semiconductor element 14 is mounted. The heat sink 10 has a flat plate structure having external copper layers 11a and 11b on both surfaces thereof. Between the outer copper layers 11a and 11b, for example, the graphite 12 having excellent thermal conductivity in the surface direction, the molybdenum layer 13, the graphite layer 12, and the copper layer 11c excellent in thermal conductivity in the surface perpendicular direction, the graphite layer 12, and copper are laminated. The six layers of the layer 11c are double-overlapped, and the graphite layer 12, the molybdenum layer 13, and the graphite layer 12 are sequentially laminated on the second copper layer 11c. In other words, the copper layer 11c, the graphite layer 12, and the molybdenum layer 13 are laminated on each other, and the outer copper layers 11a and 11b are provided on both surfaces 16a and 16b of the laminate.

又散熱板10係在層疊體的周緣具有例如層疊銅層11d與鉬層13a而構成的框部15，並覆蓋石墨層12的端部。Further, the heat dissipation plate 10 has, for example, a frame portion 15 formed by laminating a copper layer 11d and a molybdenum layer 13a on the periphery of the laminate, and covers the end portion of the graphite layer 12.

將銅層11c、石墨層12、鉬層13、外部銅層11a、11b如上述所示重複層疊並加壓加溫處理，使其一體化，例如使銅層11c為0.1mm、石墨層12為0.1mm、鉬層12為0.02mm、外部銅層11a、11b為0.2mm加以層疊。The copper layer 11c, the graphite layer 12, the molybdenum layer 13, and the outer copper layers 11a and 11b are repeatedly laminated as described above and pressurized and heated to be integrated, for example, the copper layer 11c is 0.1 mm, and the graphite layer 12 is 0.1 mm, the molybdenum layer 12 was 0.02 mm, and the outer copper layers 11a and 11b were 0.2 mm.

鉬層13的配合量係以使散熱板10的物性接近構成搭載在散熱板10的半導體元件14之例如陶瓷基板的熱膨脹 係數之方式加以選定。又外部銅層11a、11b及銅層11c的厚度總合與石墨層12的厚度總合之比係約略設定為1。The amount of the molybdenum layer 13 is such that the physical properties of the heat dissipation plate 10 are close to the thermal expansion of, for example, a ceramic substrate constituting the semiconductor element 14 mounted on the heat dissipation plate 10. The way the coefficients are chosen. Further, the ratio of the total thickness of the outer copper layers 11a and 11b and the copper layer 11c to the total thickness of the graphite layer 12 is approximately set to 1.

又在層疊體周緣，於外部銅層11a、11b之間重複層疊銅層及鉬層並藉由進行加壓加溫處理，層疊銅層11d及鉬層13a，設置框部15。Further, on the periphery of the laminate, a copper layer and a molybdenum layer are repeatedly laminated between the outer copper layers 11a and 11b, and the copper layer 11d and the molybdenum layer 13a are laminated by pressurization and heating, and the frame portion 15 is provided.

其次，說明本發明之實施例的半導體裝置。若是根據本發明之第1實施例的半導體裝置，其係具有：有銅層、石墨層與鉬層的層疊體、及設置在層疊體兩面的銅層之散熱板；搭載在散熱板上之利用半導體晶片與基板所形成之半導體元件；具有開口且設置外部連接端子的框材，並設置在散熱板上包圍半導體元件的框材；黏附框材的開口之蓋材；及電性連接半導體元件與外部連接端子之導體。Next, a semiconductor device according to an embodiment of the present invention will be described. According to the semiconductor device of the first embodiment of the present invention, there is provided a copper layer, a laminate of a graphite layer and a molybdenum layer, and a heat dissipation plate provided on both surfaces of the laminate; and the use of the heat sink plate a semiconductor element formed by a semiconductor wafer and a substrate; a frame material having an opening and provided with an external connection terminal; and a frame material surrounding the semiconductor element disposed on the heat dissipation plate; a cover material for adhering the opening of the frame material; and electrically connecting the semiconductor element and The conductor of the external connection terminal.

藉由在第1及2圖所示之實施例的散熱板10之外部銅層11a、11b及框部15的周圍設置電鍍金等未圖示的處理層，並在該處理層上搭載半導體元件14，能夠製造第3及4圖所示之半導體裝置20。A processing layer (not shown) such as gold plating is provided around the outer copper layers 11a and 11b and the frame portion 15 of the heat dissipation plate 10 of the embodiment shown in FIGS. 1 and 2, and a semiconductor element is mounted on the processing layer. 14. The semiconductor device 20 shown in FIGS. 3 and 4 can be manufactured.

如第3圖所示，在第1實施例的半導體裝置中，在散熱板10的一方外部銅層(未圖示)上安裝構成半導體封裝的框材21。在框材21係於其側壁突出設置外部連接端子22。再者，在該框材21內的散熱板10上係使用焊接等接合搭載半導體元件14之陶瓷基板141及半導體晶片142。陶瓷基板141及半導體晶片142係在相互之間及與上述外部連接端子22之間利用導線24電性連接。再者，在框材21上係黏附構成半導體封裝的蓋體23，形成如第4圖 所示之半導體裝置20。As shown in FIG. 3, in the semiconductor device of the first embodiment, the frame member 21 constituting the semiconductor package is mounted on one of the outer copper layers (not shown) of the heat dissipation plate 10. The external connection terminal 22 is protruded from the frame member 21 to the side wall thereof. Further, the ceramic substrate 141 on which the semiconductor element 14 is mounted and the semiconductor wafer 142 are bonded to the heat dissipation plate 10 in the frame member 21 by soldering or the like. The ceramic substrate 141 and the semiconductor wafer 142 are electrically connected to each other and to the external connection terminal 22 by a wire 24. Furthermore, the cover 23 constituting the semiconductor package is adhered to the frame member 21, and is formed as shown in FIG. The semiconductor device 20 is shown.

若是根據第1實施例的半導體封裝用散熱板及第1實施例的半導體裝置，散熱板10係使其熱膨脹係數藉由鉬層13的作用而接近半導體元件14之陶瓷基板141的物性。在使用焊接等接合陶瓷基板141時，即使有由於加熱及冷卻接合部所發生的溫度變化，因為藉由使散熱板的熱膨脹係數與陶瓷基板141的熱膨脹係數接近，其熱變形係與陶瓷基板141的熱變形大約相同，因此不會使陶瓷基板141裂開等，能夠維持高精度的接合。According to the semiconductor package heat sink of the first embodiment and the semiconductor device of the first embodiment, the heat dissipation plate 10 has a thermal expansion coefficient close to the physical properties of the ceramic substrate 141 of the semiconductor element 14 by the action of the molybdenum layer 13. When the ceramic substrate 141 is joined by soldering or the like, even if there is a temperature change due to heating and cooling of the joint portion, since the thermal expansion coefficient of the heat dissipation plate is close to the thermal expansion coefficient of the ceramic substrate 141, the thermal deformation is performed with the ceramic substrate 141. Since the thermal deformation is approximately the same, the ceramic substrate 141 is not cracked or the like, and high-precision bonding can be maintained.

又利用同樣的作用，即使在半導體裝置20的外周圍等發生溫度變化，也不會使半導體元件14的陶瓷基板141裂開等，能夠維持高精度的接合。By the same effect, even if a temperature change occurs in the outer periphery of the semiconductor device 20 or the like, the ceramic substrate 141 of the semiconductor element 14 is not cracked or the like, and high-precision bonding can be maintained.

進一步，當驅動搭載在散熱板10之一方外部銅層11a上的半導體晶片142而發熱時，其熱能係首先熱移送至外部銅層11a，經由外部銅層11a熱移送至陶瓷基板141。 此時，由於散熱板10係藉由使其熱膨脹係數與陶瓷基板141接近，而與陶瓷基板141的熱變形大約相同，因為不會使陶瓷基板141裂開等，能夠維持相互間的高精度接合。Further, when the semiconductor wafer 142 mounted on the outer copper layer 11a of the heat dissipation plate 10 is driven to generate heat, the thermal energy is first thermally transferred to the outer copper layer 11a, and thermally transferred to the ceramic substrate 141 via the outer copper layer 11a. At this time, since the heat dissipation plate 10 has a thermal expansion coefficient close to that of the ceramic substrate 141, the thermal deformation of the ceramic substrate 141 is approximately the same, and since the ceramic substrate 141 is not cracked or the like, high-precision bonding can be maintained. .

同時，熱移送至散熱板10的熱能係利用該外部銅層11a、11b及框部15有效地傳導至面垂直方向的同時，而且利用該石墨層12有效地傳導至面方向，因此能夠均勻地被熱傳導至散熱板10整體。藉此，散熱板10上的半導體元件14係在與其外部銅層11a之間維持高精度的搭載 之狀態下，能夠進行高效率的熱控制。At the same time, the thermal energy transferred to the heat dissipation plate 10 is efficiently conducted to the surface perpendicular direction by the outer copper layers 11a, 11b and the frame portion 15, and is effectively conducted to the surface direction by the graphite layer 12, thereby enabling uniformity It is thermally conducted to the entire heat dissipation plate 10. Thereby, the semiconductor element 14 on the heat dissipation plate 10 is mounted with high precision between the external copper layer 11a and the external copper layer 11a. In this state, high-efficiency heat control can be performed.

藉此，能夠實現防止由於搭載在散熱板10上之半導體元件14的熱變形所造成的損傷，而且能夠實現具有熱傳導性能優的散熱板10，達到半導體元件14之高效率的熱控制。Thereby, it is possible to prevent damage due to thermal deformation of the semiconductor element 14 mounted on the heat dissipation plate 10, and it is possible to realize the heat dissipation plate 10 having excellent heat conduction performance and to achieve high-efficiency thermal control of the semiconductor element 14.

本發明係不限於上述實施例，例如第5、6、7、8、9、10圖所示，也可以構成為半導體封裝用散熱板10a、10b、10c、10d、10e、10f，同樣也可以得到有效的效果。又能夠使用此等散熱板，製作半導體裝置。但是，在該第5至10圖所示之實施例中，針對與上述第1至4圖相同的部分係附予相同的符號而省略其詳細說明。The present invention is not limited to the above embodiment, and for example, as shown in FIGS. 5, 6, 7, 8, 9, and 10, the heat dissipation plates 10a, 10b, 10c, 10d, 10e, and 10f for semiconductor packages may be configured as well. Get effective results. Further, a semiconductor device can be fabricated using these heat dissipation plates. However, in the embodiment shown in the fifth to tenth embodiments, the same portions as those in the first to fourth embodiments are denoted by the same reference numerals, and the detailed description thereof will be omitted.

在第5圖係顯示第2實施例之半導體封裝用散熱板。Fig. 5 shows a heat dissipation plate for a semiconductor package of a second embodiment.

散熱板10a係層疊銅層11e形成設置在周緣的框部15a，並與第1圖所示之實施例1相同，交互層疊外部銅層11a、11b、銅層11c、石墨層12、及鉬層13構成其他部份。The heat dissipation plate 10a is formed by laminating the copper layer 11e on the peripheral edge of the frame portion 15a, and is the same as the first embodiment shown in Fig. 1, and the outer copper layers 11a and 11b, the copper layer 11c, the graphite layer 12, and the molybdenum layer are alternately laminated. 13 constitutes the other part.

在第6圖係顯示第3實施例之半導體封裝用散熱板。Fig. 6 shows a heat dissipation plate for a semiconductor package of a third embodiment.

散熱板10b係利用銅形成設置在周緣的框部15b，該框部15b係與外部銅層11b一體成形。The heat sink 10b is formed of a frame portion 15b provided on the periphery by copper, and the frame portion 15b is integrally formed with the outer copper layer 11b.

在第7圖係顯示第4實施例之半導體封裝用散熱板。Fig. 7 shows a heat dissipation plate for a semiconductor package of a fourth embodiment.

散熱板10c係在搭載半導體晶片142的區域101，於外部銅層11a、11b之間具有半導體晶片搭載部101a，半導體晶片搭載部101a係沒有設置石墨層12，層疊銅層11c及鉬層13加以形成。在半導體晶片搭載部101a中， 利用銅層11c及鉬層13，能夠取得面垂直方向之熱傳導性能的提升，更進一步得到良好的熱傳導率。藉此，在半導體元件14之中來自發熱量集中之半導體晶片142的熱能係能夠更進一步有效熱傳導至面垂直方向。The heat sink 10c is in the region 101 on which the semiconductor wafer 142 is mounted, and has a semiconductor wafer mounting portion 101a between the outer copper layers 11a and 11b. The semiconductor wafer mounting portion 101a is not provided with the graphite layer 12, and the copper layer 11c and the molybdenum layer 13 are laminated. form. In the semiconductor wafer mounting portion 101a, By using the copper layer 11c and the molybdenum layer 13, the heat conductivity in the vertical direction of the surface can be improved, and a good thermal conductivity can be obtained. Thereby, the thermal energy from the semiconductor wafer 142 in which the heat is concentrated among the semiconductor elements 14 can be further efficiently conducted to the surface perpendicular direction.

在第8圖係顯示第5實施例之半導體封裝用散熱板。Fig. 8 shows a heat dissipation plate for a semiconductor package of a fifth embodiment.

散熱板10d係沒有設置石墨層12及鉬層13，僅層疊銅層11c形成半導體晶片搭載部101b。藉此，取得半導體晶片搭載部101b中的面垂直方向之熱傳導性能的提升，更進一步得到良好的熱傳導率。在半導體元件14之中來自發熱量集中之半導體晶片142的熱能係能夠更進一步有效熱傳導至面垂直方向。The graphite layer 12 and the molybdenum layer 13 are not provided in the heat dissipation plate 10d, and only the copper layer 11c is laminated to form the semiconductor wafer mounting portion 101b. Thereby, the thermal conductivity of the surface in the semiconductor wafer mounting portion 101b in the vertical direction is improved, and a good thermal conductivity is further obtained. Among the semiconductor elements 14, the thermal energy from the semiconductor wafer 142 where heat is concentrated can be further efficiently conducted to the surface perpendicular direction.

在第9圖係顯示第6實施例之半導體封裝用散熱板。Fig. 9 shows a heat dissipation plate for a semiconductor package of a sixth embodiment.

散熱板10e係與上述第6圖所示之散熱板10b相同，僅利用銅形成設置在周緣的框部15b的同時，而且僅利用銅形成半導體晶片搭載部101c，該框部15b、半導體晶片搭載部101c、及外部銅層11b係為一體成形者。The heat sink 10e is the same as the heat sink 10b shown in Fig. 6, and the semiconductor wafer mounting portion 101c is formed only by copper, and the semiconductor wafer mounting portion 101c is mounted only by the copper frame portion 15b. The portion 101c and the outer copper layer 11b are integrally formed.

在第10圖係顯示第7實施例之半導體封裝用散熱板。Fig. 10 shows a heat dissipation plate for a semiconductor package of a seventh embodiment.

雖然在第1圖所示之第1實施例中係設置框部15，但是在該實施例中係為沒有設置框部15構成散熱板10f者。In the first embodiment shown in Fig. 1, the frame portion 15 is provided. However, in this embodiment, the frame portion 15 is not provided to constitute the heat dissipation plate 10f.

又在上述散熱板10c、10d、10e中，雖然是針對將半導體晶片搭載部101a、101b、101c設置為一處的情況加以說明，但是不限於此，也可以設置二處以上加以構成。In the above-described heat sinks 10c, 10d, and 10e, the semiconductor wafer mounting portions 101a, 101b, and 101c are provided in one place. However, the present invention is not limited thereto, and two or more positions may be provided.

在上述各實施例中，雖然是針對利用石墨層12挾裝鉬層13的情況加以說明，但是本發明係不限於此，也可以構成為挾裝在石墨層12與銅層11c之間、或外部銅層11a (11b)與銅層11c之間，或是利用銅層11c加以挾裝的方式層疊配置鉬層13。In each of the above embodiments, the case where the molybdenum layer 13 is deposited by the graphite layer 12 is described. However, the present invention is not limited thereto, and may be configured to be sandwiched between the graphite layer 12 and the copper layer 11c, or The molybdenum layer 13 is laminated between the outer copper layer 11a (11b) and the copper layer 11c or by the copper layer 11c.

由此處所揭示之發明說明書及實務的考量，對於熟悉此技藝者而言本發明的其他具體例或修飾將顯而易見。吾人試圖將說明書及示範具體例僅視為例子，而本發明的真實範圍及精神係由以下得知。Other specific examples and modifications of the present invention will be apparent to those skilled in the art from this disclosure. The specification and exemplary embodiments are to be considered as illustrative only, and the true scope and spirit of the invention are

10‧‧‧散熱板10‧‧‧heating plate

10a‧‧‧散熱板10a‧‧‧heat plate

10b‧‧‧散熱板10b‧‧‧heat plate

10c‧‧‧散熱板10c‧‧‧heat plate

10d‧‧‧散熱板10d‧‧‧heating plate

10e‧‧‧散熱板10e‧‧‧heat plate

10f‧‧‧散熱板10f‧‧‧heat plate

11a‧‧‧外部銅層11a‧‧‧External copper layer

11b‧‧‧外部銅層11b‧‧‧External copper layer

11c‧‧‧銅層11c‧‧‧ copper layer

11d‧‧‧銅層11d‧‧‧ copper layer

11e‧‧‧銅層11e‧‧‧ copper layer

12‧‧‧石墨層12‧‧‧ graphite layer

13‧‧‧鉬層13‧‧‧ molybdenum layer

13a‧‧‧鉬層13a‧‧‧Molybdenum layer

14‧‧‧半導體元件14‧‧‧Semiconductor components

15‧‧‧框部15‧‧‧ Frame Department

15a‧‧‧框部15a‧‧‧ Frame Department

15b‧‧‧框部15b‧‧‧ Frame Department

20‧‧‧半導體裝置20‧‧‧Semiconductor device

21‧‧‧框材21‧‧‧ frame materials

22‧‧‧外部連接端子22‧‧‧External connection terminal

23‧‧‧蓋體23‧‧‧ Cover

24‧‧‧導線24‧‧‧Wire

101‧‧‧搭載半導體晶片的區域101‧‧‧A region equipped with semiconductor wafers

101a‧‧‧半導體晶片搭載部101a‧‧‧Semiconductor Wafer Mounting Department

101b‧‧‧半導體晶片搭載部101b‧‧‧Semiconductor Wafer Mounting Department

101c‧‧‧半導體晶片搭載部101c‧‧‧Semiconductor Wafer Mounting Department

141‧‧‧陶瓷基板141‧‧‧Ceramic substrate

142‧‧‧半導體晶片142‧‧‧Semiconductor wafer

第1圖係為顯示有關第1實施例之半導體封裝用散熱板的主要部位之剖面圖。Fig. 1 is a cross-sectional view showing a main part of a heat sink for semiconductor package according to the first embodiment.

第2圖係為顯示第1圖的散熱板之平面圖。Fig. 2 is a plan view showing the heat sink of Fig. 1.

第3圖係為顯示分解第1實施例的半導體裝置之分解圖。Fig. 3 is an exploded view showing the semiconductor device in which the first embodiment is exploded.

第4圖係為顯示第3圖的半導體裝置之外觀構造的立體圖。Fig. 4 is a perspective view showing an appearance structure of the semiconductor device of Fig. 3.

第5圖係為顯示有關第2實施例之半導體封裝用散熱板的主要部位之剖面圖。Fig. 5 is a cross-sectional view showing a main part of a heat dissipation plate for a semiconductor package according to a second embodiment.

第6圖係為顯示有關第3實施例之半導體封裝用散熱板的主要部位之剖面圖。Fig. 6 is a cross-sectional view showing a main part of a heat sink for semiconductor package according to a third embodiment.

第7圖係為剖面顯示有關第4實施例之半導體封裝用散熱板的主要部位之剖面圖。Fig. 7 is a cross-sectional view showing a main portion of a heat sink for semiconductor package according to a fourth embodiment in a cross section.

第8圖係為剖面顯示有關第5實施例之半導體封裝用散熱板的主要部位之剖面圖。Fig. 8 is a cross-sectional view showing a main portion of a heat sink for semiconductor package according to a fifth embodiment.

第9圖係為剖面顯示有關第6實施例之半導體封裝用散熱板的主要部位之剖面圖。Fig. 9 is a cross-sectional view showing the main part of the heat sink for semiconductor package according to the sixth embodiment in a cross section.

第10圖係為剖面顯示有關第7實施例之半導體封裝用散熱板的主要部位之剖面圖。Fig. 10 is a cross-sectional view showing a main portion of a heat sink for semiconductor package according to a seventh embodiment in a cross section.

10‧‧‧散熱板10‧‧‧heating plate

11a‧‧‧外部銅層11a‧‧‧External copper layer

11b‧‧‧外部銅層11b‧‧‧External copper layer

11c‧‧‧銅層11c‧‧‧ copper layer

11d‧‧‧銅層11d‧‧‧ copper layer

12‧‧‧石墨層12‧‧‧ graphite layer

13‧‧‧鉬層13‧‧‧ molybdenum layer

13a‧‧‧鉬層13a‧‧‧Molybdenum layer

14‧‧‧半導體元件14‧‧‧Semiconductor components

15‧‧‧框部15‧‧‧ Frame Department

Claims (8)

一種半導體封裝用散熱板，其特徵為具有：層疊體，係由銅層、石墨層、及鉬層(Mo)以不重疊同種之層的方式被層疊複數層而成，而且上述鉬層之層疊數較上述石墨層之層疊數為少的層疊體；外部銅層，係於上述層疊體之兩面以重疊層的方式被設置；及框部，係設於上述層疊體之上述兩面以外之周緣，由銅形成，而且與一方之面的上述外部銅層被一體形成。 A heat dissipation plate for a semiconductor package, comprising: a laminate obtained by laminating a plurality of layers of a copper layer, a graphite layer, and a molybdenum layer (Mo) so as not to overlap a layer of the same type, and laminating the molybdenum layer a laminate having a smaller number of layers than the graphite layer; an outer copper layer provided on the both surfaces of the laminate in an overlapping layer; and a frame portion on a periphery other than the both surfaces of the laminate; It is formed of copper and is formed integrally with the outer copper layer on one side. 如申請專利範圍第1項之半導體封裝用散熱板，其中，進一步在搭載半導體元件的區域，於上述兩面之外部銅層之間具有半導體晶片搭載部。 The heat sink for semiconductor package according to claim 1, wherein the semiconductor wafer mounting portion is provided between the outer copper layers on the both surfaces in the region in which the semiconductor element is mounted. 如申請專利範圍第2項之半導體封裝用散熱板，其中，上述半導體晶片搭載部係具有由複數銅層層疊而成的層疊體。 The heat sink for semiconductor package according to the second aspect of the invention, wherein the semiconductor wafer mounting portion has a laminate in which a plurality of copper layers are laminated. 如申請專利範圍第2項之半導體封裝用散熱板，其中，上述半導體晶片搭載部係利用銅加以形成，上述半導體晶片搭載部係與一方面的上述外部銅層及上述框部一體設置。 The heat sink for semiconductor package according to claim 2, wherein the semiconductor wafer mounting portion is formed of copper, and the semiconductor wafer mounting portion is integrally provided with the outer copper layer and the frame portion on the one hand. 如申請專利範圍第2項之半導體封裝用散熱板，其中，半導體晶片搭載部係具有複數銅層與複數鉬層層疊而成的層疊體。 The heat sink for semiconductor package according to the second aspect of the invention, wherein the semiconductor wafer mounting portion has a laminate in which a plurality of copper layers and a plurality of molybdenum layers are laminated. 如申請專利範圍第1項之之半導體封裝用散熱板，其中，上述外部銅層的厚度係較上述層疊體的銅層之厚 度更厚。 The heat dissipation plate for semiconductor package according to the first aspect of the invention, wherein the thickness of the outer copper layer is thicker than the copper layer of the laminate More thick. 如申請專利範圍第1項之半導體封裝用散熱板，其中，上述層疊體具有複數銅層及複數石墨層，上述外部銅層及上述層疊體之上述複數銅層的厚度總合、與上述複數石墨層的厚度總合之比約略為1。 The heat sink for semiconductor package according to claim 1, wherein the laminate has a plurality of copper layers and a plurality of graphite layers, and the outer copper layer and the plurality of copper layers of the laminate are combined in thickness and the plurality of graphite layers. The ratio of the total thickness of the layers is approximately one. 一種半導體裝置，其特徵為具有：散熱板，其具有：層疊體，係由銅層、石墨層、及鉬層以不重疊同種之層的方式被層疊複數層而成，而且上述鉬層之層疊數較上述石墨層之層疊數為少的層疊體；外部銅層，係於上述層疊體之兩面以重疊層的方式被設置；及框部，係設於上述層疊體之上述兩面以外之周緣，由銅形成，而且與一方之面的上述外部銅層被一體形成；搭載在散熱板上之利用半導體晶片及基板形成之半導體元件；具有開口、且設置外部連接端子的框材，並設置在上述散熱板上，包圍上述半導體元件之框材；黏附上述框材的開口之蓋體；及電氣連接半導體元件與外部連接端子之導體。 A semiconductor device comprising: a heat dissipation plate having a laminate in which a copper layer, a graphite layer, and a molybdenum layer are laminated without overlapping layers of the same type, and the layer of the molybdenum layer is laminated a laminate having a smaller number of layers than the graphite layer; an outer copper layer provided on the both surfaces of the laminate in an overlapping layer; and a frame portion on a periphery other than the both surfaces of the laminate; It is formed of copper, and is formed integrally with the outer copper layer on one surface; a semiconductor element formed of a semiconductor wafer and a substrate mounted on a heat dissipation plate; and a frame material having an opening and an external connection terminal; a heat dissipation plate, a frame material surrounding the semiconductor element; a cover body to which the opening of the frame material is adhered; and a conductor electrically connecting the semiconductor element and the external connection terminal.
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