TWI438601B - Bandgap circuit and start circuit thereof - Google Patents

Description

Bandgap circuit and its starting circuit

The present invention relates to a bandgap circuit and its startup circuit, and more particularly to a bandgap circuit having a startup function and its startup circuit.

Figure 1 is a circuit diagram of a conventional bandgap circuit. As shown in FIG. 1, the bandgap circuit 100 includes a startup circuit 110 and a reference current generation circuit 120. Wherein the reference current generating circuit 120 comprises a plurality of current mirrors 121 to 124, 121 to 124 and a current mirror to each other and having a splicing bias node N ₁₁ ~ N _14. In addition, the current mirrors 121-124 are electrically connected to the ground through the bipolar transistors BT11~BT12 and the resistor R1. Thereby, the reference current generating circuit 120 maps the permeable P channel transistors MT11 and MT12 with a reference current IR ₁ proportional to absolute temperature (PTAT).

In order to cause the reference current generating circuit 120 to normally provide the reference current IR ₁ , the starting circuit 110 is used to cause the reference current generating circuit 120 to be out of the zero-current state. In operation, the control terminal of the switch SW11 receives the node voltage VN ₁ from the bias node N ₁₄ , and the switch SW12 determines whether to provide the startup voltage VT ₁ to the bias node N ₁₂ according to its conduction state. However, in the initial stage in which the power supply voltage VD ₁ gradually rises from the ground voltage, the node voltage VN ₁ approaches the ground voltage, and thus the switch SW11 cannot be turned on.

At this time, the switch SW12 will receive the power supply voltage VD ₁ through the load unit 111, thereby turning on both ends thereof and generating the starting voltage VT ₁ to the bias node N ₁₂ . Accordingly, the reference current generating circuit 120 may be based on _a zero current state from the starting voltage VT. Thereafter, the node voltage VN ₁ gradually rises as the power supply voltage VD ₁ rises, thereby turning on the switch SW11. At this time, the switch SW12 will receive the ground voltage, and thus cannot turn on both ends. As such, the startup circuit 110 will stop outputting the startup voltage VT ₁ and the reference current generation circuit 120 will normally supply the reference current IR ₁ .

However, when the on/off time of the system is too short, that is, when the power supply voltage VD ₁ is quickly switched, the residual charge will be largely concentrated at the bias nodes N ₁₁ to N ₁₄ . As a result, at the initial stage of system startup, the switch SW11 will not be normally turned off, and the switch SW12 will not be normally turned on. In other words, when the power supply voltage VD ₁ is quickly switched, the startup circuit 110 cannot operate normally, thereby causing the reference current generation circuit 120 to fail to be out of the zero current state.

The present invention provides a startup circuit that utilizes a reset control circuit to provide a discharge path to conduct residual charge accumulated at a bias node to a ground terminal. Thereby, although the power supply voltage is quickly switched, the startup circuit can still normally supply the startup voltage.

The present invention provides a bandgap circuit having a start-up circuit, and the start-up circuit can normally provide a start-up voltage under rapid switching of a power supply voltage. Thereby, the bandgap circuit will operate normally under the driving of the starting circuit.

The present invention provides a startup circuit that utilizes a startup voltage to activate a reference circuit, wherein the reference circuit includes a first bias node and a second bias node. The startup circuit includes a load unit, a first switch, a second switch, and a reset control circuit. Wherein the first end of the load unit receives the power supply voltage. The first end of the first switch is electrically connected to the second end of the load unit, the second end of the first switch is electrically connected to the ground, and the control end of the first switch receives the node voltage from the first bias node. In addition, the first end of the second switch is electrically connected to the second biasing node, the second end of the second switch is electrically connected to the ground, and the control end of the second switch is electrically connected to the second end of the load unit. In operation, the second switch determines whether to provide a starting voltage to the second biasing node depending on its conduction state. In addition, the reset control circuit provides a discharge path between the control terminal and the ground terminal of the first switch, and conducts the discharge path according to the power supply voltage during the period when the power supply voltage is less than the threshold voltage.

In an embodiment of the invention, the reset control circuit includes a third switch and a controller. Wherein, the third switch provides a discharge path. In addition, the first end of the third switch is electrically connected to the control end of the first switch, and the second end of the third switch is electrically connected to the ground end. The controller is electrically connected to the control end of the third switch. During a period when the power supply voltage is less than the threshold voltage, the controller increases the level of the reset voltage according to the power supply voltage to turn on the third switch. In addition, when the power supply voltage is greater than the threshold voltage, the controller switches the reset voltage to the ground voltage to not turn on the third switch.

The invention proposes a bandgap circuit comprising a reference circuit and a starting circuit. The reference circuit includes a first bias node and a second bias node. The startup circuit activates the reference circuit using the startup voltage and includes a load unit, a first switch, a second switch, and a reset control circuit. The first end of the load unit receives the supply voltage. The first switch is electrically connected between the second end of the load unit and the ground, and the control end of the first switch receives the node voltage from the first bias node. In addition, the first end of the second switch is electrically connected to the second biasing node, the second end of the second switch is electrically connected to the ground, and the control end of the second switch is electrically connected to the second end of the load unit. In operation, the second switch determines whether to provide a starting voltage to the second biasing node depending on its conduction state. In addition, the reset control circuit provides a discharge path between the control terminal and the ground terminal of the first switch, and conducts the discharge path according to the power supply voltage during the period when the power supply voltage is less than the threshold voltage.

Based on the above, the present invention utilizes a reset control circuit to provide a discharge path, and the reset control circuit conducts a discharge path during a period in which the power supply voltage is less than the threshold voltage. Thereby, in the initial stage of the system startup, the residual charge accumulated at the bias node will be conducted to the ground through the discharge path. In this way, although the power supply voltage is quickly switched, the startup circuit can still normally supply the startup voltage to the reference circuit, thereby causing the reference circuit to operate normally.

The above described features and advantages of the present invention will be more apparent from the following description.

2 is a circuit diagram of a bandgap circuit in accordance with an embodiment of the present invention. Referring to FIG. 2, the bandgap reference circuit 200 includes a startup circuit 210 and a reference circuit 220. The reference circuit 220 can be, for example, a reference current generating circuit or a reference voltage generating circuit. Herein, the present embodiment is described by taking a reference current generating circuit as an example. Therefore, the reference circuit 220 includes current mirrors 221-224, resistor R2, bipolar transistors BT21 and BT22, and P channel transistors MT21 and MT22.

The current mirrors 221 to 224 are overlapped with each other and have biasing nodes N ₂₁ to N ₂₄ . In addition, the current mirror 221 is configured to receive the power supply voltage VD ₂ . One end of the current mirror 224 is electrically connected to the grounding terminal through the resistor R2 and the bipolar transistor BT21, and the other end of the current mirror 224 is electrically connected to the ground through the bipolar transistor BT22. Thereby, the reference current generating circuit 220 maps the permeable P-channel transistors MT21 and MT22 with a reference current IR ₂ proportional to the absolute temperature.

With continued reference to FIG. 2, the startup circuit 210 includes a load unit 211, a switch 212, a switch 213, and a reset control circuit 214. The first end of the load unit 211 receives the power supply voltage VD ₂ . The first terminal of the second terminal of the switch 212 is electrically connected to the load unit 211, a second terminal of switch 212 is electrically connected to the ground terminal, the control terminal of the switch 212 receives the voltage VN ₂ from the node N ₂₄ of the bias node. In addition, the first end of the switch 213 is electrically connected to the bias node N ₂₂ , the second end of the switch 213 is electrically connected to the ground end, and the control end of the switch 213 is electrically connected to the second end of the load unit 211 . Furthermore, the reset control circuit 214 is electrically connected to the control terminal of the switch 212.

In operation, in order to prevent a large amount of residual charge from accumulating at the bias node N ₂₄ in response to rapid switching of the power supply voltage VD ₂ , the reset control circuit 214 provides a discharge path between the control terminal and the ground terminal of the switch 212. Further, during a period in which the power supply voltage VD _{2 is} less than a threshold voltage, the reset control circuit 214 turns on the discharge path in accordance with the power supply voltage VD ₂ . As a result, although the power supply voltage VD _{2 is} rapidly switched, the residual charge accumulated at the bias node N ₂₄ will be discharged to the ground through the discharge path provided by the reset control circuit 214.

In other words, at the initial stage of system startup, that is, at the beginning of the gradual rise of the power supply voltage VD ₂ from the ground voltage, the node voltage VN ₂ at the bias node N ₂₄ will respond to the discharge path provided by the reset control circuit 214. Approaching the ground voltage. In this way, at the beginning of the system startup, it will be ensured that the switch 212 is maintained in a non-conducting state. In contrast, since the switch 212 is not turned on, the switch 213 receives the power supply voltage VD ₂ through the load-carrying unit 211, thereby turning on both ends thereof. At this time, the level of the first end of the switch 213 will be switched to the ground voltage. In other words, the switch 213 can provide a startup voltage VT ₂ (eg, a ground voltage) to the bias node N ₂₂ through its first terminal. Thereby, the reference current generating circuit 220 will be able to deviate from the zero current state in accordance with the starting voltage VT ₂ .

Further, when the power supply voltage VD ₂ gradually rises and exceeds the threshold voltage, the reset control circuit 214 will turn off the discharge path. At this time, the node voltage VN ₂ will gradually rise as the power supply voltage VD ₂ rises, and the switch 212 is turned on. As the switch 212 is turned on, the switch 213 will receive the ground voltage and thus will not be able to conduct its ends. When the switch 213 is not conducting, the switch 213 will not be able to provide the starting voltage VT ₂ to the biasing node N ₂₂ . Thereby, the reference current generating circuit 220 will normally supply the reference current IR ₂ .

Looking further, the reset control circuit 214 includes a switch 201 and a controller 202. The first end of the switch 201 is electrically connected to the control end of the switch 212, and the second end of the switch 201 is electrically connected to the ground end. The controller 202 is electrically connected to the control end of the switch 201. In addition, FIG. 3 is a voltage timing diagram according to an embodiment of the present invention. Hereinafter, the detailed operation of the reset control circuit 214 will be described with reference to FIGS. 2 and 3.

In operation, the switch 201 is used to provide a discharge path, and the controller 202 is used to control whether the discharge path is turned on or not. Wherein, during the period when the power supply voltage VD _{2 is} less than the threshold voltage V _TH , the controller 202 increases the level of the reset voltage V _ST according to the power supply voltage VD ₂ . For example, as shown in FIG. 3, in the period T3, the controller 202 may refer to the power source voltage VD ₂ is gradually increased level of the reset voltage V _ST. Thereby, the switch 201 can be turned on both ends according to the reset voltage V _{ST to} form a discharge path. On the other hand, when the power supply voltage VD _{2 is} greater than the threshold voltage V _TH , the controller 202 will switch the reset voltage V _ST to the ground voltage. Thereby, the switch 201 will not be able to conduct its both ends, thereby turning off the discharge path.

Further, in the present embodiment, the switch 201, the switch 212, and the switch 213 are each formed of an N-channel transistor. For example, the switch 201 is composed of an N-channel transistor MN21, wherein the drain of the N-channel transistor MN21 is electrically connected to the control end of the switch 212, and the source of the N-channel transistor MN21 is electrically connected to the ground, and the N-channel is electrically connected. The gate of the crystal MN21 is electrically connected to the controller 202. In addition, the switch 212 is composed of an N-channel transistor MN22, wherein the drain of the N-channel transistor MN22 is electrically connected to the second end of the load unit 211, and the source of the N-channel transistor MN22 is electrically connected to the ground, N The gate of the channel transistor MN22 is electrically connected to the bias node N ₂₄ .

Furthermore, the switch 213 is composed of an N-channel transistor MN23, wherein the drain of the N-channel transistor MN23 is electrically connected to the bias node N ₂₂ , and the source of the N-channel transistor MN23 is electrically connected to the ground, N-channel The gate of the transistor MN23 is electrically connected to the second end of the load unit 211. Further, in the present embodiment, the load unit 211 includes a plurality of P channel transistors MP21 to MP24. Wherein the gate of the P-channel transistor MP21 ~ MP24 is connected to the ground terminal, and the P-channel transistor MP21 ~ MP24 connected in series to each other between a first supply voltage terminal and the switch 212 VD _2.

In summary, the present invention utilizes a reset control circuit to provide a discharge path and conduct a discharge path during periods when the supply voltage is less than the threshold voltage. Thereby, in the initial stage of the system startup, the residual charge accumulated at the bias node will be conducted to the ground through the discharge path. In this way, although the power supply voltage is quickly switched, the startup circuit can still normally supply the startup voltage to the reference circuit, thereby causing the reference circuit to operate normally.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100, 200. . . Bandgap reference circuit

120. . . Reference current generating circuit

220. . . Reference circuit

121~124, 221~224. . . Current mirror

R1, R2. . . resistance

BT11, BT12, BT21, BT22. . . Double carrier transistor

MT11, MT12, MT21, MT22, MP21~MP24. . . P channel transistor

N ₁₁ ~ N ₁₄ , N ₂₁ ~ N ₂₄ . . . Bias node

IR ₁ , IR ₂ . . . Reference current

110, 210. . . Startup circuit

111, 211. . . Load unit

SW11, SW12, 212, 213, 201. . . switch

214. . . Reset control circuit

202. . . Controller

MN21~MN23. . . N-channel transistor

VD ₁ , VD ₂ . . . voltage

VT ₁ , VT ₂ . . . Starting voltage

VN ₁ , VN ₂ . . . Node voltage

V _ST . . . Reset voltage

T3. . . period

V _TH . . . Threshold voltage

Figure 1 is a circuit diagram of a conventional bandgap circuit.

2 is a circuit diagram of a bandgap circuit in accordance with an embodiment of the present invention.

3 is a voltage timing diagram in accordance with an embodiment of the present invention.

200. . . Bandgap reference circuit

220. . . Reference circuit

221~224. . . Current mirror

R2. . . resistance

BT21, BT22. . . Double carrier transistor

MT21, MT22, MP21~MP24. . . P channel transistor

N ₂₁ ~N ₂₄ . . . Bias node

IR ₂ . . . Reference current

210. . . Startup circuit

211. . . Load unit

212, 213, 201. . . switch

214. . . Reset control circuit

202. . . Controller

MN21~MN23. . . N-channel transistor

VD ₂ . . . voltage

VT ₂ . . . Starting voltage

VN ₂ . . . Node voltage

V _ST . . . Reset voltage

Claims (15)

A startup circuit starts a reference circuit by using a startup voltage, wherein the reference circuit includes a first bias node and a second bias node, and the startup circuit includes: a load unit, the first end of which receives a power supply a first switch, the first end of which is electrically connected to the second end of the load unit, the second end of the first switch is electrically connected to a ground, and the control end of the first switch receives the first a node voltage of the biasing node; a second switch having a first end electrically connected to the second biasing node, a second end of the second switch electrically connected to the grounding end, and a control end of the second switch Electrically connecting to the second end of the load unit, wherein the second switch determines whether to provide the starting voltage to the second bias node according to its conduction state; and a reset control circuit at the control end of the first switch A discharge path is provided between the ground and the ground, and the discharge path is turned on according to the power voltage during the period when the power voltage is less than a threshold voltage. The start-up circuit of claim 1, wherein the reset control circuit comprises: a third switch, the discharge path is provided, wherein the first end of the third switch is electrically connected to the control end of the first switch The second end of the third switch is electrically connected to the ground end; and a controller electrically connected to the control end of the third switch, wherein the controller is configured according to the power supply voltage being less than the threshold voltage The power supply voltage is increased by a reset voltage level to turn on the third switch, and when the power supply voltage is greater than the threshold voltage, the controller switches the reset voltage to a ground voltage to not turn on the third switch . The start-up circuit of claim 2, wherein the third switch is formed by a first N-channel transistor, and the drain of the first N-channel transistor is electrically connected to the control end of the first switch The source of the first N-channel transistor is electrically connected to the ground, and the gate of the first N-channel transistor is electrically connected to the controller. The start-up circuit of claim 1, wherein the load unit comprises: a plurality of P-channel transistors, the gates of the P-channel transistors are electrically connected to the ground, and the P-channel transistors The power supply voltage is connected in series with the first end of the first switch. The starter circuit of claim 1, wherein the first switch is formed by a second N-channel transistor, and the second end of the second N-channel transistor is electrically connected to the second end of the load unit. The source of the second N-channel transistor is electrically connected to the ground, and the gate of the second N-channel transistor is electrically connected to the first bias node. The start-up circuit of claim 1, wherein the second switch is formed by a third N-channel transistor, and the drain of the third N-channel transistor is electrically connected to the second bias node, The source of the third N-channel transistor is electrically connected to the ground, and the gate of the third N-channel transistor is electrically connected to the second end of the load unit. The start-up circuit of claim 1, wherein the reference circuit is a reference current generating circuit or a reference voltage generating circuit. A bandgap circuit includes: a reference circuit including a first bias node and a second bias node; and a start circuit that activates the reference circuit by using a startup voltage, and the startup circuit includes: a load unit The first end of the first switch is electrically connected to the second end of the load unit, and the second end of the first switch is electrically connected to a ground end, the first switch The control terminal receives a node voltage from the first bias node; a second switch has a first end electrically connected to the second bias node, and a second end of the second switch is electrically connected to the ground The control end of the second switch is electrically connected to the second end of the load unit, wherein the second switch determines whether to provide the starting voltage to the second bias node according to its conduction state; and a reset control circuit, A discharge path is provided between the control end of the first switch and the ground, and the discharge path is turned on according to the power supply voltage during the period when the power supply voltage is less than a threshold voltage. The bandgap circuit of claim 8, wherein the reset control circuit comprises: a third switch providing the discharge path, wherein the first end of the third switch is electrically connected to the control of the first switch The second end of the third switch is electrically connected to the ground end; and a controller is electrically connected to the control end of the third switch, wherein the controller is based on the power supply voltage being less than the threshold voltage The power supply voltage is increased by a reset voltage level to turn on the third switch, and when the power supply voltage is greater than the threshold voltage, the controller switches the reset voltage to a ground voltage to not turn on the third switch. The bandgap circuit of claim 9, wherein the third switch is formed by a first N-channel transistor, and the first pole of the first N-channel transistor is electrically connected to the control of the first switch The source of the first N-channel transistor is electrically connected to the ground, and the gate of the first N-channel transistor is electrically connected to the controller. The bandgap circuit of claim 8, wherein the load unit comprises: a plurality of P-channel transistors, the gates of the P-channel transistors are electrically connected to the ground, and the P-channels are electrically The crystals are connected in series between the supply voltage and the first end of the first switch. The bandgap circuit of claim 8, wherein the first switch is formed by a second N-channel transistor, and the second N-channel transistor is electrically connected to the second of the load unit. The source of the second N-channel transistor is electrically connected to the ground, and the gate of the second N-channel transistor is electrically connected to the first bias node. The bandgap circuit of claim 8, wherein the second switch is formed by a third N-channel transistor, and the drain of the third N-channel transistor is electrically connected to the second bias node. The source of the third N-channel transistor is electrically connected to the ground, and the gate of the third N-channel transistor is electrically connected to the second end of the load unit. The bandgap circuit of claim 8, wherein the reference circuit is a reference current generating circuit or a reference voltage generating circuit. The bandgap circuit of claim 8, wherein the reference circuit further comprises: a first to a fourth current mirror, wherein the first to fourth current mirrors are overlapped with each other, the first current mirror Receiving the power voltage, the second current mirror has the first bias node, the fourth current mirror has the second bias node; a resistor; and a first and a second bipolar transistor, wherein the One end of the fourth current mirror is electrically connected to the first dual carrier transistor through the resistor, and the other end of the fourth current mirror is electrically connected to the ground through the second dual carrier transistor. .