TWI437684B - Power transistor device with electrostatic discharge protection and low dropout regulator using same - Google Patents

Description

Power transistor component with electrostatic protection and low dropout regulator using the power transistor component

The present invention relates to a power transistor component having electrostatic protection and a low dropout regulator using the power transistor component, wherein an electrostatic discharge path is provided for the power transistor component.

Figure 1 shows a schematic diagram of a prior art low dropout regulator. The low dropout regulator (LDO) 100 is a linear regulator that converts the input voltage Vin into an output voltage Vout. The basic structure is as follows. The figure shows an error amplifying circuit 10 and a power transistor element 20. The error amplifying circuit 10 receives an output voltage sampling signal, and the output voltage sampling signal is between the output voltage and the ground potential, and has series resistors R1 and R2, which are taken on R2. The partial voltage is used as the output voltage sampling signal. The error amplifying circuit 10 compares the output voltage sampling signal with the reference signal Vref, and amplifies the comparison result to the gate of the PMOSFET in the power transistor element 20 to control the conduction between the source and the drain, that is, the input voltage Vin and Conversion parameter between output voltages Vout. The cross-sectional view of the PMOSFET in the power transistor element 20 is shown in Fig. 2. From the cross-sectional view, the PMOSFET is located on the P-substrate (P-sub) 21, and adjacent high-pressure N-type well regions are formed below the upper surface. (NW) 23 and high-pressure P-type well (PW) 24; and forming a plurality of shallow trench isolation (STI) 25, N+ body pole 26, P+ source 27, and P+汲 in the two well regions a pole 29; and a gate 28 formed above the upper surface.

Continuing to refer to Figures 1 and 2, the output of the power transistor component 20 is the contact pad 1, which may come into contact with the human body or contact various electric fields in the application and test environment, and thus may accumulate charge and generate static electricity. The voltage or direct contact with the high static voltage, when the static voltage is higher than the range that the power transistor element 20 can tolerate, is discharged through the discharge path, one of which may be as shown by the broken line in FIG. 2, which will cause Operation of the circuit is incorrect or the component is seriously damaged.

In view of the above, the present invention is directed to the above-mentioned deficiencies of the prior art, and provides a power transistor element and a low-dropout voltage regulator with electrostatic protection.

One of the objects of the present invention is to provide a power transistor element having electrostatic protection.

Another object of the present invention is to provide a low dropout voltage regulator having electrostatic protection using the above power transistor elements.

In order to achieve the above object, the present invention provides a power transistor component with electrostatic protection, comprising: a PMOSFET having a source and a drain electrically connected to a voltage input terminal and a voltage output terminal, respectively; And an electrostatic protection component electrically connected to the voltage input terminal and the voltage output terminal, and providing an electrostatic discharge path through which the static voltage of the output terminal can be discharged to protect the PMOSFET; wherein the voltage output terminal A contact pad that can be powered to a load circuit.

In the above-mentioned electrostatic protection power transistor component, the electrostatic protection component may further comprise a deep N-well (deep NW) or an N-type buried layer (NBL).

In one embodiment, the ESD protection element may include an NPN transistor, an emitter and a collector are electrically connected to the voltage output end and the voltage input end, respectively, and the base is controlled by the Voltage output.

In another embodiment, the ESD protection element may comprise an N-type metal oxide semiconductor (NMOS) field effect transistor with a drain and a source respectively The voltage output terminal and the voltage input terminal are electrically connected, and the gate is grounded or controlled by the voltage output terminal.

In another embodiment, the ESD protection component may include a silicon controlled rectifier (SCR), and a cathode and an anode are electrically connected to the voltage output terminal and the voltage input terminal respectively. The pole is controlled by this voltage output.

In another aspect, the present invention provides a low-dropout voltage regulator with electrostatic protection for converting an input voltage of an input terminal into an output voltage of an output terminal, the low-voltage voltage regulator with electrostatic protection. The device includes: an error amplifying circuit, generating an error amplification signal according to an output voltage sampling signal and a reference signal, wherein the output voltage sampling signal is sampled from the output voltage; and a power transistor component, including: a PMOSFET, The source and the drain are electrically connected to the input end and the output end respectively; and the ESD protection component is electrically connected to the input end and the output end, and provides an electrostatic discharge path, so that the static voltage at the output end can be passed through The electrostatic discharge path is discharged to protect the P-type metal oxide semiconductor field effect transistor; wherein the output end is a contact pad, and the power supply is connected to a load circuit.

In the above-mentioned electrostatic protection low-dropout voltage regulator, the static protection component may further comprise a deep N-type well region or an N-type buried layer.

In the above-mentioned electrostatic protection low-dropout voltage regulator, the static protection component may comprise an NPN transistor, the emitter and the collector being electrically connected to the output terminal and the input terminal, respectively, and the base is controlled by the output terminal.

In the above-mentioned electrostatic protection low-dropout voltage regulator, the static protection component may comprise an N-type metal oxide semiconductor field effect transistor, wherein the drain and the source are electrically connected to the output terminal and the input terminal, respectively, and the gate is grounded. Or controlled by the output.

In the above-mentioned electrostatic protection low-dropout voltage regulator, the static protection component may include a voltage-controlled rectifier, and the cathode and the anode are electrically connected to the output terminal and the input terminal, respectively, and the gate is controlled by the output terminal.

The purpose, technical content, features and effects achieved by the present invention will be more readily understood by the detailed description of the embodiments.

The main technical idea of the present invention is to form a discharge path using an N-type channel element to remove the electrostatic problem of the P-type power transistor.

Referring to Figures 3 and 4, a first embodiment of the present invention is shown. As shown in FIG. 3, the LDO 200 includes an error amplifying circuit 10 and a power transistor element 30. Unlike the prior art, the power transistor element 30 includes an electrostatic protection element 2 in addition to the PMOSFET. The source and the drain of the PMOSFET are electrically connected to the voltage input terminal Vin and the voltage output terminal Vout, respectively. In this embodiment, the electrostatic protection component 2 includes an NPN bipolar junction transistor (BJT). The emitter 31 and the collector 32 are electrically connected to the voltage output terminal Vout and the voltage input terminal Vin, respectively, and the base thereof is also controlled by the voltage output terminal Vout. When the voltage output terminal Vout is in contact with the pad 1 When the static voltage is applied, it can be discharged through the collector-to-emitter path of the static protection element NPNBJT to protect the PMOSFET.

Referring to Figure 4, a cross-sectional view of the power transistor component 30 in the first embodiment is shown. Wherein, compared with the prior art, the embodiment further includes a deep N-type well region (deep NW) or an N-type buried layer (NBL) 22, which is formed on the P-type substrate 21 and the high-pressure N-type well region and the high-pressure P-type well Between the regions 24, the power transistor element 30 and the P-type substrate 21 are isolated; in addition, the N+-type emitter 31, the N+-type collector 32, and the P+-type base of the NPNBJT are respectively shown in the figure. Figure 4 also shows the symbols of NPNBJT and resistors to show the circuit relationships represented by the various regions in the cross-section. In addition, the dotted line with an arrow represents the discharge path when the contact pad 1 is exposed to the static voltage. Since the NPNBJT additionally provides a static voltage discharge path, it does not cause functional influence and structural damage to the PMOSFET.

Figures 5 and 6 show a second embodiment of the present invention. As shown, the LDO 300 includes an error amplifying circuit 10 and a power transistor element 40, which includes a PMOSFET and an ESD element 2. In this embodiment, the ESD protection device 2 includes an NMOSFET, and a drain 42 and a source 43 are electrically connected to the voltage output terminal Vout and the voltage input terminal Vin, respectively, and the gate 44 thereof is also Controlled by the voltage output terminal Vout, when the contact pad 1 of the voltage output terminal Vout contacts the static voltage, the path from the drain 42 to the source 43 can be discharged via the parasitic NPNBJT of the static protection element NMOSFET to protect the PMOSFET.

Referring to Figure 6, a cross-sectional view of the power transistor 40 in the second embodiment is shown. Wherein, a deep N-type well region or an N-type buried layer 22 is formed between the P-type substrate 21 and the high-pressure N-type well region and the high-voltage P-type well region 24 to isolate the power transistor element 40 and the P-type substrate 21; In addition, the N+ type drain electrode 42, the N+ type source electrode 43, and the gate electrode 44 of the NMOSFET are respectively as shown in the figure. Figure 6 also shows the parasitic NPNBJT of the NMOSFET, showing the circuit relationships represented by the various regions in the cross-sectional view. In addition, the dotted line with the arrow represents the discharge path when the contact pad 1 is exposed to the static voltage. Since the parasitic NPNBJT of the NMOSFET provides a discharge path of the static voltage, it does not cause a functional influence on the PMOSFET and the structural damage.

Fig. 7 and Fig. 8 show a third embodiment of the present invention. As shown, the LDO 400 includes an error amplifying circuit 10 and a power transistor element 50, and the power transistor element 50 includes a PMOSFET and an ESD element 2. In this embodiment, the ESD protection device 2 includes an NMOSFET having a drain 52 and a source 53 electrically connected to the voltage output terminal Vout and the voltage input terminal Vin, respectively, and the gate 54 thereof. Electrically connected to the ground potential, when the contact pad 1 of the voltage output terminal Vout contacts the static voltage, the path from the drain 52 to the source 53 can be discharged via the parasitic NPNBJT of the static protection element NMOSFET to protect the PMOSFET.

Referring to Figure 8, a cross-sectional view of the power transistor 50 in the third embodiment is shown. The deep N-type well region or the N-type buried layer 22 is formed between the P-type substrate 21 and the high-pressure N-type well region and the high-voltage P-type well region 24 to isolate the power transistor element 60 and the P-type substrate 21; In addition, the N+ type drain 52, the N+ type source 53, and the gate 54 of the NMOSFET are as shown in the figure, respectively. Figure 8 also shows the parasitic NPNBJT of the NMOSFET, showing the circuit relationships represented by the various regions in the cross-sectional view. In addition, the dotted line with the arrow represents the discharge path when the contact pad 1 is exposed to the static voltage. Since the parasitic NPNBJT of the NMOSFET provides a discharge path of the static voltage, it does not cause a functional influence on the PMOSFET and the structural damage.

Fig. 9 and Fig. 10 show a fourth embodiment of the present invention. As shown, the LDO 500 includes an error amplifying circuit 10 and a power transistor element 60, which includes a PMOSFET and an ESD element 2. In this embodiment, the ESD protection device 2 includes a silicon controlled rectifier (SCR), and a cathode 62 and an anode 63 are electrically connected to the voltage output terminal Vout and the voltage input terminal Vin, respectively. The gate is also connected in series with a resistor and electrically connected to the voltage output terminal Vout. When the contact pad 1 of the voltage output terminal Vout contacts the static voltage, the gate can be discharged through the path of the cathode 62 to the anode 63 of the electrostatic protection element SCR. Protect the PMOSFET.

Referring to FIG. 10, a cross-sectional view of the power transistor 60 in the fourth embodiment is shown. Wherein, a deep N-type well region or an N-type buried layer 22 is formed between the P-type substrate 21 and the high-pressure N-type well region and the high-voltage P-type well region 24 to isolate the power transistor element 50 and the P-type substrate 21; In addition, the cathode 62, the anode 63, and the gate of the SCR are respectively as shown in the figure. Figure 10 also shows the BJT composition symbol of the SCR, indicating the circuit relationship represented by each region in the cross-sectional view. In addition, the dotted line with an arrow represents the discharge path when the contact pad 1 is exposed to the static voltage. Since the cathode 62 to the anode 63 of the SCR further provides a static voltage discharge path, it does not have a functional influence on the PMOSFET. Structural damage.

11 shows another embodiment of power transistor component 30. Unlike FIG. 4, its PMOSFET and NPNBJT are separated from high voltage P-well region 24 by STI 25 and high pressure N-well region 23.

Figure 12 shows another embodiment of a power transistor component 40. Unlike Figure 6, its PMOSFET and NMOS are separated from the high voltage P-well region 24 by the STI 25 and the high voltage N-well region 23.

The power transistor element 50 of Fig. 8 can also be changed to a semiconductor structure similar to that of Fig. 12, as shown in Fig. 13.

Figure 14 shows another embodiment of a power transistor component 60, which differs from FIG. 10 in that its PMOSFET and SCR are separated from the high voltage P-well region 24 by STI 25 and high pressure N-well region 23.

The present invention has been described with reference to the preferred embodiments thereof, and the present invention is not intended to limit the scope of the present invention. In the same spirit of the invention, various equivalent changes can be conceived by those skilled in the art. For example, in the circuits of the various embodiments shown, components that do not affect the primary meaning of the signal, such as other switches, may be inserted; the shallow trench isolation region may be changed to a partial germanium oxide region or the like. All such modifications may be made in accordance with the teachings of the present invention, and the scope of the present invention should be construed to cover the above and other equivalents.

1. . . Contact pad

10. . . Error amplifier circuit

20, 30, 40, 50, 60. . . Power transistor component

twenty one. . . P-type substrate

twenty two. . . Deep N-type well or N-type buried layer

twenty three. . . High pressure N-type well area

twenty four. . . High pressure P type well area

25. . . Shallow trench insulation

26. . . Body pole

27. . . Source

28. . . Gate

29. . . Bungee

31. . . Emitter

32. . . Collector

42,52. . . Bungee

23‧‧‧High pressure N-well area

24‧‧‧High pressure P-well area

25‧‧‧Shallow trench insulation zone

26‧‧‧ body pole

27‧‧‧ source

28‧‧‧ gate

29‧‧‧汲polar

31‧‧‧ emitter

32‧‧‧ Collector

42,52‧‧‧汲

43,53‧‧‧ source

44,54‧‧‧ gate

62‧‧‧ cathode

63‧‧‧Anode

R1, R2‧‧‧ resistance

Vin‧‧‧Input voltage

Vout‧‧‧ output voltage

Vref‧‧‧ reference signal

100,200,300,400,500‧‧‧ Low dropout regulator

Figure 1 shows a schematic diagram of a prior art low dropout regulator.

Fig. 2 is a schematic cross-sectional view showing the structure of the power transistor element 20 of Fig. 1.

3 and 4 show a first embodiment of the present invention.

Figures 5 and 6 show a second embodiment of the present invention.

Fig. 7 and Fig. 8 show a third embodiment of the present invention.

Fig. 9 and Fig. 10 show a fourth embodiment of the present invention.

Figure 11 shows another embodiment of a power transistor component 30.

Figure 12 shows another embodiment of a power transistor component 40.

Figure 13 shows another embodiment of a power transistor component 50.

Figure 14 shows another embodiment of a power transistor component 60.

1. . . Contact pad

twenty one. . . P-type substrate

twenty two. . . Deep N-type well or N-type buried layer

twenty three. . . High pressure N-type well area

twenty four. . . High pressure P type well area

25. . . Shallow trench insulation

26. . . Body pole

27. . . Source

28. . . Gate

31. . . Emitter

32. . . Collector

Vin. . . Input voltage

Vout. . . The output voltage

Claims (8)

A power transistor component with electrostatic protection, comprising: a P-type metal oxide semiconductor (PMOS) field effect transistor (FET), the source and the drain are electrically connected to the drain a voltage input end and a voltage output end; and an ESD protection component, electrically connected to the voltage input end and the voltage output end, and providing an electrostatic discharge path, so that the static voltage of the output end can be discharged through the ESD path, Protecting the PMOSFET; wherein the voltage output end is a contact pad, and the power supply is connected to a load circuit; wherein the ESD protection component further comprises a deep N-well or an N-type buried layer (N) -type buried layer). The power transistor component with electrostatic protection according to claim 1, wherein the electrostatic protection component comprises an NPN bipolar junction transistor, and an emitter and a collector respectively and the voltage The output terminal and the voltage input terminal are electrically connected, and the base is controlled by the voltage output terminal. The power transistor component with electrostatic protection according to claim 1, wherein the electrostatic protection component comprises an N-type metal oxide semiconductor (NMOS) field effect transistor and a drain electrode thereof The drain and the source are electrically connected to the voltage output terminal and the voltage input terminal, respectively, and the gate is grounded or controlled by the voltage output terminal. The power transistor component with electrostatic protection according to claim 1, wherein the static electricity protection component comprises a silicon controlled rectifier (SCR), and a cathode and an anode respectively The voltage output terminal and the voltage input terminal are electrically connected, and the gate is controlled by the voltage output end. A low-voltage difference voltage regulator with electrostatic protection for converting an input voltage of an input terminal into an output voltage of an output terminal, the static-protection low-dropout voltage regulator comprising: an error amplifying circuit according to an output voltage The sampling signal and a reference signal generate an error amplification signal, wherein the output voltage sampling signal is sampled from the output voltage; and a power transistor component includes: a P-type metal oxide semiconductor (P-type metal oxide semiconductor, a PMOS) field effect transistor (FET) having a source and a drain electrically connected to the input terminal and the output terminal, respectively, a gate controlled by the error amplification signal; and an electrostatic protection component, and the input The terminal and the output are electrically connected, and an electrostatic discharge path is provided, so that the static voltage of the output terminal can be discharged through the electrostatic discharge path to protect the PMOSFET; wherein the output end is a contact pad, and the power supply can be connected to a load The circuit; wherein the ESD protection element further comprises a deep N-well or an N-type buried layer. The low voltage difference voltage regulator having static electricity protection according to claim 5, wherein the static electricity protection component comprises an NPN bipolar junction transistor, and an emitter and a collector respectively The output end and the input end are electrically connected, and the base is controlled by the output end. The low voltage difference regulator having static electricity protection according to claim 5, wherein the static protection component comprises an N-type metal oxide semiconductor (N-type metal oxide semiconductor, NMOS) field effect transistor, wherein a drain and a source are electrically connected to the voltage output terminal and the voltage input terminal, respectively, and the gate is grounded or controlled by the output terminal . The invention relates to a low-voltage difference regulator with electrostatic protection as claimed in claim 5, wherein the electrostatic protection component comprises a silicon controlled rectifier (SCR), and a cathode and an anode respectively The voltage output terminal and the voltage input terminal are electrically connected, and the gate is controlled by the output terminal.