201205766 六、發明說明： 【發明所屬之技術領域】 本發明係有關一種具有靜電防護之功率電晶體元件與使 用該功率電晶體元件之低壓差穩壓器，其中為該功率電晶體元 件提供了靜電放電路徑。 【先前技術】 第1圖顯示先前技術的低壓差穩壓器示意圖，低壓差穩墨 器(low dropout regulator，LDO) 100為一種線性穩壓器，用以將 輸入電壓Vin轉換為輸出電壓Vout，其基本結構如圖所示，包 含誤差放大電路10以及功率電晶體元件20，誤差放大電路 10接收輸出電壓取樣訊號’輸出電壓取樣訊號係輸出電壓與 接地電位之間，具有串聯電阻R1與R2，擷取R2上的分壓 作為輸出電壓取樣訊號。誤差放大電路1〇比較輸出電壓取樣 訊號與參考訊號Vref ’並將比較結果放大輸出至功率電晶體 元件20中PMOSFET之閘極’以控制源極與汲極間之導通程 度，也就是輸入電壓Vin與輸出電壓Vout間之轉換參數。功 率電晶體元件20中PMOSFET之結構剖面圖如第2圖所示， 從剖面圖視之’ PMOSFET位於P型基板(P_sub) 21上，於上 表面以下形成相鄰之高壓N型井區(NW) 23以及高壓！》型井 區(PW) 24 ;並於兩井區中形成複數淺溝槽絕緣區(shai_ trench isolation，STI) 25、N+本體極 26、P+源極 27、以及 p+ 及極29 ;以及於上表面以上形成閘極28。 請繼續參閱第1圖及第2圖’功率電晶體元件2〇之輸出 端為翻塾卜其可能接_人體，或於躺及職環境中 接觸到各種電場，因而可能會累積電荷而產生靜電壓或直接 201205766 接觸到高靜賴，當靜高於轉電綠 放電路徑放電，其中-個可能的放電： 如此將造成電路的操作錯誤或是嚴重 有鑑於此，本發明即針對上述先前技術之不足 具有靜電防護之裤電晶體元件與低壓差穩壓器。 【發明内容】 本發明目的之-在提供―種具有靜物護之功率電 兀仵。 本發明的另—目的在提供—種使用上述功率電晶體元件 而具有靜電防護之低壓差穩壓器。 為達上述之目的，就其中一個觀點言，本發明提一 種具有靜電防護之功率電晶體元件，包含：pmosfet:、 極與汲極分職連接於—電壓輸人端與—電壓輸出端丨以及 靜，P方護猶，與該電壓輸人端以及該電壓輸出端電連接， 並提供-靜f放電路彳f，使輸A端之靜電壓可經由此靜 電路徑放電，以防護該PM0SFET;其中，該領輪 一接觸墊，可供電連接至一負載電路。 ’、 上述具有靜電防護之功率電晶體元件中，該靜電防護元 件可更包含一深N型井區(deepN-well，deepNW)或一N型埋 層(N-type buriedlayer，NBL)。 在其中一種實施型態中，該靜電防護元件可包含一 NPW 電晶體，其射極(emitter)與集極(c〇l]ect〇r)分別與該電壓輪出 端及電壓輸入端電連接，基極受控於該電壓輸出端。 在另一種實施型態中，該靜電防護元件可包含一N型金 201205766 屬氧化物半導體(N-type metal oxide semiconductor, NMOS) 場效電晶體’其汲極(drain)與源極(source)分別與該電壓輸出 端及電壓輸入端電連接，閘極接地或受控於該電壓輸出端。 在又一種實施型態中，該靜電防護元件可包含一矽控整 流器(silicon controlled rectifier, SCR)，其陰極(cathode)與陽 極(anode)分別與該電壓輸出端及電壓輸入端電連接，閘極受 控於該電壓輸出端。201205766 VI. Description of the Invention: [Technical Field] The present invention relates to a power transistor component having electrostatic protection and a low dropout regulator using the power transistor component, wherein static electricity is provided for the power transistor component Discharge path. [Prior Art] FIG. 1 shows a schematic diagram of a prior art low dropout regulator, a low dropout regulator (LDO) 100 is a linear regulator for converting an input voltage Vin into an output voltage Vout. The basic structure is as shown in the figure, including an error amplifying circuit 10 and a power transistor element 20, and the error amplifying circuit 10 receives an output voltage sampling signal 'output voltage sampling signal between the output voltage and the ground potential, and has series resistors R1 and R2, The partial voltage on R2 is taken as the output voltage sampling signal. The error amplifying circuit 1 〇 compares the output voltage sampling signal with the reference signal Vref 'and amplifies the comparison result to the gate of the PMOSFET in the power transistor element 20 to control the conduction between the source and the drain, that is, the input voltage Vin Conversion parameter between the output voltage Vout. The cross-sectional view of the PMOSFET in the power transistor element 20 is shown in Fig. 2. From the cross-sectional view, the PMOSFET is located on the P-substrate (P_sub) 21, and adjacent high-pressure N-type well regions (NW) are formed below the upper surface. ) 23 and high pressure! 》Type well area (PW) 24; and form a plurality of shallow trench isolation regions (STI) 25, N+ body poles 26, P+ source poles 27, and p+ and poles 29 in the two well regions; A gate 28 is formed above the surface. Please continue to refer to Figure 1 and Figure 2: The output of the power transistor component 2 is turned over, it may be connected to the human body, or it may be exposed to various electric fields in the lying environment, and thus may accumulate charge and generate static electricity. The voltage or direct 201205766 is in contact with the high static, when the static discharge is higher than the green discharge path of the power-on, one of the possible discharges: this will cause an operational error of the circuit or serious. In view of this, the present invention is directed to the prior art described above. Insufficient anti-static pants and transistor components and low-dropout regulators. SUMMARY OF THE INVENTION It is an object of the present invention to provide a power conditioner having a still life. Another object of the present invention is to provide a low dropout voltage regulator having electrostatic protection using the above power transistor elements. In order to achieve the above purpose, in one aspect, the present invention provides a static-protected power transistor component comprising: pmosfet:, a pole and a drain are connected to a voltage input terminal and a voltage output terminal, and Static, P-side protection, electrically connected with the voltage input terminal and the voltage output terminal, and provides a static-discharge circuit 彳f, so that the static voltage of the input A terminal can be discharged through the electrostatic path to protect the PMOS transistor; Wherein, the collar wheel is a contact pad, and the power supply is connected to a load circuit. The above-mentioned electrostatic protection element may further comprise a deep N-well (deep N-well) or an N-type buried layer (NBL). In one embodiment, the ESD protection element may include an NPW transistor, and an emitter and a collector (c〇l]ect〇r) are electrically connected to the voltage wheel terminal and the voltage input terminal, respectively. The base is controlled by the voltage output. In another embodiment, the ESD protection element may comprise an N-type metal oxide oxide (N-type metal oxide semiconductor, NMOS) field effect transistor [the drain and the source]. The voltage output terminal and the voltage input terminal are respectively electrically connected, and the gate is grounded or controlled by the voltage output terminal. In another embodiment, the ESD protection device may include a silicon controlled rectifier (SCR), and a cathode and an anode are electrically connected to the voltage output terminal and the voltage input terminal respectively. The pole is controlled by this voltage output.
就另一個觀點言，本發明提供了一種提供一種具有靜電 防護之低壓差穩壓器，用以將一輸入端之輸入電壓轉換為一 輸出端之輸出電壓，該具有靜電防護之低壓差穩壓器包含： 一誤差放大電路，根據一輸出電壓取樣訊號與一參考訊號， 產生一誤差放大訊號，其中，該輸出電壓取樣訊號係取樣自 該輸出電壓；以及一功率電晶體元件，包括：pM〇SFET，其 ，極與沒極分別電連接於該輸人端與該輸出端；以及靜電防 «蔓元件，與6亥輸入端以及該輸出端電連接，並提供一靜電放 電路徑，使輸出端之靜電壓可經由此靜電放電路徑放電，以 防護該P型金屬氧化物半導體場效€晶體；射，該輸出端 係一接觸墊，可供電連接至一負載電路。 〇上述具有靜電防護之低壓差穩壓器中，該靜電防護元件 可更包含一深N型井區或一n型埋層。 ^述具有靜電防護之低壓差財，該靜f防護元件 娃iirNPN電晶體，其射極觸極分職該輸出端及輸入 、接’基極受控於該輸出端。 j具有靜電_之低壓差种，該靜電防護元件 分金屬氧化物㈣體場效電晶體，其汲極與源極 輪出端及輸入端電連接’閘極接地或受控於該輪出 201205766 端。 上述具有靜電防護之低壓差觀时，該靜 可包含-·整流器，其陰極與陽極分顺 及 端電連接，閘極受控於該輸出端。 入 底下藉由具體實施例詳加說明，t更容易瞭解本發明之 目的、技術内容、特點及其所達成之功效。 【實施方式】 "本發明的主要技術思缺_Nm道元件形成放電路 徑，以去除p型功率電晶體的靜電問題。 凊參閱第3圖與第4圖，顯示本發明的第一實施例。如 第3圖所示’ LDO 200包含誤差放大電路1〇與 元件30 ’與先前技術不_是，功率電晶體元件3g除^括 PMOSFET之外，另包含一個靜電防護元件2。pM〇sFET的 源極與沒極分別電連接於輸人端Vin與電 Vout ;在本實施射，靜電防護元件2包括—個㈣雙極接 面電晶體(bipolar junction transistor，BJT)，其射極(emkte仰 與集極(collector)%分別與電壓輸出端v〇ut及電壓輸入端vin 電連接’其基極(base)亦受控於電壓輸出端偏，當電壓輸 出端Vout的接觸墊1接觸到靜電壓時，可經由靜電防護元件 NPNBJT之集極到射極之路經放電，以保護pM〇SFET。 請繼續參閱第4目’顯示第一實施例中，功率電晶體元 件30之剖面圖。其中’相較於先前技術，本實施例更包含深 N型井區(deepNW)或N型埋層，其形成於p型基板 21與南壓N型井區及高壓p型井區24之間，以隔離功率電晶 體元件30與P型基板21 ;另外，NPNBJT之N+型射極31、 201205766 N+型集極32、及P+型基極分別如本圖中所示。第4圖亦顯示 ΝΡΝΒΓΓ與電阻之符號’絲*其剖面财各區域所代表的 電路關係。另外，帶有箭號之虛線代表當接觸塾1接觸到靜 電壓時的放電路徑，因ΝΡΝΒίΤ另提供了靜電壓的放電路 • 徑’因此不會對pM〇SFET造成功能上的影響與結構上的損 壞。 、 第5圖與第6圖顯示本發明的第二實施例。如圖所示， LDO 300包含誤差放大電路1〇與功率電晶體元件4〇，功率 • 電晶體元件40包括PM〇SFET和靜電防護元件2。在本實施 例中’靜電防護元件2包括一個NM〇SFET，其汲極(drain)42 與源極(S〇urCe)43分別與電壓輸出端v〇ut及電壓輸入端* 電連接，其閘極(gate)44亦受控於電壓輸出端v〇ut，當電壓 輸出端Vout的接觸墊1接觸到靜電壓時，可經由靜電防護元 件NMOSFET之寄生NPNBJT提供由汲極42到源極43之路 徑放電，以保護PMOSFET。 請繼續參閱第6圖，顯示第二實施例肀，功率電晶體4〇 鲁之剖面圖。其中’深N型井區或N型埋層22，其形成於p型 基板21與尚壓N型井區及高壓p型井區24之間，以隔離功 率電晶體元件40與P型基板21 ;另外，nmosfet之n+型 汲極42、N+型源極43、及閘極44 ’分別如本圖中所示。第6 圖亦顯示出NMOSFET之寄生npnbjt，表示其剖面圖中各 區域所代表的電路關係。另外，帶有箭號之虛線代表當接觸 墊1接觸到靜電壓時的放電路徑，因NM0SFET之寄生 NPNBJT另提供了靜電壓的放電路徑，因此不會對 PMOSFET造成功能上的影響與結構上的損壞。 第7圖與第8圖顯示本發明的第三實施例。如圖所示， 201205766 LDO 400包含誤差放大電路1〇與功率電晶體元件％，功率 電晶體元件50包括PMOSFET和靜電防護元件2。在本實施 例中’靜電防護元件2包括一個NMOSFET，其汲極(drain)52 與源極(source)53分別與電壓輸出端v〇ut及電壓輸入端vin 電連接，其閘極(gate)54則電連接至接地電位，當電壓輸出 端Vont的接觸墊1接觸到靜電壓時，可經由 NMOSFET之寄生NP丽提供她極52贿、極 電，以保護PMOSFET。 请繼續參閱第8圖，顯示第三實施例中，功率電晶體5〇 之剖面圖。其中，深N型井區或N型埋層22，其形成於P型 基板21與高壓N型井區及高壓p型井區24之間，以隔離功 率電晶體元件60與P型基板21 ;另外，之N+型 汲極52、N+型源極53、及閘極54，分別如本圖中所示。第8 圖亦顯示出NMOSFET之寄生NPNBJT，表示其剖面圖中各 區域所代表的電路關係。另外，帶有箭號之虛線代表當接觸 墊1接觸到靜電壓時的放電路徑，因NM0SFET之寄生 NPNBJT另提供了靜電壓的放電路徑，因此不會對 PMOSFET造成功能上的影響與結構上的損壞。 第9圖與第1〇圖顯示本發明的第四實施例。如圖所示， LDO 500包含誤差放大電路10與功率電晶體元件6〇，功率 電晶體元件60包括PMOSFET和靜電防護元件2。在本實施 例中’靜電防護元件2包括一個矽控整流器(siHc〇nc〇ntr〇丨led rectifier, SCR)，其陰極(cathode)62 與陽極(anode)63 分別與電 壓輸出端Vout及電壓輸入端Vin電連接，其閘極(gate)亦串 聯一電阻後電連接至電壓輸出端Vout,當電壓輸出端v〇ut 的接觸墊1接觸到靜電壓時，可經由靜電防護元件SCR之陰 201205766 極62到陽極63之路徑放電，以保護pM〇SFET。 請繼續參閱第10圖，顯示第四實施例中，功率電晶體 6〇之剖面圖。其中’深N型井區或N型埋層22，其形成於p 型基板21與高壓N型井區及高壓p型井區24之間，以隔離 . 1率電晶體元件5G與P型基板21 ;另外，SCR之陰極62、In another aspect, the present invention provides a low-dropout voltage regulator with electrostatic protection for converting an input voltage of an input terminal into an output voltage of an output terminal, the low-voltage voltage regulator with electrostatic protection. The device comprises: an error amplifying circuit, generating an error amplification signal according to an output voltage sampling signal and a reference signal, wherein the output voltage sampling signal is sampled from the output voltage; and a power transistor component, including: pM〇 a SFET, wherein the pole and the pole are electrically connected to the input end and the output end respectively; and the electrostatic anti-band element is electrically connected to the 6-inch input end and the output end, and provides an electrostatic discharge path to make the output end The static voltage can be discharged through the electrostatic discharge path to protect the P-type metal oxide semiconductor field effect crystal; the output end is a contact pad, and can be powered to be connected to a load circuit. In the above-mentioned electrostatic protection low-dropout voltage regulator, the static electricity protection element may further comprise a deep N-type well region or an n-type buried layer. The low-voltage difference with electrostatic protection, the static f-protection element, the iirNPN transistor, the emitter of the emitter is divided into the output and the input and the base are controlled by the output. j has a low voltage difference of static electricity, the static protection component is divided into metal oxide (four) body field effect transistor, the drain is electrically connected with the source wheel terminal and the input terminal 'gate grounded or controlled by the round out 201205766 end. In the above-mentioned low-voltage difference with electrostatic protection, the static may comprise a rectifier having a cathode and an anode electrically connected to the terminal, and the gate is controlled by the output. The purpose, technical content, features, and effects achieved by the present invention are more readily understood by the detailed description of the specific embodiments. [Embodiment] The main technical problem of the present invention is that the Nm track element forms a discharge path to remove the electrostatic problem of the p-type power transistor. Referring to Figures 3 and 4, a first embodiment of the present invention is shown. As shown in Fig. 3, the 'LDO 200 includes the error amplifying circuit 1' and the element 30' and the prior art is not. The power transistor element 3g includes an electrostatic protection element 2 in addition to the PMOSFET. The source and the bottom of the pM〇sFET are electrically connected to the input terminal Vin and the electric Vout respectively. In the present embodiment, the electrostatic protection element 2 includes a (four) bipolar junction transistor (BJT). The pole (emkte elevation and collector% are electrically connected to the voltage output terminal v〇ut and the voltage input terminal vin respectively] whose base is also controlled by the voltage output terminal, when the voltage output terminal Vout contacts the pad 1 When the static voltage is contacted, it can be discharged through the collector-to-emitter path of the static protection element NPNBJT to protect the pM〇SFET. Please refer to the fourth item to show the power transistor element 30 in the first embodiment. A cross-sectional view, wherein the present embodiment further includes a deep N-type well region (deep NW) or an N-type buried layer formed in the p-type substrate 21 and the south-pressure N-type well region and the high-pressure p-type well region. Between 24, the power transistor element 30 and the P-type substrate 21 are isolated; in addition, the N+-type emitter 31, the 201205766 N+-type collector 32, and the P+-type base of the NPNBJT are respectively shown in the figure. It also shows the circuit relationship between the ΝΡΝΒΓΓ and the symbol of the resistance 'wire*'. In addition, the dotted line with the arrow indicates the discharge path when the contact 塾1 is exposed to the static voltage, because the circuit of the static voltage is provided, so it does not have a functional influence on the pM〇SFET and the structure. The second embodiment of the present invention is shown in Figures 5 and 6. As shown, the LDO 300 includes an error amplifying circuit 1 and a power transistor element 4, and the power transistor element 40 includes a PM. SFET and ESD protection element 2. In this embodiment, 'electrostatic protection element 2 includes an NM〇SFET with drain 42 and source (S〇urCe) 43 and voltage output terminal v〇ut and voltage input, respectively. The terminal* is electrically connected, and its gate 44 is also controlled by the voltage output terminal v〇ut. When the contact pad 1 of the voltage output terminal Vout contacts the static voltage, it can be supplied via the parasitic NPNBJT of the electrostatic protection component NMOSFET. The path from the pole 42 to the source 43 is discharged to protect the PMOSFET. Please continue to refer to FIG. 6 to show a cross-sectional view of the power transistor 4 〇 第二, where the 'deep N-type well or the N-type buried layer 22, which is formed on the p-type substrate 21 and the still-pressed N-type well region Between the high-voltage p-type well regions 24, the power transistor element 40 and the P-type substrate 21 are isolated; in addition, the n+ type drain electrode 42, the N+ type source electrode 43, and the gate electrode 44' of the nmosfet are respectively as shown in the figure. Figure 6 also shows the parasitic npnbjt of the NMOSFET, indicating the circuit relationship represented by each region in the cross-sectional view. In addition, the dotted line with the arrow indicates the discharge path when the contact pad 1 is exposed to the static voltage, because of the NM0SFET The parasitic NPNBJT also provides a static voltage discharge path, so it does not cause functional and structural damage to the PMOSFET. Fig. 7 and Fig. 8 show a third embodiment of the present invention. As shown, the 201205766 LDO 400 includes an error amplifying circuit 1A and a power transistor element %, and the power transistor element 50 includes a PMOSFET and an ESD element 2. In the present embodiment, the 'electrostatic protection element 2 includes an NMOSFET, and the drain 52 and the source 53 are electrically connected to the voltage output terminal v〇ut and the voltage input terminal vin, respectively, and the gate thereof. 54 is electrically connected to the ground potential. When the contact pad 1 of the voltage output terminal Vont contacts the static voltage, the parasitic NP of the NMOSFET can be provided to protect her PMOSFET. Referring to Figure 8, a cross-sectional view of the power transistor 5A in the third embodiment is shown. Wherein, a deep N-type well region or an N-type buried layer 22 is formed between the P-type substrate 21 and the high-pressure N-type well region and the high-voltage p-type well region 24 to isolate the power transistor element 60 from the P-type substrate 21; In addition, the N+ type drain 52, the N+ type source 53 and the gate 54 are respectively as shown in the figure. Figure 8 also shows the parasitic NPNBJT of the NMOSFET, showing the circuit relationships represented by the various regions in its profile. In addition, the dotted line with the arrow indicates the discharge path when the contact pad 1 is exposed to the static voltage. Since the parasitic NPNBJT of the NM0SFET provides a discharge path of the static voltage, it does not cause a functional influence on the PMOSFET and the structure. damage. Fig. 9 and Fig. 1 show a fourth embodiment of the present invention. As shown, the LDO 500 includes an error amplifying circuit 10 and a power transistor element 6A, and the power transistor element 60 includes a PMOSFET and an ESD element 2. In the present embodiment, the 'electrostatic protection element 2 includes a sigma-controlled rectifier (SCR), the cathode 62 and the anode 63 are respectively connected to the voltage output terminal Vout and the voltage input. The terminal Vin is electrically connected, and the gate is also connected in series with a resistor and electrically connected to the voltage output terminal Vout. When the contact pad 1 of the voltage output terminal v〇ut contacts the static voltage, the cathode can pass the static protection element SCR 201205766 The path from pole 62 to anode 63 is discharged to protect the pM〇SFET. Referring to Figure 10, there is shown a cross-sectional view of the power transistor 6A in the fourth embodiment. The 'deep N-type well region or the N-type buried layer 22 is formed between the p-type substrate 21 and the high-pressure N-type well region and the high-voltage p-type well region 24 to isolate. 1 rate transistor component 5G and P-type substrate 21; in addition, the cathode 62 of the SCR,
陽極63、及閘極’分別如本圖中所示。第10圖亦顯示SCR 之BJT組成符號，表示其剖面圖中各區域所代表的電路關 係。另外，帶有箭號之虛線代表當接觸墊丨接觸到靜電壓時 • 的放電路徑，因SCR之陰極62到陽極63另提供了靜電壓的 放電路徑’因此*會對PMQSFET造成魏上的影響與結構 上的損壞。 第11圖顯示功率電晶體元件30的另一種實施例，與第4 圖不同的是’其PMOSFET與NPNBJT以STI 25以及高壓>^ 型井區23與高壓p型井區24隔開。 第12圖顯示功率電晶體元件4〇的另一種實施例，與第6 圖不同的是，其PMOSFET與NM〇S以STI 25以及高壓N型 _ 井區23與高壓P型井區24隔開。 第8圖之功率電晶體元件5 〇亦可改為與第丨2圖類似的半 - ‘導體結構，如第13圖。 第14圖顯示功率電晶體元件6〇的另一種實施例，與第 10圖不同的是，其PMOSFET與SCR以STI25以及高壓N型 井區23與高壓P型井區24隔開。 以上已針對較佳實施例來說明本發明，唯以上所述者， 僅係為使熟悉本技術者易於了解本發明的内容而已，並非用 來限定本發明之權利範圍。在本發明之相同精神下，熟悉本 技術者可以思及各種等效變化。例如，在所示各實施例電路 201205766 中，可插入不影響訊號主要意義的元件，如其他開關等；淺溝 槽絕緣區可以改換為局部魏化區料。凡此觀，皆可根 據本發明的教示類推而得，因此，本發明的範圍應涵蓋 及其他所有等效變化。 ^ l圖式簡單說明】 第1圖示出先前技術的低壓麵屋器示意圖。 第2圖示出第1圖之功率電晶體元件2〇結構 _ 土 第3圖與第4圖顯示本發明的第—實施例。σ不思圖 第5圖與第6圖顯示本發明的第二實施例。 · 第7圖與第8圖顯示本發明的第三實施例。 第9圖與第1〇圖顯示本發明的第四實施例。 第11圖顯示功率電晶體元件3〇 第12圖顯示功率電晶體元件4 =。 第示功率電晶體元件5 ^一^施例。 第Η圖顯示功率電晶體元件6Q的^種實:: 【主要元件符號說明】 25淺溝槽絕緣區 26本體極 27源極 28閘極 $沒極 31射極 32集極 42，力汲極 1接觸墊 10誤差放大電路 30, 40, 50, 60功率電晶體 元件 21P型基板 22深N型井區或n型埋層 23高壓n型井區 24高壓p型井區 201205766 43,53源極 Vin輸入電壓 44, 54閘極 Vout輸出電壓 62陰極 Vref參考訊號 63陽極 100, 200, 300, 400, 500 低壓差穩 R1,R2電阻 壓器 5 11The anode 63 and the gate ' are respectively as shown in the figure. Figure 10 also shows the BJT composition of the SCR, indicating the circuit relationships represented by the various regions in the profile. In addition, the dotted line with the arrow indicates the discharge path when the contact pad is in contact with the static voltage. Since the cathode 62 to the anode 63 of the SCR provides a discharge path of the static voltage, the * will affect the PMQSFET. With structural damage. Figure 11 shows another embodiment of a power transistor component 30, which differs from FIG. 4 in that its PMOSFET and NPNBJT are separated from the high voltage p-well region 24 by a STI 25 and high pressure > Figure 12 shows another embodiment of a power transistor component 4, which differs from Figure 6 in that the PMOSFET and NM〇S are separated from the high voltage P-well region 24 by the STI 25 and the high voltage N-type well region 23. . The power transistor component 5 of Fig. 8 can also be changed to a half- ‘conductor structure similar to that of Fig. 2, as shown in Fig. 13. Figure 14 shows another embodiment of a power transistor component 6A. Unlike FIG. 10, its PMOSFET and SCR are separated from the high voltage P-well region 24 by STI 25 and high pressure N-type well region 23. The present invention has been described with reference to the preferred embodiments thereof, and the present invention is not intended to limit the scope of the present invention. In the same spirit of the invention, various equivalent changes can be conceived by those skilled in the art. For example, in the circuit of the embodiment 201205566, components that do not affect the main meaning of the signal, such as other switches, can be inserted; the shallow trench slot insulation area can be changed to a local Weihua zone. The present invention can be derived from the teachings of the present invention and, therefore, the scope of the present invention should be construed as the BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic view showing a prior art low pressure surface house. Fig. 2 is a view showing a structure of a power transistor element of Fig. 1 _ _ 3rd and 4th drawings showing a first embodiment of the present invention. σ不思图 Figures 5 and 6 show a second embodiment of the present invention. Fig. 7 and Fig. 8 show a third embodiment of the present invention. Fig. 9 and Fig. 1 show a fourth embodiment of the present invention. Figure 11 shows the power transistor component 3 〇 Figure 12 shows the power transistor component 4 =. The first embodiment shows a power transistor component. The first diagram shows the power transistor component 6Q:: [Main component symbol description] 25 shallow trench isolation region 26 body pole 27 source 28 gate $ no pole 31 emitter 32 collector 42, force bungee 1 contact pad 10 error amplifying circuit 30, 40, 50, 60 power transistor element 21P type substrate 22 deep N-type well or n-type buried layer 23 high pressure n-type well area 24 high pressure p-type well area 201205766 43,53 source Vin input voltage 44, 54 gate Vout output voltage 62 cathode Vref reference signal 63 anode 100, 200, 300, 400, 500 low dropout stability R1, R2 resistor 5 11