TWI435658B - Digital flash charger controller - Google Patents

Description

Digital flash charging circuit

The present invention relates to a flash lamp charging circuit, and more particularly to a digital flash charging circuit having a pulse positive edge close to an inductive negative edge.

At present, the common charging circuit, the power supply is mostly combined with the transformer, and the adjusting device is arranged on the primary side of the transformer to achieve the purpose of simultaneously adjusting the output current and completing the charging and discharging function of the circuit. In the current design field, designers mostly choose to install an integrated chip (IC) on the primary side of the transformer to implement a charging circuit.

Conventionally, the charging circuit is generally composed of a charging chip, and an analog component is used for observation of voltage and current. Therefore, this method is susceptible to noise and makes the measured data distorted. Secondly, the passive components such as resistors and capacitors required to charge the wafer and the observation point also occupy a considerable area and component number on the circuit board. Therefore, in summary, the circuit that uses the charging chip to charge and discharge the flash lamp has a certain degree of complexity in operation, and is also worthy of consideration in terms of manufacturing cost and work performance.

In view of the above, the present invention provides a digital flash charging circuit, which can not only solve the problem of using analog components for voltage and current observation, so that the measured data is affected by noise and is distorted, and the logic circuit can be used instead of the conventional one. Recharge the wafer to reduce the number of components and area consumed on the board.

The present invention provides a digital flash charging circuit adapted to charge an energy storage component. The digital flash charging circuit comprises: a transformer, a power component and a special application integrated circuit. The transformer has a primary side and a secondary side, wherein the secondary side is electrically connected to the energy storage element. The power component is used to output a power. The special application integrated circuit is used to output a pulse modulation signal to control whether the power is selectively input to the primary side. The pulse modulation signal has a pulse positive edge and a cutoff time. The secondary side system generates an inductive signal in response to the primary side, and the inductive signal has an inductive negative edge. The special application integrated circuit converts the sensing signal into a digital signal, and tracks the sensing negative edge according to the digital signal, thereby adjusting the cutting time and making the positive edge of the next pulse close to the corresponding sensing negative edge.

Therefore, the digital flash charging circuit of the present invention can adjust the cutting time of the pulse modulation signal by using the special application integrated circuit, so that a pulse positive edge under the pulse modulation signal can be close to the corresponding induced negative edge. In order to achieve higher charging and discharging work efficiency.

The above description of the present invention is intended to be illustrative and illustrative of the spirit and principles of the invention, and to provide further explanation of the scope of the invention. The features, implementations, and utilities of the present invention are described in detail with reference to the preferred embodiments.

"FIG. 1" is a digital flash charging circuit according to an embodiment of the present invention. The digital flash charging circuit 100 includes a transformer 10, an application-specific integrated circuit (ASIC) 20 and a power supply component 30. The power component 30 is connected to the primary side 11 of the transformer 10, and the power component 30 is used to provide an input voltage V _in (or power), and an output voltage V is outputted to the secondary side 12 thereof by switching of the transformer 10. _o . The secondary element 12 is connected to the energy storage, the energy storage member can be charged through the power elements 30 provided on the input voltage V _in. For example, the energy storage component can be a capacitor 50 as in FIG.

Application-specific integrated circuit 20 is disposed between the primary side 12 and secondary side 11, and may be used to generate a pulse modulation signal V _PWM to control the input voltage V _in for selectively inputting an input or primary side 11 is not. According to an embodiment of the invention, the capacitor 50 is further connected to the flash to complete charging of the flash by the digital flash charging circuit 100.

As shown in "2A" to "2C", when the pulse modulation signal V _{PWM is} just switched to the low level, the secondary side switching current I _s has the secondary side switching current maximum I _spk . The secondary side 12 of the transformer 10 simultaneously forms an inductive signal V _FB in response to the secondary side switching current I _s . When the value of the secondary side switching current I _s gradually decreases with the charging time of the capacitor 50 (ie, the time when the pulse modulation signal V _PWM is low), and the secondary side switching current I _s finally returns to zero, The inductive signal V _FB will also gradually disappear. Here, it is defined as the induced negative edge V- of the inductive signal V _FB .

Therefore, the pulse modulation signal V _PWM is switched from low level to high level of the pulse rising edge time point of P +, the pulse modulation signal V _PWM is switched from high level to low level of the negative pulse edge time point P-, and a pulse The modulation signal V _PWM has a working time _Ton and a cut-off time _Toff . The working time T _on and the cutting time T _off are time intervals in which the pulse modulation signal V _PWM is at a high level and a low level, respectively.

Referring to FIG. 3A, the special application integrated circuit 20 includes an analog-to-digital converter 32, a pulse-width-modulation controller (PWM controller) 34, and a pulse signal generator 36. The analog-to-digital converter 32 can be used to convert the sensing signal V _FB into a digital signal, and sample the sensing signal V _FB and output a plurality of digital signals respectively according to different sampling time points.

According to the first embodiment of the present invention, the pulse controller 34 includes a first register 310, a second register 320, a differentiator 330, a first comparator 340, an indication controller 350, and a first register. 310, a multiplexer 360 and a flip-flop 370 between the second register 320 and the analog-to-digital converter 32.

As shown in Figure 4A, the user can pre-set a positive edge sampling time T+ and a negative edge sampling time T- through the software to enable the indicator controller 350 to pulse the negative edge P- of the pulse modulation signal V _PWM . After the next positive edge sampling time T+, the sampling trigger of the first sampling time point T ₁ is performed. Then, after the pulse modulation signal V _PWM ends the current duty cycle T _D and reaches the pulse positive edge P+, the working time _Ton and the pulse negative edge P- again, the controller 350 is instructed to return to the pulse negative edge P-. At the negative sampling time T-, the sampling trigger of the second sampling time point T ₂ is performed.

The digital signals obtained by the two sampling time points are the base signal V _CMP and the offset signal V _{OFF , respectively} . The differentiator 330 can be used to obtain the difference between the base signal V _CMP and the offset signal V _OFF and output the differential signal V _DIFF . The first comparator 340 can be used to compare the differential signal V _DIFF to a maximum tolerance signal V _DUP and a minimum tolerance signal V _DWN .

As shown in FIG. 5A, when the differential signal V _{DIFF is} greater than the maximum tolerance signal V _DUP (ie, Case-A in the figure), the first comparator 340 outputs a high level indication signal V _IND , ie, The offset signal V _OFF sampled by the analog-to-digital converter 32 is a low level value of the inductive signal V _FB . Therefore, the indication controller 350 can update the negative edge sampling time T- and the cutoff time T _off according to the high level signal of the indication signal V _IND . Here, according to the first embodiment of the present invention, as shown in "FIG. 4A", the next negative edge sampling time T'- will be shortened by a modulation time interval T further than the previous negative edge sampling time T-. _Δ . The off time pulse of the modulation signal V _PWM T _'off will equal the negative edge of a previous sampling time T-.

Similarly, analog to digital converter 32 T'- for the third sampling time point T ₃ of the sampling operation to a negative edge sampling time. If the differential signal V _DIFF is less than the minimum tolerance signal V _DWN (ie, Case-C in the figure), the indication signal V _IND output by the first comparator 340 is low. (Not-hit), which means the analog to digital converter 32 in the third sampling time T ₃ to give samples of the shift signal V _'OFF line at the high level value of the sensing signal V _FB. Therefore, the indication controller 350 can update the negative edge sampling time T- and the cutoff time T _off again according to the low level signal of the indication signal V _IND . Here, as shown in "Fig. 4A", the next negative edge sampling time T"- will be increased by one-half of the modulation time interval T _Δ from the previous negative edge sampling time T'-. The cut-off time T" _{off of the} modulation signal V _PWM is one more of the modulation time interval T _Δ more than the previous cut-off time T' _off .

Then, the offset signal V" _OFF obtained by the analog-to-digital converter 32 at the fourth sampling time point T ₄ is further subjected to the signal processing procedure as described above to cause the indication controller 350 to follow the high or low level of the indication signal V _IND . Correctly, and sequentially change and update the pulse modulation signal V _PWM cutoff time _Toff and the negative edge sampling time T-. Since the modulation time interval T _Δ can be preset through the software, and is successively halved and decreased with time, Therefore, the user can determine in advance that the modulation time interval T _Δ is reduced to a lower limit value in a certain period of time through the software. In the case where each modulation time interval T _{Δ is} successively decreased and converged, as in "Block 4B" It is shown that the pulse positive edge P+ of the final pulse modulation signal V _PWM will be close to the induced negative edge V- of the induced signal V _FB which is generated after the previous cutting time T _off , and the pulse modulation signal V _PWM The duty cycle T _D will also be fixed until the induced negative edge V-position of the sensing signal V _FB changes, and the special application integrated circuit 20 according to the embodiment of the present invention will continue to track the sensing negative edge of the sensing signal V _FB . V-.

Moreover, to increase the accuracy of the data, the pulse controller 34 can further include more than one multiplexer 360, a flip-flop 370, and a filter 380. The "FIG. 3B" is a special application integrated circuit according to the second embodiment of the present invention, wherein the pulse controller 34a includes a first register 310, a second register 320, a differentiator 330, and a first comparator 340. The controller 350 is coupled to the filter 380, the multiplexer 360, and the flip-flop 370 connected between the first register 310, the second register 320, and the analog-to-digital converter 32.

Next, the special application integrated circuit according to the third embodiment of the present invention may also be as shown in FIG. 3C, wherein the pulse controller 34b includes a second register 320, a second comparator 342, and an indication controller 350. The multiplexer 360 and the flip-flop 370 are connected between the second register 320 and the analog-to-digital converter 32.

Please refer to "4C". The user can pre-set a negative edge sampling time T- through the software to ensure that the analog digital converter 32 can sample the low level of the sensing signal V _FB at the first sampling time point T ₁ . Quasi-value.

The digital signal obtained by the analog-to-digital converter 32 at the first sampling time point T ₁ is the offset signal V _OFF , and the offset signal V _OFF can be triggered by the trigger of the end of convert in the 3C picture. Stored in the second register 320. The second comparator 342 can be used to compare the offset signal V _OFF to a maximum critical signal V _THH and a minimum critical signal V _THL .

As shown in FIG. 5B, when the offset signal V _{OFF is} less than the minimum critical signal V _THL (ie, Case-A in the drawing), the second comparator 342 outputs the high level indication signal V _IND . Therefore, the indication controller 350 can update the negative edge sampling time T- and the cutoff time T _off according to the high level (Hit) signal of the indication signal V _IND . Here, as shown in "Fig. 4C", the next negative edge sampling time T'- will be shortened by a modulation time interval T _Δ more than the previous negative edge sampling time T-. The off time pulse of the modulation signal V _PWM T _'off will equal the negative edge of a previous sampling time T-.

Similarly, the analog-to-digital converter 32 performs a sampling operation at the second sampling time point T ₂ at the negative edge sampling time T'-. Thereto, analog to digital converter 32 to an offset sampled signal V _'OFF will be under complete conversion trigger signals, to be stored in the second register 320. Then, with please see "FIG. 5B", when comparator 342 comparing the second analog to digital converter 32 to a second sampling time point T ₂ is offset to the sampled signal V _'OFF line greater than the maximum threshold signal V _THH (ie, Case-C in the figure), the second comparator 342 outputs a low level indication signal V _IND . Therefore, the indication controller 350 can update the negative edge sampling time T- and the cutoff time T _off again according to the low-level (Not-hit) signal of the indication signal V _IND . Here, the next negative edge sampling time T"- will be increased by one-half of the modulation time interval T _Δ from the previous negative edge sampling time T'-. The cut-off time of the pulse modulation signal V _PWM T" _off will be one more of the modulation time interval T _Δ than the previous cut-off time T' _off .

Next, analog to digital converter 32 to a _three-shift signal to obtain the third sample time T V _"OFF will then be temporarily stored in the second register 320, and then compared to the maximum comparator 342 through the second The critical signal V _THH and the minimum critical signal V _THL . The cut-off time T _off and negative of the pulse modulation signal V _PWM are sequentially modulated and updated according to the high or low level of the indication signal V _IND outputted by the second comparator 342. Edge sampling time T-.

In the case where each modulation time interval T _{Δ is} successively decreased and converged, as shown in "4D", the pulse positive edge P+ of the final pulse modulation signal V _PWM will be close to its previous cutting time T. _{After the off} , the induced negative edge V- of the induced signal V _{FB is} generated, and the duty cycle T _{D of the} pulse modulated signal V _PWM is also fixed.

In addition, to increase the accuracy of the data, the pulse controller 34b may further include more than one multiplexer 360, a flip-flop 370, and a filter 380. The "3D picture" is a special application integrated circuit according to the fourth embodiment of the present invention, wherein the pulse controller 34c includes a second register 320, a second comparator 342, an indication controller 350, and a connection to the second temporary A filter 380, a multiplexer 360, and a flip-flop 370 between the register 320 and the analog-to-digital converter 32.

Further, in accordance with the fifth embodiment of the present invention, the second embodiment (such as "3B") and the fourth embodiment (such as "3D") may be combined to form a preferred embodiment. Please refer to FIG. 3E, which is a special application integrated circuit according to a fifth embodiment of the present invention. The sampling principle of the pulse controller 34d is a combination of the second and fourth embodiments of the present invention. The pulse controller 34d of the preferred embodiment further includes a multiplexer 400.

Therefore, according to the digital flash charging circuit of the embodiment of the present invention, the analog signal can be sampled by the analog digital converter, and according to the two algorithms, the pulse positive edge of the pulse modulated signal can be close to the sensing of the sensing signal. Negative edge, so that the transformer returns to the primary side charging, in order to achieve higher efficiency of the digital flash charging circuit.

While the present invention has been described above in its preferred embodiments, it is not intended to limit the invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of patent protection shall be subject to the definition of the scope of the patent application attached to this specification.

10. . . transformer

11. . . Primary side

12. . . Secondary side

20. . . Special application integrated circuit

30. . . Power supply component

32. . . Analog digital converter

34, 34a, 34b, 34c, 34d. . . Pulse controller

36. . . Pulse signal generator

100. . . Digital flash charging circuit

50. . . capacitance

310. . . First register

320. . . Second register

330. . . Differentiator

340. . . First comparator

342. . . Second comparator

350. . . Indication controller

360,400. . . Multiplexer

370. . . Positive and negative

380. . . filter

I _s . . . Secondary side switching current

I _spk . . . Secondary side switching current maximum

P+. . . Pulse positive edge

P-. . . Pulse negative edge

T+. . . Positive edge sampling time

T-, T'-, T"-... negative edge sampling time

T _on . . . operating hours

V _CMP . . . Base signal

V _FB . . . Inductive signal

V-. . . Inductive negative edge

V _in . . . Input voltage

V _o . . . The output voltage

V _DIFF . . . Differential signal

V _PWM . . . Pulse modulation signal

T _Δ . . . Modulation time interval

T _D . . . Working period

V _DUP . . . Maximum tolerance signal

V _DWN . . . Minimum tolerance signal

V _THH . . . Maximum critical signal

V _THL . . . Minimum critical signal

T ₁ . . . First sampling time point

T ₂ . . . Second sampling time point

T ₃ . . . Third sampling time point

T ₄ . . . Fourth sampling time point

V _IND . . . Indication signal

T _off , T' _off , T" _off ... cut off time

V _OFF , V' _OFF , V" _OFF ... offset signal

Figure 1 is a digital flash charging circuit in accordance with an embodiment of the present invention;

2A to 2C are respectively schematic diagrams of waveforms according to an embodiment of the present invention;

Figure 3A is a special application integrated circuit according to the first embodiment of the present invention;

Figure 3B is a special application integrated circuit according to a second embodiment of the present invention;

3C is a special application integrated circuit according to a third embodiment of the present invention;

3D is a special application integrated circuit according to a fourth embodiment of the present invention;

3E is a special application integrated circuit according to a fifth embodiment of the present invention;

Figure 4A is a schematic view of sampling according to the first embodiment of the present invention;

Figure 4B is a schematic diagram of tracking the positive edge of the pulse to the inductive negative edge according to Figure 4A;

Figure 4C is a schematic view of sampling according to a third embodiment of the present invention;

4D is a schematic diagram of tracking the positive edge of the pulse to the inductive negative edge according to FIG. 4C;

Figure 5A is a data comparison reference diagram of the sampling method according to the first and second embodiments of the present invention;

Fig. 5B is a data comparison reference diagram of the sampling method according to the third and fourth embodiments of the present invention.

10. . . transformer

11. . . Primary side

12. . . Secondary side

20. . . Special application integrated circuit

30. . . Power supply component

50. . . capacitance

100. . . Digital flash charging circuit

I _s . . . Secondary side switching current

V _PWM . . . Pulse modulation signal

V _FB . . . Inductive signal

V _in . . . Input voltage

V _o . . . The output voltage

Claims (7)

A digital flash charging circuit adapted to charge an energy storage component, the digital flash charging circuit comprising: a transformer having a primary side and a secondary side, the secondary side being electrically connected to the energy storage a power component that outputs a power; and a special application integrated circuit that outputs a pulse modulation signal to control whether the power is selectively input to the primary side, the pulse modulation signal having a pulse positive edge and everything In the off time, the secondary side generates an inductive signal in response to the primary side, the inductive signal has an inductive negative edge, and the special application integrated circuit converts the inductive signal into a digital signal and tracks the digital signal according to the digital signal. The sensing negative edge is used to adjust the cutting time of the next pulse modulation signal, so that the positive edge of the pulse of the next pulse modulation signal is close to the cutting time of the previous pulse modulation signal, and then The induced negative edge of the inductive signal. The digital flash charging circuit of claim 1, wherein the special application integrated circuit comprises: an analog-to-digital converter for converting the sensing signal to the digital signal; a pulse signal generator, according to a working time, The pulse cutting signal generates the pulse modulation signal, and the pulse modulation signal sequentially includes the pulse positive edge, the working time, a pulse negative edge and the cutting time; and a pulse controller according to a positive edge sampling Time, a negative edge sampling time, and a negative edge of the pulse obtain a sample value from the analog digital converter, the pulse control The device updates the cutoff time and the negative edge sampling time based on the sampled value, an upper threshold, and a lower threshold. The digital flash charging circuit of claim 2, wherein the pulse controller obtains a high level value from the analog digital converter according to the positive edge sampling time and the pulse negative edge, and the pulse controller samples the negative edge according to the negative edge The time and the negative edge of the pulse obtain a low level value from the analog digital converter, and the pulse controller uses the difference between the high level value and the low level value as the sample value. The digital flash charging circuit of claim 2, wherein the pulse controller obtains a plurality of high level values from the analog digital converter according to the positive edge sampling time and the pulse negative edge, the pulse controller according to the negative edge The sampling time and the negative edge of the pulse obtain a plurality of low level values from the analog digital converter, and the pulse controller uses the difference between a high level median value and a low level median value as the sample value, wherein the high level The quasi-median value and the low-order median value are the median of the high-level values and the median of the low-level values, respectively. The digital flash charging circuit of claim 2, wherein the pulse controller obtains a low level value from the analog digital converter according to the negative edge sampling time and the pulse negative edge, and the sampling is performed at the low level value. The digital flash charging circuit of claim 2, wherein the pulse controller obtains a plurality of low level values from the analog digital converter according to the negative edge sampling time and the pulse negative edge, and uses a low level median value For the sampled value, the low level median value is the median of the low level values. The digital flash charging circuit of claim 2, wherein the pulse controller Obtaining a plurality of high level values from the analog-to-digital converter according to the positive edge sampling time and the pulse negative edge, the pulse controller obtaining a plurality of low levels from the analog edge converter according to the negative edge sampling time and the pulse negative edge And the pulse controller further includes a multiplexer, and selectively selecting a sample value according to the multiplexer with a difference median value and a low level median value, wherein the high level values have a high level The median value, and the low median value is the median of the low level values, and the difference median value is the difference between the high level median value and the low level median value.