TWI435425B - Semiconductor device and semiconductor package having the same - Google Patents

Semiconductor device and semiconductor package having the same Download PDF

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Publication number
TWI435425B
TWI435425B TW100111448A TW100111448A TWI435425B TW I435425 B TWI435425 B TW I435425B TW 100111448 A TW100111448 A TW 100111448A TW 100111448 A TW100111448 A TW 100111448A TW I435425 B TWI435425 B TW I435425B
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TW
Taiwan
Prior art keywords
ball
under
metal
layer
dielectric layer
Prior art date
Application number
TW100111448A
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Chinese (zh)
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TW201222742A (en
Inventor
Chi Tsung Chiu
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Advanced Semiconductor Eng
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Publication of TW201222742A publication Critical patent/TW201222742A/en
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Publication of TWI435425B publication Critical patent/TWI435425B/en

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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
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Description

半導體裝置及具有該半導體裝置之半導體封裝結構Semiconductor device and semiconductor package structure having the same

本發明係關於一種半導體裝置及具有該半導體裝置之半導體封裝結構，詳言之，係關於一種具有球下金屬平面之半導體裝置及具有該半導體裝置之半導體封裝結構。The present invention relates to a semiconductor device and a semiconductor package structure having the same, and more particularly to a semiconductor device having a sub-spherical metal plane and a semiconductor package structure having the same.

在一習知半導體裝置(例如，一晶粒或一中介基板(Interposer))中，至少一接地平面或電源平面係形成於一重佈層(Redistribution Layer,RDL)上，該重佈層係內埋於位於一半導體基板之正面或背面上的複數個介電層內。該習知半導體裝置的缺點是，形成該接地平面或該電源平面的成本較高。In a conventional semiconductor device (for example, a die or an interposer), at least one ground plane or power plane is formed on a redistribution layer (RDL), and the redistribution layer is buried. In a plurality of dielectric layers on the front or back side of a semiconductor substrate. A disadvantage of the conventional semiconductor device is that the cost of forming the ground plane or the power plane is high.

本發明提供一種半導體裝置，其包括一半導體基板、複數個第一導通柱、至少一第二導通柱、一背面介電層、複數個第一背面球下金屬(Under Ball Metal,UBM)銲墊及一第一背面球下金屬平面。該半導體基板具有一正面及一背面。該等第一導通柱係位於該半導體基板內，且每一該等第一導通柱係被一第一內襯(Liner)所圍繞。該第二導通柱係位於該半導體基板內且被一第二內襯所圍繞。該背面介電層係與該背面位於同一側。該等第一背面球下金屬銲墊係位於該背面介電層上且電性連接至該等第一導通柱。該第一背面球下金屬平面係位於該背面介電層上且電性連接至該至少一第二導通柱。該第一背面球下金屬平面具有複數個穿孔，該等第一背面球下金屬銲墊係設置於該等穿孔內，且該第一背面球下金屬平面及該等第一背面球下金屬銲墊之間具有一間距(Gap)。The present invention provides a semiconductor device including a semiconductor substrate, a plurality of first via posts, at least one second via post, a back dielectric layer, and a plurality of first Under Ball Metal (UBM) pads. And a metal plane under the first back ball. The semiconductor substrate has a front side and a back side. The first conductive pillars are located in the semiconductor substrate, and each of the first conductive pillars is surrounded by a first liner. The second conductive pillar is located in the semiconductor substrate and is surrounded by a second liner. The back dielectric layer is on the same side as the back side. The first back ball under metal pads are located on the back dielectric layer and are electrically connected to the first via posts. The first back ball under metal plane is on the back dielectric layer and is electrically connected to the at least one second via. The first back ball under the metal plane has a plurality of through holes, the first back ball under the metal pads are disposed in the through holes, and the first back ball under the metal plane and the first back ball under the metal welding There is a gap between the pads (Gap).

在本發明中，該等第一背面球下金屬銲墊及該第一背面球下金屬平面係位於該半導體裝置之最外層。因此，形成該等第一背面球下金屬銲墊及該第一背面球下金屬平面的成本較低。此外，該第一背面球下金屬平面係可為一接地平面或一電源平面，藉此，可維持電氣性能之信號完整性及電源完整性。In the present invention, the first back ball under metal pads and the first back ball under metal plane are located at the outermost layer of the semiconductor device. Therefore, the cost of forming the first back ball under the metal pad and the first back ball under the metal plane is lower. In addition, the first back ball under metal plane can be a ground plane or a power plane, thereby maintaining signal integrity and power integrity of electrical performance.

本發明更提供一種半導體封裝結構，其包括上述的半導體裝置、一上晶粒及一底膠(Underfill)。該上晶粒係位於該半導體裝置上且具有複數個上連接元件於其一表面上，其中該等上連接元件係分別連接至該等第一背面球下金屬銲墊，且該等上連接元件至少其中之一係電性連接至該第一背面球下金屬平面。該底膠係位於該上晶粒及該半導體裝置之間，以保護該等上連接元件。The invention further provides a semiconductor package structure comprising the above semiconductor device, an upper die and an underfill. The upper die is on the semiconductor device and has a plurality of upper connecting elements on one surface thereof, wherein the upper connecting elements are respectively connected to the first back ball underlying metal pads, and the upper connecting elements are At least one of the wires is electrically connected to the first back ball under the metal plane. The primer is positioned between the upper die and the semiconductor device to protect the upper connection elements.

參考圖1，其顯示本發明第一實施例之半導體裝置之俯視圖。參考圖2，其顯示沿著圖1之線2-2之剖面示意圖。該半導體裝置1包括一半導體基板10、複數個第一導通柱11、至少一第二導通柱12、一背面鈍化層(Passivation)13、複數個第一背面重佈層(Redistribution Layer,RDL)14、至少一第二背面重佈層15、一背面介電層16、複數個第一背面球下金屬(Under Ball Metal,UBM)銲墊17及一第一背面球下金屬平面18。Referring to Fig. 1, there is shown a plan view of a semiconductor device according to a first embodiment of the present invention. Referring to Figure 2, a cross-sectional view taken along line 2-2 of Figure 1 is shown. The semiconductor device 1 includes a semiconductor substrate 10, a plurality of first via posts 11, at least one second via post 12, a back passivation layer 13, and a plurality of first back redistribution layers (RDL) 14 At least a second back redoning layer 15, a back dielectric layer 16, a plurality of first Under Ball Metal (UBM) pads 17 and a first back ball under metal plane 18.

該半導體基板10具有一正面101及一背面102。該等第一導通柱11係位於該半導體基板10內，且每一該等第一導通柱11係被一第一內襯(Liner)111所圍繞。該第二導通柱12係位於該半導體基板10內且被一第二內襯121所圍繞。在本實施例中，該等第一導通柱11之頂面、該等第一內襯111、該第二導通柱12及該第二內襯121係大致與該背面102齊平。較佳地，該等第一內襯111及該第二內襯121包括一層或多層的氮化矽(Silicon Nitride,SiN)、氧化物、聚合物等等，且該等第一導通柱11及該第二導通柱12包括銅、鎢、鋁、銀及其混合物等等。亦可使用其他包含導電擴散阻隔層的材料，例如氮化鉭(Tantalum Nitride,TaN)、鉭(Tantalum,Ta)、氮化鈦(Titanium Nitride,TiN)、鈦(Titanium,Ti)、鎢化鈷(Cobalt Tungsten,CoW)等等。The semiconductor substrate 10 has a front side 101 and a back side 102. The first conductive pillars 11 are located in the semiconductor substrate 10, and each of the first conductive pillars 11 is surrounded by a first liner 111. The second via 12 is located within the semiconductor substrate 10 and is surrounded by a second liner 121. In this embodiment, the top surfaces of the first conductive posts 11 , the first inner liners 111 , the second conductive pillars 12 , and the second inner liners 121 are substantially flush with the back surface 102 . Preferably, the first inner liner 111 and the second inner liner 121 comprise one or more layers of silicon nitride (SiN), an oxide, a polymer, etc., and the first conductive pillars 11 and The second via 12 includes copper, tungsten, aluminum, silver, mixtures thereof, and the like. Other materials including conductive diffusion barrier layers such as tantalum nitride (Tantalum Nitride, TaN), tantalum (Tantalum, Ta), titanium nitride (Titanium Nitride, TiN), titanium (Titanium, Ti), cobalt cobalt may also be used. (Cobalt Tungsten, CoW) and more.

該背面鈍化層13(例如，一光阻層(例如，苯環丁烯(Benzocyclobutene,BCB))或一不導電聚合物)係位於該半導體基板10之背面102，且具有複數個開口以顯露該等第一導通柱11及該第二導通柱12之末端。該等第一背面重佈層14係位於該背面鈍化層13之該等開口內及部分該背面鈍化層13上，以接觸且電性連接該等第一導通柱11。該第二背面重佈層15係位於該背面鈍化層13之該等開口內及部分該背面鈍化層13上，以接觸且電性連接該第二導通柱12。該等第一背面重佈層14及該第二背面重佈層15係以電鍍形成的相同銅層。The back passivation layer 13 (eg, a photoresist layer (eg, Benzocyclobutene (BCB)) or a non-conductive polymer) is located on the back side 102 of the semiconductor substrate 10 and has a plurality of openings to reveal the Waiting for the ends of the first via posts 11 and the second via posts 12. The first back redistribution layer 14 is located in the openings of the back passivation layer 13 and partially on the back passivation layer 13 to contact and electrically connect the first via posts 11 . The second back redistribution layer 15 is located in the openings of the back passivation layer 13 and partially on the back passivation layer 13 to contact and electrically connect the second via posts 12 . The first back redistribution layer 14 and the second back redistribution layer 15 are the same copper layer formed by electroplating.

該背面介電層16係與該背面102位於同一側。在本實施例中，該背面介電層16係位於該等第一背面重佈層14、該第二背面重佈層15及該背面鈍化層13上方。該背面介電層16具有複數個第一開口161及至少一第二開口162，以分別顯露部分該等第一背面重佈層14及該第二背面重佈層15。The back dielectric layer 16 is on the same side as the back surface 102. In this embodiment, the back dielectric layer 16 is located above the first back redistribution layer 14 , the second back redistribution layer 15 , and the back passivation layer 13 . The back dielectric layer 16 has a plurality of first openings 161 and at least one second opening 162 to respectively expose portions of the first back redistribution layer 14 and the second back redistribution layer 15.

該等第一背面球下金屬銲墊17係位於該等第一開口161內及部分該背面介電層16上，且電性連接至該等第一導通柱11。該第一背面球下金屬平面18係位於該背面介電層16上，且電性連接至該至少一第二導通柱12。該第一背面球下金屬平面18之面積係大於每一該等第一背面球下金屬銲墊17之面積。該第一背面球下金屬平面18係顯露於空氣中且具有複數個穿孔181。該等第一背面球下金屬銲墊17係設置於該等穿孔181內。該第一背面球下金屬平面18及該等第一背面球下金屬銲墊17之間具有一間距(Gap)182。亦即，該第一背面球下金屬平面18並未接觸該等第一背面球下金屬銲墊17。The first back ball under metal pads 17 are located in the first openings 161 and on the portion of the back dielectric layer 16 and are electrically connected to the first vias 11 . The first back ball under metal plane 18 is located on the back dielectric layer 16 and is electrically connected to the at least one second via post 12 . The area of the first back ball under metal plane 18 is greater than the area of each of the first back ball under metal pads 17. The first back ball under metal plane 18 is exposed to the air and has a plurality of perforations 181. The first back ball under metal pads 17 are disposed in the through holes 181. There is a gap (Gap) 182 between the first back ball under metal plane 18 and the first back ball under metal pads 17. That is, the first back ball under metal plane 18 does not contact the first back ball under metal pads 17.

在本實施例中，該半導體裝置1更包括至少一第二背面球下金屬銲墊19。該第二背面球下金屬銲墊19係位於該第二開口162內及該背面介電層16上，且電性連接至該第二導通柱12。該第一背面球下金屬平面18係透過該第二背面球下金屬銲墊19電性連接至該第二導通柱12。在本實施例中，該半導體裝置1更包括至少一跡線(Trace)183連接該第二背面球下金屬銲墊19a至該第一背面球下金屬平面18。In this embodiment, the semiconductor device 1 further includes at least one second back ball under metal pad 19 . The second back ball under metal pad 19 is located in the second opening 162 and the back dielectric layer 16 and is electrically connected to the second via 12 . The first back ball under metal plane 18 is electrically connected to the second via post 12 through the second back ball under metal pad 19 . In this embodiment, the semiconductor device 1 further includes at least one trace 183 connecting the second back ball under metal pad 19a to the first back ball under metal plane 18.

在本實施例中，該等第一背面球下金屬銲墊17、該第二 背面球下金屬銲墊19及該第一背面球下金屬平面18係藉由選擇性圖案化包括一銅層、一鎳層、一鈀層及一金層的一球下金屬(Under Ball Metal,UBM)層而形成。然而，在其他實施例中，該球下金屬層包括一銅層、一鎳層及一錫/銀合金層。在另一實施例中，該球下金屬層係可以鋁/鎳/金(Al/Ni/Au)、鋁/釩化鎳/銅(Al/NiV/Cu)、銅/鎳/金(Cu/Ni/Au)、銅/鎳/鈀(Cu/Ni/Pd)、銅/鉻/鋁(Cu/Cr/Al)或鈦/鋁/鈦/釩化鎳(Ti/Al/Ti/NiV)形成。In this embodiment, the first back ball under the metal pad 17, the second The back ball under metal pad 19 and the first back ball under metal plane 18 are formed by selectively patterning a under ball metal including a copper layer, a nickel layer, a palladium layer and a gold layer (Under Ball Metal, UBM) layer is formed. However, in other embodiments, the under-ball metal layer comprises a copper layer, a nickel layer, and a tin/silver alloy layer. In another embodiment, the under-metal layer may be aluminum/nickel/gold (Al/Ni/Au), aluminum/vanadium nickel/copper (Al/NiV/Cu), copper/nickel/gold (Cu/ Ni/Au), copper/nickel/palladium (Cu/Ni/Pd), copper/chromium/aluminum (Cu/Cr/Al) or titanium/aluminum/titanium/vanadium nickel (Ti/Al/Ti/NiV) .

在本實施例中，該半導體基板10之背面102上之結構係與該半導體基板10之正面101上之結構相同。該半導體裝置1更包括一正面鈍化層23、複數個第一正面重佈層24、至少一第二正面重佈層25、一正面介電層26、複數個第一正面球下金屬銲墊27及一第一正面球下金屬平面28。In the present embodiment, the structure on the back surface 102 of the semiconductor substrate 10 is the same as that on the front surface 101 of the semiconductor substrate 10. The semiconductor device 1 further includes a front passivation layer 23, a plurality of first front redistribution layers 24, at least one second front redistribution layer 25, a front dielectric layer 26, and a plurality of first front under-ball metal pads 27 And a first frontal ball under the metal plane 28.

該正面鈍化層23係位於該半導體基板10之正面101，且具有複數個開口以顯露該等第一導通柱11及該第二導通柱12之末端。The front passivation layer 23 is located on the front side 101 of the semiconductor substrate 10 and has a plurality of openings to expose the ends of the first via posts 11 and the second via posts 12 .

該等第一正面重佈層24係位於該正面鈍化層23之該等開口內及部分該正面鈍化層23上，以接觸且電性連接該等第一導通柱11。該第二正面重佈層25係位於該正面鈍化層23之該等開口內及部分該正面鈍化層23上，以接觸且電性連接該第二導通柱12。The first front redistribution layer 24 is located in the openings of the front passivation layer 23 and on the portion of the front passivation layer 23 to contact and electrically connect the first via posts 11 . The second frontmost redistribution layer 25 is located in the openings of the front passivation layer 23 and on the portion of the front passivation layer 23 to contact and electrically connect the second via posts 12 .

該正面介電層26係與該正面101位於同一側。在本實施例中，該正面介電層26係位於該等第一正面重佈層24、該第二正面重佈層25及該正面鈍化層23下方。該正面介電層26具有複數個第一開口261及至少一第二開口262，以分別顯露部分該等第一正面重佈層24及該第二正面重佈層25。The front dielectric layer 26 is on the same side as the front surface 101. In this embodiment, the front dielectric layer 26 is located below the first front redistribution layer 24 , the second front redistribution layer 25 , and the front passivation layer 23 . The front dielectric layer 26 has a plurality of first openings 261 and at least one second opening 262 to respectively expose portions of the first front redistribution layer 24 and the second front redistribution layer 25.

該等第一正面球下金屬銲墊27係位於該等第一開口261內及部分該正面介電層26上，且電性連接至該等第一導通柱11。該第一正面球下金屬平面28係位於該正面介電層26上，且電性連接至該至少一第二導通柱12。該第一正面球下金屬平面28係顯露於空氣中且具有複數個穿孔281。該等第一正面球下金屬銲墊27係設置於該等穿孔281內。該第一正面球下金屬平面28及該等第一正面球下金屬銲墊27之間具有一間距(Gap)282。亦即，該第一正面球下金屬平面28並未接觸該等第一正面球下金屬銲墊27。The first front under-ball metal pads 27 are located in the first openings 261 and on the portion of the front dielectric layer 26 and are electrically connected to the first via posts 11 . The first front under-ball metal plane 28 is located on the front dielectric layer 26 and electrically connected to the at least one second via post 12 . The first front under-ball metal plane 28 is exposed to the air and has a plurality of perforations 281. The first front under-ball metal pads 27 are disposed within the perforations 281. There is a gap (Gap) 282 between the first front under-ball metal plane 28 and the first front under-ball metal pads 27. That is, the first front under-ball metal plane 28 does not contact the first front under-ball metal pads 27.

在本實施例中，該半導體裝置1更包括至少一第二正面球下金屬銲墊29。該第二正面球下金屬銲墊29係位於該第二開口262內及該正面介電層26上，且電性連接至該第二導通柱12。該第一正面球下金屬平面28係透過該第二正面球下金屬銲墊29電性連接至該第二導通柱12。In this embodiment, the semiconductor device 1 further includes at least one second front under-ball metal pad 29 . The second front under-ball metal pad 29 is located in the second opening 262 and on the front dielectric layer 26 and is electrically connected to the second via post 12 . The first front under-ball metal plane 28 is electrically connected to the second via post 12 through the second front under-ball metal pad 29 .

參考圖3，其顯示沿著圖1之線3-3之剖面示意圖。在本實施例中，該半導體裝置1更包括至少一第三導通柱12a及一第二背面球下金屬平面18a。該第三導通柱12a係位於該半導體基板10內且被一第三內襯121a所圍繞。該第二背面球下金屬平面18a係位於該背面介電層16上且電性連接至該第三導通柱12a。該第二背面球下金屬平面18a係顯露於空氣中且並未連接該第一背面球下金屬平面18。該第二背面球下金屬平面18a及該第一背面球下金屬平面18之間具有一狹縫184。Referring to Figure 3, a cross-sectional view taken along line 3-3 of Figure 1 is shown. In this embodiment, the semiconductor device 1 further includes at least one third via post 12a and a second back ball under metal plane 18a. The third via post 12a is located within the semiconductor substrate 10 and is surrounded by a third liner 121a. The second back ball under metal plane 18a is located on the back dielectric layer 16 and is electrically connected to the third via post 12a. The second back ball under metal plane 18a is exposed to the air and is not connected to the first back ball under metal plane 18. A slit 184 is defined between the second back ball under metal plane 18a and the first back ball under metal plane 18.

在本實施例中，該第二背面球下金屬銲墊19b係位於該第二開口162內及該背面介電層16上，且電性連接至該第三導通柱12a。該第二背面球下金屬平面18a係透過該第二背面球下金屬銲墊19b及該第二背面重佈層15電性連接至該第三導通柱12a。在本實施例中，該半導體裝置1更包括至少一跡線183a連接該第二背面球下金屬銲墊19b至該第二背面球下金屬平面18a。In this embodiment, the second back ball under metal pad 19b is located in the second opening 162 and the back dielectric layer 16, and is electrically connected to the third via 12a. The second back ball under metal plane 18a is electrically connected to the third via post 12a through the second back ball under metal pad 19b and the second back layer redistribution layer 15a. In this embodiment, the semiconductor device 1 further includes at least one trace 183a connecting the second back under ball metal pad 19b to the second back ball under metal plane 18a.

在本實施例中，該等第一背面球下金屬銲墊17、該第一背面球下金屬平面18、該等第二背面球下金屬銲墊19,19a,19b、該第二背面球下金屬平面18a及該等跡線183,183a係位於該半導體裝置1之最外層，且以一球下金屬層製程形成。因此，形成該等第一背面球下金屬銲墊17、該第一背面球下金屬平面18、該等第二背面球下金屬銲墊19,19a,19b、該第二背面球下金屬平面18a及該等跡線183,183a的成本較低。此外，該第一背面球下金屬平面18及該第二背面球下金屬平面18a其中之一係可為一接地平面或一電源平面。或者，該第一背面球下金屬平面18及該第二背面球下金屬平面18a係可皆為接地平面或皆為電源平面。因為該第一背面球下金屬平面18及該第二背面球下金屬平面18a係位於最外層，而得以維持電氣性能之信號完整性及電源完整性。In this embodiment, the first back ball under metal pad 17, the first back ball under metal plane 18, the second back ball under the metal pads 19, 19a, 19b, the second back ball The metal plane 18a and the traces 183, 183a are located at the outermost layer of the semiconductor device 1, and are formed by a ball under metal layer process. Therefore, the first back ball under metal pad 17 , the first back ball under metal plane 18 , the second back ball under the metal pads 19 , 19 a , 19 b , and the second back ball under the metal plane 18 a are formed. And the cost of the traces 183, 183a is lower. In addition, one of the first back ball sub-metal plane 18 and the second back ball sub-metal plane 18a may be a ground plane or a power plane. Alternatively, the first back ball under metal plane 18 and the second back ball under metal plane 18a may both be ground planes or both are power planes. Because the first back ball under metal plane 18 and the second back ball under metal plane 18a are located at the outermost layer, the signal integrity and power integrity of the electrical performance are maintained.

參考圖4，其顯示本發明第二實施例之半導體裝置之剖面示意圖。第二實施例之半導體裝置2係與第一實施例之半導體裝置1(圖1至圖3)大致相同，除了如下所述之該半導體基板10之正面101上之結構。該半導體裝置2更包括一個或多個佈線層30、複數個銲墊31及複數個外部連接元件32(例如，銅柱或凸塊)。該一個或多個佈線層30係位於該半導體基板10之正面101。該等佈線層30包括至少一介電層及至少一導線。該導線係位於該介電層內。該導線係可以銅、銅合金或其他導電金屬形成，且可利用習知的嵌入製程形成。此外，該等佈線層30可包括習知的層間介電層(Inter-layer Dielectric,ILD)及金屬間介電層(Inter-metal Dielectric,IMD)。Referring to Figure 4, there is shown a schematic cross-sectional view of a semiconductor device in accordance with a second embodiment of the present invention. The semiconductor device 2 of the second embodiment is substantially the same as the semiconductor device 1 (Figs. 1 to 3) of the first embodiment except for the structure on the front surface 101 of the semiconductor substrate 10 as described below. The semiconductor device 2 further includes one or more wiring layers 30, a plurality of pads 31, and a plurality of external connection elements 32 (eg, copper posts or bumps). The one or more wiring layers 30 are located on the front side 101 of the semiconductor substrate 10. The wiring layers 30 include at least one dielectric layer and at least one wire. The wire is located within the dielectric layer. The wire can be formed from copper, copper alloy or other conductive metal and can be formed using conventional embedding processes. In addition, the wiring layers 30 may include a conventional Inter-layer Dielectric (ILD) and an Inter-metal Dielectric (IMD).

該等銲墊31係位於該一個或多個佈線層30上，且分別電性連接至該等第一導通柱11及該第二導通柱12。該等外部連接元件32係為分別位於該等銲墊31上。可以理解的是，該外部連接元件32並非本發明之必要層面。如果省略該等外部連接元件32，則可顯露該等銲墊31以達成外部連接。The pads 31 are located on the one or more wiring layers 30 and electrically connected to the first via posts 11 and the second via posts 12, respectively. The external connection elements 32 are located on the pads 31, respectively. It will be appreciated that the external connection element 32 is not a necessary aspect of the invention. If the external connection elements 32 are omitted, the pads 31 can be exposed to achieve an external connection.

參考圖5，其顯示本發明第三實施例之半導體裝置之剖面示意圖。第三實施例之半導體裝置3係與第一實施例之半導體裝置1(圖1至圖3)大致相同，除了該等第一導通柱11及該第二導通柱12之結構。在該半導體裝置3中，該等第一導通柱11、該第一內襯111、該第二導通柱12及該第二內襯121突出於該背面102及該背面鈍化層13。同樣地，該等第一導通柱11、該第一內襯111、該第二導通柱12及該第二內襯121突出於該正面101及該正面鈍化層23。Referring to Figure 5, there is shown a schematic cross-sectional view of a semiconductor device in accordance with a third embodiment of the present invention. The semiconductor device 3 of the third embodiment is substantially the same as the semiconductor device 1 (FIGS. 1 to 3) of the first embodiment except for the structures of the first via posts 11 and the second via posts 12. In the semiconductor device 3, the first vias 11, the first liner 111, the second vias 12, and the second liner 121 protrude from the back surface 102 and the back passivation layer 13. Similarly, the first conductive pillars 11 , the first inner liner 111 , the second conductive pillars 12 , and the second inner liner 121 protrude from the front surface 101 and the front passivation layer 23 .

參考圖6，其顯示本發明第四實施例之半導體裝置之剖面示意圖。第四實施例之半導體裝置4係與第三實施例之半導體裝置3(圖5)大致相同，除了如下所述之該半導體基板10之正面101上之結構。該半導體裝置4更包括一個或多個佈線層40、複數個銲墊41及複數個外部連接元件42(例如，銅柱或凸塊)。該一個或多個佈線層40係位於該半導體基板10之正面101。該等銲墊41係位於該一個或多個佈線層40上，且分別電性連接至該等第一導通柱11及該第二導通柱12。該等外部連接元件42係為分別位於該等銲墊41上。Referring to Figure 6, there is shown a schematic cross-sectional view of a semiconductor device in accordance with a fourth embodiment of the present invention. The semiconductor device 4 of the fourth embodiment is substantially the same as the semiconductor device 3 (FIG. 5) of the third embodiment except for the structure on the front surface 101 of the semiconductor substrate 10 as described below. The semiconductor device 4 further includes one or more wiring layers 40, a plurality of pads 41, and a plurality of external connection elements 42 (eg, copper posts or bumps). The one or more wiring layers 40 are located on the front side 101 of the semiconductor substrate 10. The pads 41 are located on the one or more wiring layers 40 and electrically connected to the first via posts 11 and the second via posts 12, respectively. The external connecting elements 42 are located on the pads 41, respectively.

參考圖7，其顯示本發明第五實施例之半導體裝置之俯視圖。參考圖8，其顯示沿著圖7之線8-8之剖面示意圖。第五實施例之半導體裝置5係與第一實施例之半導體裝置1(圖1至圖3)大致相同，除了該半導體裝置5並未包括該等第一導通柱11及該第二導通柱12，且該半導體裝置5係為一主動晶片。Referring to Figure 7, there is shown a plan view of a semiconductor device in accordance with a fifth embodiment of the present invention. Referring to Figure 8, a cross-sectional view taken along line 8-8 of Figure 7 is shown. The semiconductor device 5 of the fifth embodiment is substantially the same as the semiconductor device 1 (FIGS. 1 to 3) of the first embodiment except that the semiconductor device 5 does not include the first via posts 11 and the second via posts 12 And the semiconductor device 5 is an active wafer.

該半導體裝置5包括一半導體基板50、複數個訊號銲墊51、至少一電源或接地銲墊52、一絕緣層503、一鈍化層53、複數個第一重佈層54、至少一第二重佈層55、一介電層56、複數個第一球下金屬銲墊57及一第一球下金屬平面58。The semiconductor device 5 includes a semiconductor substrate 50, a plurality of signal pads 51, at least one power or ground pad 52, an insulating layer 503, a passivation layer 53, a plurality of first redistribution layers 54, and at least a second weight. The layer 55, a dielectric layer 56, a plurality of first under-ball metal pads 57 and a first under-ball metal plane 58.

該半導體基板50具有一表面502(主動面)。該等訊號銲墊51及該電源或接地銲墊52係鄰接於該半導體基板50之表面502。The semiconductor substrate 50 has a surface 502 (active surface). The signal pads 51 and the power or ground pads 52 are adjacent to the surface 502 of the semiconductor substrate 50.

該絕緣層503係位於該半導體基板50之表面502，且具有複數個開口以顯露該等訊號銲墊51及該電源或接地銲墊52。該鈍化層53係位於該絕緣層503上，且具有複數個開口以顯露該等訊號銲墊51及該電源或接地銲墊52。該等第一重佈層54係位於該鈍化層53之該等開口內及部分該鈍化層53上，以接觸且電性連接該等訊號銲墊51。該第二重佈層55係位於該鈍化層53之該等開口內及部分該鈍化層53上，以接觸且電性連接該電源或接地銲墊52。The insulating layer 503 is located on the surface 502 of the semiconductor substrate 50 and has a plurality of openings to expose the signal pads 51 and the power or ground pads 52. The passivation layer 53 is disposed on the insulating layer 503 and has a plurality of openings to expose the signal pads 51 and the power or ground pads 52. The first redistribution layer 54 is located in the openings of the passivation layer 53 and partially on the passivation layer 53 to contact and electrically connect the signal pads 51. The second redistribution layer 55 is located in the openings of the passivation layer 53 and partially on the passivation layer 53 to contact and electrically connect the power source or the ground pad 52.

該介電層56係與該表面502位於同一側。在本實施例中，該介電層56係位於該等第一重佈層54、該第二重佈層55及該鈍化層53上方。該介電層56具有複數個第一開口561及至少一第二開口562，以分別顯露部分該等第一重佈層54及該第二重佈層55。The dielectric layer 56 is on the same side as the surface 502. In this embodiment, the dielectric layer 56 is located above the first redistribution layer 54, the second redistribution layer 55, and the passivation layer 53. The dielectric layer 56 has a plurality of first openings 561 and at least one second opening 562 to respectively expose portions of the first redistribution layer 54 and the second redistribution layer 55.

該等第一球下金屬銲墊57係位於該等第一開口561內及部分該介電層56上，且電性連接至該等訊號銲墊51。該第一球下金屬平面58係位於該介電層56上，且電性連接至該電源或接地銲墊52。該第一球下金屬平面58之面積係大於每一該等第一球下金屬銲墊57之面積。該第一球下金屬平面58係顯露於空氣中且具有複數個穿孔581。該等第一球下金屬銲墊57係設置於該等穿孔581內。該第一球下金屬平面58及該等第一球下金屬銲墊57之間具有一間距582。亦即，該第一球下金屬平面58並未接觸該等第一球下金屬銲墊57。The first under-metal pads 57 are located in the first openings 561 and on the portion of the dielectric layer 56 and are electrically connected to the signal pads 51. The first under-ball metal plane 58 is located on the dielectric layer 56 and is electrically connected to the power or ground pad 52. The area of the first under-ball metal plane 58 is greater than the area of each of the first under-ball metal pads 57. The first under-ball metal plane 58 is exposed to the air and has a plurality of perforations 581. The first under-ball metal pads 57 are disposed within the vias 581. The first under-ball metal plane 58 and the first under-ball metal pads 57 have a spacing 582 therebetween. That is, the first under-ball metal plane 58 does not contact the first under-ball metal pads 57.

在本實施例中，該半導體裝置5更包括至少一第二球下金屬銲墊59。該第二球下金屬銲墊59係位於該第二開口562內及該介電層56上，且電性連接至該電源或接地銲墊52。該第一球下金屬平面58係透過該第二球下金屬銲墊59電性連接至該電源或接地銲墊52。In this embodiment, the semiconductor device 5 further includes at least one second under-ball metal pad 59. The second under-ball metal pad 59 is located in the second opening 562 and on the dielectric layer 56 , and is electrically connected to the power or ground pad 52 . The first under-ball metal plane 58 is electrically connected to the power or ground pad 52 through the second under-ball metal pad 59.

在本實施例中，該半導體裝置5更包括至少一跡線583連接該第二球下金屬銲墊59a至該第一球下金屬平面58。In this embodiment, the semiconductor device 5 further includes at least one trace 583 connecting the second under-ball metal pad 59a to the first under-ball metal plane 58.

參考圖9，其顯示本發明第六實施例之半導體封裝結構之剖面示意圖。該半導體封裝結構6包括該半導體裝置1、一上晶粒60及一底膠(Underfill)62。該半導體裝置1係與第一實施例之半導體裝置1(圖1至圖3)相同，且包括該半導體基板10、該等第一導通柱11、該第二導通柱12、該背面鈍化層13、該等第一背面重佈層14、該第二背面重佈層15、該背面介電層16、該等第一背面球下金屬銲墊17及該第一背面球下金屬平面18。Referring to Figure 9, there is shown a cross-sectional view of a semiconductor package structure in accordance with a sixth embodiment of the present invention. The semiconductor package structure 6 includes the semiconductor device 1, an upper die 60, and an underfill 62. The semiconductor device 1 is the same as the semiconductor device 1 (FIGS. 1 to 3) of the first embodiment, and includes the semiconductor substrate 10, the first via posts 11, the second via posts 12, and the back passivation layer 13. The first back redistribution layer 14 , the second back redistribution layer 15 , the back dielectric layer 16 , the first back ball under metal pads 17 , and the first back ball under metal plane 18 .

該上晶粒60係位於該半導體裝置1上，且具有複數個上連接元件61於其一表面(底面)上。該等上連接元件61(例如，銲球)係分別連接至該等第一背面球下金屬銲墊17，且該等上連接元件61至少其中之一係電性連接至該第一背面球下金屬平面18。在本實施例中，該等上連接元件61至少其中之一接觸該第二背面球下金屬銲墊19。該底膠62係位於該上晶粒60及該半導體裝置1之間，以保護該等上連接元件61。應注意的是，該半導體裝置1係可以該等半導體裝置2(圖4),3(圖5),4(圖6)取代。The upper die 60 is located on the semiconductor device 1 and has a plurality of upper connecting members 61 on one surface (bottom surface) thereof. The upper connecting elements 61 (eg, solder balls) are respectively connected to the first back ball under metal pads 17 , and at least one of the upper connecting elements 61 is electrically connected to the first back ball Metal plane 18. In this embodiment, at least one of the upper connecting members 61 contacts the second back ball under the metal pad 19. The primer 62 is located between the upper die 60 and the semiconductor device 1 to protect the upper connecting members 61. It should be noted that the semiconductor device 1 can be replaced by the semiconductor devices 2 (Fig. 4), 3 (Fig. 5), and 4 (Fig. 6).

參考圖10，其顯示本發明第七實施例之半導體封裝結構之剖面示意圖。該半導體封裝結構7包括該半導體裝置1、該上晶粒60、該底膠62、一下基板70、複數個下連接元件72及一封膠材料80。該半導體裝置1、該上晶粒60及該底膠62係與第六實施例之半導體封裝結構6(圖9)相同。該下基板70具有一頂面701、一底面702、複數個上銲墊71、複數個下銲墊73及複數個銲球74。該等上銲墊71係位於該頂面701，且該等下銲墊73係位於該底面702。該等下連接元件72連接該等上銲墊71、該等第一正面球下金屬銲墊27及該第一正面球下金屬平面28，以連接該下基板70及該半導體裝置1。在本實施例中，該等下連接元件72至少其中之一接觸該第二正面球下金屬銲墊29。該封膠材料80包覆該下基板70、該半導體裝置1及該上晶粒60。應注意的是，該半導體裝置1係可以該等半導體裝置2(圖4),3(圖5),4(圖6)取代。該等銲球74係位於該等下銲墊73上。Referring to Figure 10, there is shown a cross-sectional view of a semiconductor package structure in accordance with a seventh embodiment of the present invention. The semiconductor package structure 7 includes the semiconductor device 1, the upper die 60, the primer 62, the lower substrate 70, a plurality of lower connecting members 72, and an adhesive material 80. The semiconductor device 1, the upper die 60, and the primer 62 are the same as the semiconductor package structure 6 (FIG. 9) of the sixth embodiment. The lower substrate 70 has a top surface 701, a bottom surface 702, a plurality of upper pads 71, a plurality of lower pads 73, and a plurality of solder balls 74. The upper pads 71 are located on the top surface 701, and the lower pads 73 are located on the bottom surface 702. The lower connecting elements 72 are connected to the upper pads 71, the first front under-ball metal pads 27 and the first front under-ball metal plane 28 to connect the lower substrate 70 and the semiconductor device 1. In this embodiment, at least one of the lower connecting members 72 contacts the second front under-ball metal pad 29. The encapsulant 80 covers the lower substrate 70, the semiconductor device 1 and the upper die 60. It should be noted that the semiconductor device 1 can be replaced by the semiconductor devices 2 (Fig. 4), 3 (Fig. 5), and 4 (Fig. 6). The solder balls 74 are located on the lower pads 73.

惟上述實施例僅為說明本發明之原理及其功效，而非用以限制本發明。因此，習於此技術之人士對上述實施例進行修改及變化仍不脫本發明之精神。本發明之權利範圍應如後述之申請專利範圍所列。However, the above embodiments are merely illustrative of the principles and effects of the invention and are not intended to limit the invention. Therefore, those skilled in the art can make modifications and changes to the above embodiments without departing from the spirit of the invention. The scope of the invention should be as set forth in the appended claims.

1．．．本發明第一實施例之半導體裝置1. . . Semiconductor device of the first embodiment of the present invention

2．．．本發明第二實施例之半導體裝置2. . . Semiconductor device of a second embodiment of the present invention

3．．．本發明第三實施例之半導體裝置3. . . Semiconductor device of a third embodiment of the present invention

4．．．本發明第四實施例之半導體裝置4. . . Semiconductor device of a fourth embodiment of the present invention

5．．．本發明第五實施例之半導體裝置5. . . Semiconductor device of a fifth embodiment of the present invention

6．．．本發明第六實施例之半導體封裝結構6. . . Semiconductor package structure of a sixth embodiment of the present invention

7．．．本發明第七實施例之半導體封裝結構7. . . Semiconductor package structure of a seventh embodiment of the present invention

10．．．半導體基板10. . . Semiconductor substrate

11．．．第一導通柱11. . . First conduction post

12．．．第二導通柱12. . . Second conduction column

12a．．．第三導通柱12a. . . Third conducting column

13．．．背面鈍化層13. . . Back passivation layer

14．．．第一背面重佈層14. . . First back redistribution

15．．．第二背面重佈層15. . . Second back re-layer

16．．．背面介電層16. . . Back dielectric layer

17．．．第一背面球下金屬銲墊17. . . First back ball under metal pad

18．．．第一背面球下金屬平面18. . . First back ball under the metal plane

18a．．．第二背面球下金屬平面18a. . . Second back ball under the metal plane

19．．．第二背面球下金屬銲墊19. . . Second back ball under metal pad

19a．．．第二背面球下金屬銲墊19a. . . Second back ball under metal pad

19b．．．第二背面球下金屬銲墊19b. . . Second back ball under metal pad

23．．．正面鈍化層twenty three. . . Front passivation layer

24．．．第一正面重佈層twenty four. . . First frontal redistribution

25．．．第二正面重佈層25. . . Second frontal redistribution

26．．．正面介電層26. . . Front dielectric layer

27．．．第一正面球下金屬銲墊27. . . First front ball under metal pad

28．．．第一正面球下金屬平面28. . . First frontal ball under the metal plane

29．．．第二正面球下金屬銲墊29. . . Second front ball under metal pad

30．．．佈線層30. . . Wiring layer

31．．．銲墊31. . . Solder pad

32．．．外部連接元件32. . . External connection element

40．．．佈線層40. . . Wiring layer

41．．．銲墊41. . . Solder pad

42．．．外部連接元件42. . . External connection element

50．．．半導體基板50. . . Semiconductor substrate

51．．．訊號銲墊51. . . Signal pad

52．．．電源或接地銲墊52. . . Power or ground pad

53．．．鈍化層53. . . Passivation layer

54．．．第一重佈層54. . . First redistribution layer

55．．．第二重佈層55. . . Second redistribution

56．．．介電層56. . . Dielectric layer

57．．．第一球下金屬銲墊57. . . First ball under metal pad

58．．．第一球下金屬平面58. . . First ball under metal plane

59．．．第二球下金屬銲墊59. . . Second ball under metal pad

59a．．．第二球下金屬銲墊59a. . . Second ball under metal pad

60．．．上晶粒60. . . Upper grain

61．．．上連接元件61. . . Upper connecting element

62．．．底膠62. . . Primer

70．．．下基板70. . . Lower substrate

71．．．上銲墊71. . . Upper pad

72．．．下連接元件72. . . Lower connecting element

73．．．下銲墊73. . . Lower pad

74．．．銲球74. . . Solder ball

80．．．封膠材料80. . . Sealing material

101．．．正面101. . . positive

102．．．背面102. . . back

111．．．第一內襯111. . . First lining

121．．．第二內襯121. . . Second lining

121a．．．第三內襯121a. . . Third lining

161．．．第一開口161. . . First opening

162．．．第二開口162. . . Second opening

181．．．穿孔181. . . perforation

182．．．間距182. . . spacing

183．．．跡線183. . . Trace

183a．．．跡線183a. . . Trace

184．．．狹縫184. . . Slit

261．．．第一開口261. . . First opening

262．．．第二開口262. . . Second opening

281．．．穿孔281. . . perforation

282．．．間距282. . . spacing

502．．．表面502. . . surface

503．．．絕緣層503. . . Insulation

561．．．第一開口561. . . First opening

562．．．第二開口562. . . Second opening

581．．．穿孔581. . . perforation

582．．．間距582. . . spacing

583．．．跡線583. . . Trace

701．．．頂面701. . . Top surface

702．．．底面702. . . Bottom

圖1顯示本發明第一實施例之半導體裝置之俯視圖；1 is a plan view showing a semiconductor device according to a first embodiment of the present invention;

圖2顯示沿著圖1之線2-2之剖面示意圖；Figure 2 shows a schematic cross-sectional view along line 2-2 of Figure 1;

圖3顯示沿著圖1之線3-3之剖面示意圖；Figure 3 shows a schematic cross-sectional view along line 3-3 of Figure 1;

圖4顯示本發明第二實施例之半導體裝置之剖面示意圖；4 is a cross-sectional view showing a semiconductor device according to a second embodiment of the present invention;

圖5顯示本發明第三實施例之半導體裝置之剖面示意圖；Figure 5 is a cross-sectional view showing a semiconductor device according to a third embodiment of the present invention;

圖6顯示本發明第四實施例之半導體裝置之剖面示意圖；6 is a cross-sectional view showing a semiconductor device according to a fourth embodiment of the present invention;

圖7顯示本發明第五實施例之半導體裝置之俯視圖：Figure 7 is a plan view showing a semiconductor device according to a fifth embodiment of the present invention:

圖8顯示沿著圖7之線8-8之剖面示意圖；Figure 8 is a cross-sectional view taken along line 8-8 of Figure 7;

圖9顯示本發明第六實施例之半導體封裝結構之剖面示意圖；及FIG. 9 is a cross-sectional view showing a semiconductor package structure according to a sixth embodiment of the present invention; and

圖10顯示本發明第七實施例之半導體封裝結構之剖面示意圖。Figure 10 is a cross-sectional view showing a semiconductor package structure of a seventh embodiment of the present invention.

1．．．本發明第一實施例之半導體裝置1. . . Semiconductor device of the first embodiment of the present invention

10．．．半導體基板10. . . Semiconductor substrate

11．．．第一導通柱11. . . First conduction post

12．．．第二導通柱12. . . Second conduction column

13．．．背面鈍化層13. . . Back passivation layer

14．．．第一背面重佈層14. . . First back redistribution

15．．．第二背面重佈層15. . . Second back re-layer

16．．．背面介電層16. . . Back dielectric layer

17．．．第一背面球下金屬銲墊17. . . First back ball under metal pad

18．．．第一背面球下金屬平面18. . . First back ball under the metal plane

19．．．第二背面球下金屬銲墊19. . . Second back ball under metal pad

23．．．正面鈍化層twenty three. . . Front passivation layer

24．．．第一正面重佈層twenty four. . . First frontal redistribution

25．．．第二正面重佈層25. . . Second frontal redistribution

26．．．正面介電層26. . . Front dielectric layer

27．．．第一正面球下金屬銲墊27. . . First front ball under metal pad

28．．．第一正面球下金屬平面28. . . First frontal ball under the metal plane

29．．．第二正面球下金屬銲墊29. . . Second front ball under metal pad

101．．．正面101. . . positive

102．．．背面102. . . back

111．．．第一內襯111. . . First lining

121．．．第二內襯121. . . Second lining

161．．．第一開口161. . . First opening

162．．．第二開口162. . . Second opening

181．．．穿孔181. . . perforation

182．．．間距182. . . spacing

261．．．第一開口261. . . First opening

262．．．第二開口262. . . Second opening

281．．．穿孔281. . . perforation

282．．．間距282. . . spacing

Claims (15)

一種半導體裝置，包括：一半導體基板，具有一正面及一背面；複數個第一導通柱，位於該半導體基板內，每一該等第一導通柱係被一第一內襯(Liner)所圍繞；至少一第二導通柱，位於該半導體基板內且被一第二內襯所圍繞；一背面介電層，與該背面位於同一側；複數個第一背面球下金屬(Under Ball Metal,UBM)銲墊，位於該背面介電層上且電性連接至該等第一導通柱；及一第一背面球下金屬平面，位於該背面介電層上且電性連接至該至少一第二導通柱，其中該第一背面球下金屬平面具有複數個穿孔，該等第一背面球下金屬銲墊係設置於該等穿孔內，且該第一背面球下金屬平面及該等第一背面球下金屬銲墊之間具有一間距(Gap)。 A semiconductor device comprising: a semiconductor substrate having a front surface and a back surface; a plurality of first conductive pillars located in the semiconductor substrate, each of the first conductive pillars being surrounded by a first liner At least one second via post is located in the semiconductor substrate and surrounded by a second liner; a back dielectric layer is on the same side as the back surface; and a plurality of first back ball metal (Under Ball Metal, UBM) a solder pad on the back dielectric layer and electrically connected to the first via posts; and a first back ball under metal plane on the back dielectric layer and electrically connected to the at least one second a conductive pillar, wherein the first back ball under the metal plane has a plurality of through holes, the first back ball under metal pads are disposed in the through holes, and the first back ball under the metal plane and the first back There is a gap (Gap) between the under-metal pads. 如請求項1之半導體裝置，更包括：一背面鈍化層(Passivation)，位於該半導體基板之背面且顯露該等第一導通柱及該第二導通柱之末端；複數個第一背面重佈層(Redistribution Layer,RDL)，位於該背面鈍化層上且電性連接至該等第一導通柱；至少一第二背面重佈層，位於該背面鈍化層上且電性連接至該至少一第二導通柱，其中該背面介電層係位於該等第一背面重佈層、該第二背面重佈層及該背面鈍化 層上方，該背面介電層具有複數個第一開口及至少一第二開口以分別顯露部分該等第一背面重佈層及該第二背面重佈層，且該等第一背面球下金屬銲墊係位於該等第一開口內；至少一第二背面球下金屬銲墊，位於該至少一第二開口內及該背面介電層上；及至少一跡線(Trace)，連接該至少一第二背面球下金屬銲墊至該第一背面球下金屬平面，其中該第一背面球下金屬平面係透過該至少一第二背面球下金屬銲墊電性連接至該至少一第二導通柱。 The semiconductor device of claim 1, further comprising: a back passivation layer on the back side of the semiconductor substrate and exposing the ends of the first via post and the second via post; the plurality of first back re-layers a (Redistribution Layer, RDL) on the back passivation layer and electrically connected to the first via posts; at least one second back redistribution layer on the back passivation layer and electrically connected to the at least one second a via pillar, wherein the back dielectric layer is located on the first back redistribution layer, the second back redistribution layer, and the backside passivation layer Above the layer, the back dielectric layer has a plurality of first openings and at least one second opening to respectively expose a portion of the first back redistribution layer and the second back redistribution layer, and the first back ball under the metal a solder pad is disposed in the first openings; at least one second back ball under metal pad is disposed in the at least one second opening and the back dielectric layer; and at least one trace is connected to the at least one trace a second back ball under the metal pad to the first back ball under metal plane, wherein the first back ball under metal plane is electrically connected to the at least one second through the at least one second back ball under metal pad Conduction column. 如請求項1之半導體裝置，其中該等第一導通柱、該第一內襯、該至少一第二導通柱及該第二內襯突出於該背面。 The semiconductor device of claim 1, wherein the first conductive pillars, the first inner liner, the at least one second conductive pillar, and the second inner liner protrude from the back surface. 如請求項1之半導體裝置，更包括：至少一第三導通柱，位於該半導體基板內且被一第三內襯所圍繞；及一第二背面球下金屬平面，位於該背面介電層上且電性連接至該至少一第三導通柱，其中該第二背面球下金屬平面並未連接該第一背面球下金屬平面。 The semiconductor device of claim 1, further comprising: at least one third via post located in the semiconductor substrate and surrounded by a third liner; and a second back ball under metal plane on the back dielectric layer And electrically connected to the at least one third via post, wherein the second back ball under metal plane is not connected to the first back ball under metal plane. 如請求項1之半導體裝置，更包括：一正面介電層，與該正面位於同一側；複數個第一正面球下金屬銲墊，位於該正面介電層上且電性連接至該等第一導通柱；及一第一正面球下金屬平面，位於該正面介電層上且電 性連接至該至少一第二導通柱，其中該第一正面球下金屬平面具有複數個穿孔，該等第一正面球下金屬銲墊係設置於該等穿孔內，且該第一正面球下金屬平面及該等第一正面球下金屬銲墊之間具有一間距。 The semiconductor device of claim 1, further comprising: a front dielectric layer on the same side as the front surface; a plurality of first front under-ball metal pads on the front dielectric layer and electrically connected to the first a conductive pillar; and a first frontal ball under the metal plane, located on the front dielectric layer and electrically Connected to the at least one second conductive post, wherein the first front under-ball metal plane has a plurality of through holes, and the first front under-ball metal pads are disposed in the through holes, and the first front ball is under the ball There is a spacing between the metal plane and the first front ball under metal pads. 如請求項5之半導體裝置，更包括：一正面鈍化層，位於該半導體基板之正面且顯露該等第一導通柱及該第二導通柱之末端；複數個第一正面重佈層，位於該正面鈍化層上且電性連接至該等第一導通柱；至少一第二正面重佈層，位於該正面鈍化層上且電性連接至該至少一第二導通柱，其中該正面介電層係位於該等第一正面重佈層、該第二正面重佈層及該正面鈍化層上方，該正面介電層具有複數個第一開口及至少一第二開口以分別顯露部分該等第一正面重佈層及該第二正面重佈層，且該等第一正面球下金屬銲墊係位於該等第一開口內；及至少一第二正面球下金屬銲墊，位於該至少一第二開口內及該正面介電層上，其中該第一正面球下金屬平面係透過該至少一第二正面球下金屬銲墊電性連接至該至少一第二導通柱。 The semiconductor device of claim 5, further comprising: a front passivation layer on the front side of the semiconductor substrate and exposing the ends of the first conductive pillars and the second conductive pillars; and a plurality of first frontal redistribution layers And a front surface of the first pass-through layer; The first front redistribution layer, the second front redistribution layer and the front passivation layer are disposed, the front dielectric layer has a plurality of first openings and at least one second opening to respectively expose portions of the first a front redistribution layer and the second front redistribution layer, wherein the first front under-ball metal pads are located in the first openings; and at least one second front-ball under-metal pad is located in the at least one The first front under-ball metal plane is electrically connected to the at least one second via post through the at least one second front under-ball metal pad. 如請求項1之半導體裝置，其中該第一背面球下金屬平面係為一接地平面或一電源平面。 The semiconductor device of claim 1, wherein the first back ball sub-metal plane is a ground plane or a power plane. 一種半導體封裝結構，包括：一半導體裝置，包括： 一半導體基板，具有一正面及一背面；複數個第一導通柱，位於該半導體基板內，每一該等第一導通柱係被一第一內襯所圍繞；至少一第二導通柱，位於該半導體基板內且被一第二內襯所圍繞；一背面介電層，與該背面位於同一側；複數個第一背面球下金屬銲墊，位於該背面介電層上且電性連接至該等第一導通柱；及一第一背面球下金屬平面，位於該背面介電層上且電性連接至該至少一第二導通柱，其中該第一背面球下金屬平面具有複數個穿孔，該等第一背面球下金屬銲墊係設置於該等穿孔內，且該第一背面球下金屬平面及該等第一背面球下金屬銲墊之間具有一間距；一上晶粒，位於該半導體裝置上且具有複數個上連接元件於其一表面上，其中該等上連接元件係分別連接至該等第一背面球下金屬銲墊，且該等上連接元件至少其中之一係電性連接至該第一背面球下金屬平面；一底膠(Underfill)，位於該上晶粒及該半導體裝置之間，以保護該等上連接元件；一下基板；複數個下連接元件，連接該下基板及該半導體裝置；及一封膠材料，包覆該下基板、該半導體裝置及該上晶粒。 A semiconductor package structure comprising: a semiconductor device comprising: a semiconductor substrate having a front surface and a back surface; a plurality of first conductive pillars located in the semiconductor substrate, each of the first conductive pillars being surrounded by a first inner liner; at least one second conductive pillar located at The semiconductor substrate is surrounded by a second inner liner; a back dielectric layer is on the same side as the back surface; a plurality of first back ball under metal pads are located on the back dielectric layer and are electrically connected to The first conductive pillars and a first back ball metal plane are disposed on the back dielectric layer and electrically connected to the at least one second conductive pillar, wherein the first back ball sub-metal plane has a plurality of perforations The first back ball under metal pads are disposed in the through holes, and the first back ball under the metal plane and the first back ball under the metal pads have a spacing; an upper die, Located on the semiconductor device and having a plurality of upper connecting elements on one surface thereof, wherein the upper connecting elements are respectively connected to the first back ball sub-metal pads, and at least one of the upper connecting elements is Electrically connected to a first back ball metal plane; an underfill located between the upper die and the semiconductor device to protect the upper connecting components; a lower substrate; a plurality of lower connecting components, connecting the lower substrate and the a semiconductor device; and an adhesive material covering the lower substrate, the semiconductor device, and the upper die. 如請求項8之半導體封裝結構，其中該半導體裝置更包 括：一背面鈍化層，位於該半導體基板之背面且顯露該等第一導通柱及該第二導通柱之末端；複數個第一背面重佈層，位於該背面鈍化層上且電性連接至該等第一導通柱；至少一第二背面重佈層，位於該背面鈍化層上且電性連接至該至少一第二導通柱，其中該背面介電層係位於該等第一背面重佈層、該第二背面重佈層及該背面鈍化層上方，該背面介電層具有複數個第一開口及至少一第二開口以分別顯露部分該等第一背面重佈層及該第二背面重佈層，且該等第一背面球下金屬銲墊係位於該等第一開口內；至少一第二背面球下金屬銲墊，位於該至少一第二開口內及該背面介電層上；及至少一跡線，連接該至少一第二背面球下金屬銲墊至該第一背面球下金屬平面，其中該第一背面球下金屬平面係透過該至少一第二背面球下金屬銲墊電性連接至該至少一第二導通柱。 The semiconductor package structure of claim 8, wherein the semiconductor device is further packaged a back passivation layer is disposed on the back surface of the semiconductor substrate and exposes the ends of the first conductive pillars and the second conductive pillars; a plurality of first back surface redistribution layers are disposed on the back passivation layer and electrically connected to The first conductive vias are disposed on the back passivation layer and electrically connected to the at least one second via post, wherein the back dielectric layer is located on the first back surface The first back opening layer and the at least one second opening have a plurality of first back openings and at least one second opening to respectively expose portions of the first back redistribution layers and the second back surface Re-layering, and the first back-ball under-metal pads are located in the first openings; at least one second back-ball under-metal pad is located in the at least one second opening and the back dielectric layer And at least one trace connecting the at least one second back ball under the metal pad to the first back ball under metal plane, wherein the first back ball under metal plane passes through the at least one second back ball under metallization Padded to the at least one Conducting post. 如請求項8之半導體封裝結構，其中該等第一導通柱、該第一內襯、該至少一第二導通柱及該第二內襯突出於該背面。 The semiconductor package structure of claim 8, wherein the first conductive pillars, the first inner liner, the at least one second conductive pillar, and the second inner liner protrude from the back surface. 如請求項8之半導體封裝結構，其中該半導體裝置更包括：至少一第三導通柱，位於該半導體基板內且被一第三 內襯所圍繞；及一第二背面球下金屬平面，位於該背面介電層上且電性連接至該至少一第三導通柱，其中該第二背面球下金屬平面並未連接該第一背面球下金屬平面。 The semiconductor package structure of claim 8, wherein the semiconductor device further comprises: at least one third via post, located in the semiconductor substrate and being a third a second back ball metal plane is disposed on the back dielectric layer and electrically connected to the at least one third conductive pillar, wherein the second back ball under metal plane is not connected to the first The metal plane under the ball on the back. 如請求項8之半導體封裝結構，其中該半導體裝置更包括：一正面介電層，與該正面位於同一側；複數個第一正面球下金屬銲墊，位於該正面介電層上且電性連接至該等第一導通柱；及一第一正面球下金屬平面，位於該正面介電層上且電性連接至該至少一第二導通柱，其中該第一正面球下金屬平面具有複數個穿孔，該等第一正面球下金屬銲墊係設置於該等穿孔內，且該第一正面球下金屬平面及該等第一正面球下金屬銲墊之間具有一間距。 The semiconductor package structure of claim 8, wherein the semiconductor device further comprises: a front dielectric layer on the same side as the front surface; and a plurality of first front under-ball metal pads on the front dielectric layer and electrically Connecting to the first conductive pillars; and a first front under-ball metal plane on the front dielectric layer and electrically connected to the at least one second conductive pillar, wherein the first front-ball sub-metal plane has a plurality The first front ball under metal pads are disposed in the through holes, and the first front ball under metal plane and the first front under ball metal pads have a spacing therebetween. 如請求項12之半導體封裝結構，其中該半導體裝置更包括：一正面鈍化層，位於該半導體基板之正面且顯露該等第一導通柱及該第二導通柱之末端；複數個第一正面重佈層，位於該正面鈍化層上且電性連接至該等第一導通柱；至少一第二正面重佈層，位於該正面鈍化層上且電性連接至該至少一第二導通柱，其中該正面介電層係位於該等第一正面重佈層、該第二正面重佈層及該正面鈍化層上方，該正面介電層具有複數個第一開口及至少一第 二開口以分別顯露部分該等第一正面重佈層及該第二正面重佈層，且該等第一正面球下金屬銲墊係位於該等第一開口內；及至少一第二正面球下金屬銲墊，位於該至少一第二開口內及該正面介電層上，其中該第一正面球下金屬平面係透過該至少一第二正面球下金屬銲墊電性連接至該至少一第二導通柱。 The semiconductor package structure of claim 12, wherein the semiconductor device further comprises: a front passivation layer on the front side of the semiconductor substrate and exposing the ends of the first via post and the second via post; the plurality of first frontal weights a layer of the layer on the front passivation layer and electrically connected to the first via posts; at least one second frontmost redistribution layer on the front passivation layer and electrically connected to the at least one second via post, wherein The front dielectric layer is located above the first front redistribution layer, the second front redistribution layer and the front passivation layer, and the front dielectric layer has a plurality of first openings and at least one a second opening to respectively expose a portion of the first front redistribution layer and the second front redistribution layer, wherein the first front under-ball metal pads are located in the first openings; and at least one second front ball a lower metal pad is disposed in the at least one second opening and the front dielectric layer, wherein the first front under-ball metal plane is electrically connected to the at least one through the at least one second front under-ball metal pad Second conduction post. 一種半導體裝置，包括：一半導體基板；複數個訊號銲墊，鄰接於該半導體基板；至少一電源或接地銲墊，鄰接於該半導體基板；一第一球下金屬平面，鄰接於該半導體基板且電性連接至該至少一電源或接地銲墊，且該第一球下金屬平面具有複數個穿孔；及複數個第一球下金屬銲墊，分別設置於該等穿孔內且電性連接至該等訊號銲墊，其中該第一球下金屬平面之面積係大於每一該等第一球下金屬銲墊之面積。 A semiconductor device comprising: a semiconductor substrate; a plurality of signal pads adjacent to the semiconductor substrate; at least one power or ground pad adjacent to the semiconductor substrate; a first under-ball metal plane adjacent to the semiconductor substrate Electrically connected to the at least one power source or the grounding pad, and the first ball under metal plane has a plurality of through holes; and a plurality of first ball under metal pads are respectively disposed in the through holes and electrically connected to the The signal pad of the first ball, wherein the area of the metal plane of the first ball is greater than the area of the metal pad of each of the first balls. 如請求項14之半導體裝置，更包括：一鈍化層，鄰接於該半導體基板之一表面；複數個第一重佈層，位於該鈍化層上且電性連接至該等訊號銲墊；至少一第二重佈層，位於該鈍化層上且電性連接至該至少一電源或接地銲墊；一介電層，位於該等第一重佈層、該第二重佈層及該 鈍化層上方，該介電層具有複數個第一開口及至少一第二開口以分別顯露部分該等第一重佈層及該第二重佈層，其中該等第一球下金屬銲墊係位於該等第一開口內；至少一第二球下金屬銲墊，位於該至少一第二開口內及該介電層上；及至少一跡線，連接該至少一第二球下金屬銲墊至該第一球下金屬平面，其中該第一球下金屬平面係透過該至少一第二球下金屬銲墊電性連接至該至少一電源或接地銲墊。The semiconductor device of claim 14, further comprising: a passivation layer adjacent to a surface of the semiconductor substrate; a plurality of first redistribution layers on the passivation layer and electrically connected to the signal pads; at least one a second redistribution layer on the passivation layer and electrically connected to the at least one power or ground pad; a dielectric layer located on the first redistribution layer, the second redistribution layer, and the Above the passivation layer, the dielectric layer has a plurality of first openings and at least one second opening to respectively expose a portion of the first redistribution layer and the second redistribution layer, wherein the first under-ball metal pads are Located in the first openings; at least one second under-ball metal pad is located in the at least one second opening and on the dielectric layer; and at least one trace connecting the at least one second under-ball metal pad Up to the first ball lower metal plane, wherein the first ball under metal plane is electrically connected to the at least one power source or ground pad through the at least one second ball under metal pad.
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