TWI434183B - Driving circuit and data transmission method thereof - Google Patents

Description

Drive circuit and data transmission method

The invention relates to a source driver of a liquid crystal display panel, in particular to a source driver supporting a plurality of busbar modes.

Liquid crystal displays (LCDs) have the advantages of low radiation, light weight, and low power consumption. Therefore, liquid crystal displays have gradually replaced traditional cathode ray tube (CRT) displays and are widely used in various types. Among information products, such as notebook computers, personal digital assistants (PDAs), mobile phones, and the like. Generally, the liquid crystal display uses a timing controller to generate a data signal corresponding to the image to be displayed, a control signal, and a timing signal for driving the liquid crystal display panel. Then, the source driver of the liquid crystal display is enabled according to the These data signals, control signals, and timing signals are used to generate driving signals for the liquid crystal display panel. In order to suppress noise and reduce power consumption, the data transmitted from the timing controller to the source driver via the data bus is usually transmitted in different signals. The common data transmission bread contains a reduced swing differential signal (Reduced Swing). Differential Signaling (RSDS) interface, mini low voltage differential signal (mini-LVDS) interface, etc.

The miniature low-pressure differential signal bread contains several bus patterns, and the common five-pair mode and six-pair mode. However, today's source drivers with a miniature low-voltage differential signal interface can only support five pairs of modes or six pairs of modes, that is, a miniature low-voltage differential signal interface source driver supporting five pairs of modes cannot be used in six pairs of modes. Thus, the range in which the source driver can be applied is limited, and thus the production cost is required to manufacture the source driver applied to different modes.

Accordingly, it is an object of the present invention to provide a drive circuit and associated data transfer method to solve the above problems.

According to an embodiment of the invention, a drive circuit is provided. The driving circuit comprises a receiving module, a data mapping module, a shift register module, a plurality of output channels and a switching module. The receiving module receives data from a first number of parallel inputs. The data mapping module is coupled to the receiving module for mapping data received from the first number of parallel inputs to a second number of data busses according to a bus mode signal. The shift register module is configured to generate a plurality of shift control signals. Each output channel is latched to the data bus according to a corresponding shift control signal. The switching module is connected between the shift register module and the output channels for outputting the shift control signals to the output channels according to the bus pattern signal. The driving circuit is a source driver of a liquid crystal display panel. The driver circuit supports a miniature low voltage differential signaling interface having a plurality of bus patterns (including at least five pairs of modes and six pairs of modes).

According to another embodiment of the present invention, a data transmission method is provided. The data transmission method includes: receiving data from a first number of parallel inputs; mapping data received from the first number of parallel inputs to a second amount of data according to a bus mode signal a bus bar; generating a plurality of shift control signals; outputting the shift control signals to the plurality of output channels according to the bus mode signal; and latching the data according to the corresponding shift control signals The data is on the bus.

Certain terms are used throughout the description and following claims to refer to particular elements. Those of ordinary skill in the art should understand that a hardware manufacturer may refer to the same component by a different noun. The scope of this specification and the subsequent patent application do not use the difference of the names as the means for distinguishing the elements, but the difference in function of the elements as the criterion for distinguishing. The term "including" as used throughout the specification and subsequent claims is an open term and should be interpreted as "including but not limited to". In addition, the term "coupled" is used herein to include any direct and indirect electrical connection means. Therefore, if a first device is coupled to a second device, it means that the first device can be directly electrically connected to the device. The second device is indirectly electrically connected to the second device through other devices or connection means.

1 is a block diagram of a driving circuit 100 in an embodiment of the present invention. The driving circuit 100 can be a source driver of a liquid crystal display panel, but this is not a limitation of the present invention, and it can also be a driving circuit of any form of display. As shown in FIG. 1 , the driving circuit 100 includes, but is not limited to, a receiving module 110 , a data mapping module 120 , a shift register module 130 , a switching module 140 , and a plurality of outputs Channel CH1~CHN. The output channels CH1~CHN have output terminals OUT1~OUTN, respectively. The receiving module 110 receives the data from a parallel input SIN_1~SIN_A of the first number A of the plurality of input bus bars. The data mapping module 120 is coupled to the receiving module 110 for mapping data received from the parallel input terminals SIN_1 S SIN_A of the first quantity A to a second quantity B according to a bus pattern signal S _BM Data bus BUS_1~BUS_B. The shift register module 130 is configured to generate a plurality of shift control signals SR ₁ ~SR _M . The switching module 140 is connected between the shift register module 130 and the output channels CH1~CHN. The switching module 140 selectively outputs the shift control signals SR ₁ to SR _M to the output channels CH1 to CHN according to the bus pattern signal S _BM . Each of the output channels CH1~CHN latches the data on the data bus BUS_1~BUS_B according to the corresponding shift control signal received.

The drive circuit 100 is adapted to support a data transmission interface of a plurality of bus modes. The bus pattern signal S _BM represents one of the bus transmission modes of the data transmission interface of the driving circuit 100 and is used to control the operation of the data mapping module 120 and the switching module 140.

Each bus pattern represents a different number of parallel inputs and data busses. In the bus pattern of one embodiment of the invention, the first number of parallel inputs is less than the second number of data busses. The data mapping module 120 maps the first number of parallel input terminals to the second number of data bus bars. Therefore, the output channels CH1 CHCH are used according to the shift control signals output by the switching module 140. The latch is locked to the data bus BUS_1~BUS_B.

In one embodiment, the driver circuit 100 supports a mini low voltage differential signal (mini-LVDS) interface applied to the parallel inputs, but this is not a limitation of the present invention. The miniature low-voltage differential signal interface supports complex array input busses, such as five-pair (5-pair) input busbars or six-pair (6-pair) input busbars. Of course, those skilled in the art should be able to understand that there is any The miniature low-voltage differential signal interface of the quantity input busbar can also be flexibly applied to the driving circuit 100 according to different requirements.

A first bus bar mode with six pairs of input bus bars and six pairs of data bus bars is taken as an example, that is, the first quantity A and the second quantity B are all six. The receiving module 110 receives data from six parallel input terminals SIN_1~SIN_6 on the six pairs of input bus bars. At the same time, the data mapping module 120 directly maps the six parallel input terminals SIN_1~SIN_6 to six data busbars. BUS_1~BUS_6.

In a second bus pattern with five pairs of input busses and six pairs of data busses, that is, the first number A is five and the second number B is six. The receiving module 110 receives data from five parallel input terminals SIN_1~SIN_5 on the five pairs of input bus bars. At the same time, the data mapping module 120 maps five parallel input terminals SIN_1~SIN_5 to six data bus bars BUS_1. ~BUS_6. The operation of the data mapping module 120 and the switching module 140 in the driving circuit 100 will be described in detail in the following embodiments.

The driving circuit chip disposed in the driving circuit 100 disclosed in the present invention can support different numbers of input bus bars, and therefore, the manufacturing cost of the driving circuit 100 can be effectively reduced.

In order to arrange the driver circuit chip in the circuit structure of the present invention, the following two problems must be solved: the control mode of the shift register and the data mapping order. 2A and 2B are schematic circuit diagrams showing the detailed configuration of the driving circuit 100 shown in Fig. 1 in an embodiment of the present invention. In this embodiment, the driver circuit 100 supports two bus bar modes: a first bus bar mode for six pairs of input bus bars and a second bus bar mode for five pairs of input bus bars. The switching module 140 includes selection switches SW ₁ -SW ₁₀ . As shown in FIG. 2A and FIG. 2B, each of the sixty output channels is divided into the same group based on the number of data bus bars. For example, the sixty output channels CH1 to CH60 in FIGS. 2A and 2B can be regarded as the first group. When the driving circuit 100 is used in the first bus mode, all of the selection switches SW ₁ to SW _{10 are} switched to the broken line; when the driving circuit 100 is used in the second bus mode, all the selection switches SW ₁ to SW _{10 are} Switch to the solid line.

In the first bus mode for six pairs of input busses, each shift control signal is input to the six output channels through the switching module 140. For example, the first shift control signal SR ₁ controls the six output channels CH1 CHCH6 and the second shift control signal SR ₂ controls the six output channels CH7~CH12. At this time, the first selection out switch SW ₁ of the first shift control signal SR is connected to the output channel _{CH6. 1, 2} a second selection switch SW ₂ is connected to a second shift control signal SR output channels CH11 and CH12, and so on .

In the second bus mode for five pairs of input busses, each shift control signal is input to the five output channels through the switching module 140. For example, the first shift control signal SR ₁ controls the five output channels CH1 CHCH5 and the second shift control signal SR ₂ controls the five output channels CH6~CH10. At this time, the first selection out switch SW ₁ of the first shift control signal SR is connected to the output channel _{CH6. 1, 2} a second selection switch SW ₂ is connected to a second shift control signal SR output channels CH11 and CH12, and so on .

The driving circuit 100 has a function of supporting a plurality of bus bar modes by the switching module 140 and the data mapping module 120. That is, the driving circuit 100 can be used for several interfaces having different number of input bus bars without modification. Internal circuit. Please note that the selection switch can be disposed between the shift registers in the shift register module 130, so that the size of the circuit area is not affected, but the above embodiment is not a limitation of the present invention. The artist can also place the selector switch in a variety of different positions. In addition, the circuit structure of the embodiment divides sixty output channels into a group, which has the advantages of being symmetrical and easy to set.

FIG. 3 is a schematic diagram of how the data mapping module 120 operates in an embodiment of the present invention. Taking a five-to-six mapping as an example, the data mapping module 120 maps the data received from the five parallel input terminals SIN_1 S SIN_5 to the six data bus bars BUS_1 BUS BUS_6 according to the bus bar mode signal S _BM . In the first time period T ₁ , the data bus bars BUS_1~BUS_5 are sequentially filled in, and the data bus bar BUS_6 is dummy, which is represented by “D” in the figure. In the second time period T ₂ , the data bus BUS_6 is filled in first, then the data bus BUS_1~BUS_4 is sequentially filled, and the data bus BUS_5 is dummy. The rest of the time can be learned from this logical inference. After the thirty sets of data are filled in, a loop is completed and the five-to-six map is completed. In other words, the data mapping module 120 cyclically maps the data received by the receiving module 110 to the six data bus bars BUS_1 BUS BUS_6.

The above embodiments are only intended to illustrate the technical features of the present invention and are not intended to limit the scope of the present invention. Those skilled in the art will appreciate that the data mapping module 120 can also be appropriately modified to achieve the desired functionality. For example, the five-to-six mapping can also be applied to a circuit structure in the opposite direction of transmission. In this case, the data sequence is reversed, which is also within the scope of the present invention.

By integrating the circuit structures of FIGS. 2A and 2B and the mapping order of FIG. 3, the driving circuit 100 disclosed in the present invention can support different interfaces, such as a miniature low-voltage differential signal interface having a different number of input bus bars. However, the invention is not limited to five or six pairs of input busses, which can be extended to any number of input busses and data busses, and such variations are also within the scope of the invention.

Please refer to FIG. 4, which is a flow chart of an embodiment of the data transmission method of the present invention. Note that if the same result can be obtained substantially, the steps do not have to be performed sequentially in the order shown in FIG. The method includes the following steps:

Step 402: Start.

Step 404: Receive data from a first number of parallel inputs.

Step 406: Map the data received from the first number of parallel inputs to a second number of data bus according to a bus mode signal.

Step 408: Generate a plurality of shift control signals.

Step 410: Output the shift control signals to the plurality of output channels according to the bus pattern signal.

Step 412: The data is respectively latched on the data bus according to the corresponding shift control signal.

Since the steps in FIG. 4 have been described in detail in the above embodiments, they are not described herein. It should be noted that the method described in FIG. 4 is only an example of implementation and is not intended to limit the conditions of the present invention. The order of the steps is only one preferred embodiment of the present invention. In other words, the order of the steps may be appropriately adjusted according to different situations, and is not limited to the above order.

The above embodiments are only intended to illustrate the technical features of the present invention and are not intended to limit the scope of the present invention. In summary, the present invention provides a driving circuit capable of supporting a data transmission interface having a plurality of bus modes, and a related data transmission method, by adding a plurality of selection switches SW ₁ to SW ₁₀ in the circuit architecture and cooperating with the present invention. According to the data mapping sequence disclosed by the invention, the driving circuit 100 can switch the micro low-voltage differential signal interface between a plurality of input modes (for example, five pairs of modes and six pairs of modes), thereby not only substantially reducing the manufacturing of the driving circuit. The cost does not limit its application range; in addition, the driving circuit architecture of the present invention is also applicable to the structure of 450/630/645/720 output channels, but the number of output channels is not limited by the present invention.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

100. . . Drive circuit

110. . . Receiving module

120. . . Data mapping module

130. . . Shift register module

140. . . Switching module

1 is a block diagram of a driving circuit in an embodiment of the present invention.

2A and 2B are respectively schematic diagrams showing the detailed circuit configuration of the driving circuit shown in Fig. 1 in an embodiment of the present invention.

FIG. 3 is a schematic diagram of how the data mapping module operates in an embodiment of the present invention.

Figure 4 is a flow chart showing an embodiment of the data transmission method of the present invention.

100. . . Drive circuit

110. . . Receiving module

120. . . Data mapping module

130. . . Shift register module

140. . . Switching module

Claims (10)

A driving circuit includes: a receiving module for receiving data from a first number of parallel input terminals; a data mapping module coupled to the receiving module for using a bus mode signal Mapping data received from the first number of parallel inputs to a second number of data buss; a shift register module for generating a plurality of shift control signals; a plurality of output channels, Each output channel is latched to the data bus according to a corresponding shift control signal; and a switching module is connected between the shift register module and the output channels. And outputting the shift control signals to the output channels according to the bus mode signal; wherein the first quantity is less than the second quantity, and the data mapping module outputs the first number of parallel inputs Mapping to the second number of data buss, so that the output channels latch the corresponding data according to the shift control signals output by the switching module. The driving circuit of claim 1, wherein the driving circuit is a source driver of a liquid crystal display panel. The driving circuit of claim 1, wherein the driving circuit supports a mini low voltage differential signal (mini low voltage differential signal, mini-LVDS) interface. The driving circuit of claim 3, wherein the driving circuit supports a plurality of micro low-voltage differential signal interfaces each having a different number of input bus bars. The driving circuit of claim 4, wherein the number of the input bus bars is five or six. A data transmission method includes: receiving data from a first number of parallel input terminals; mapping data received from the first number of parallel input terminals to a second quantity according to a bus pattern signal a data bus; generating a plurality of shift control signals; outputting the shift control signals to the plurality of output channels according to the bus mode signal; and latching the data according to the corresponding shift control signals The data bus is arranged; wherein the second quantity is greater than the first quantity, and the step of mapping the data received from the first quantity of parallel inputs to the second quantity of data bus includes: cycling Map the data to the data bus. For example, the data transmission method described in claim 6 of the patent application system supports a miniature low Pressure differential signal interface. For example, the data transmission method described in claim 6 can support a plurality of micro low-voltage differential signal interfaces having different input bus bars respectively. The data transmission method of claim 8, wherein the input bus bars can be five pairs (pairs) or six pairs (6-pairs). A driving circuit includes: a receiving module for receiving data from a first number of parallel input terminals; a data mapping module coupled to the receiving module for using a bus mode signal Mapping data received from the first number of parallel inputs to a second number of data buss; a shift register module for generating a plurality of shift control signals; a plurality of output channels, Each output channel is latched to the data bus according to a corresponding shift control signal; and a switching module is connected between the shift register module and the output channels. And outputting the shift control signals to the output channels according to the bus mode signal; wherein the second quantity is greater than the first quantity, and the data mapping module receives the receiving module The data is cyclically mapped to the data bus.