TWI433155B - Non-volatile semiconductor memory - Google Patents

Description

Non-volatile semiconductor memory device

The present invention relates to electrically rewriteable non-volatile semiconductor memory devices (EEPROM), such as flash memory.

A plurality of memory cell transistors (hereinafter referred to as memory cells) between a bit line and a source line are connected in series to form a NAND string, thereby realizing that A high-density NAND type non-volatile semiconductor memory device is known (for example, refer to Patent Documents 1 to 4).

When an ordinary NAND type nonvolatile semiconductor memory device is erased, a voltage of 20 V is applied to the semiconductor substrate, and 0 V is applied to the word line. In this way, the electrons are pulled out from the floating gate, that is, the charge accumulation layer formed by the polysilicon, and the threshold voltage is lower than the erase start voltage (for example: - 3V). On the other hand, when writing is performed, 0 V is applied to the semiconductor substrate, and a high voltage of 20 V is applied to the control gate. As a result, electrons are injected into the floating gate from the semiconductor substrate such that the starting voltage is higher than the writing start voltage (for example, 1 V). For a memory cell using these start voltages, a read voltage (for example, 0 V) between the write start voltage and the read start voltage is applied to the control gate to know whether or not current flows in the memory cell. And can judge its status.

However, with the low voltage and high density characteristics of the NAND type flash memory, the problem of coupling noise caused by the capacitance capacity between the bit lines becomes unnegligible. A bit line shield technique (for example, refer to Patent Document 1) is for solving this problem, and it is possible to reduce coupling interference between bit lines. When page reading is performed, the bit line masking technique reads every other bit line and grounds the unselected bit line. In other words, the selection unit and the unselected unit are connected to each other to form a control gate line.

Further, Patent Document 5 provides a technique capable of improving the electrical characteristics of a non-volatile memory such as a flash memory, and has the following structure. A wiring including a signal line is formed in the first layer of the wiring layer. The gate transistor is formed in a region of a memory mat, and a wiring such as the signal line is formed on a region of the selected gate transistor. Next, in the region of the memory matrix, shield wiring is formed in the unwiring region where wiring such as signal lines is not formed. That is, the shield wiring is formed on the memory cell array region where wiring such as signal lines is not formed. A global bit line for commonly connecting a plurality of bit lines is formed in the second layer of the wiring layer. According to the shielding wiring provided in the first layer, the total bit line of the second layer is shielded, and the coupling interference between adjacent total bit lines is reduced.

[Patent Document 1] Japanese Laid-Open Patent Publication No. Hei 9-147582.

[Patent Document 2] JP-A-2000-285692.

[Patent Document 3] JP-A-2003-346485.

[Patent Document 4] JP-A-2001-028575.

[Patent Document 5] JP-A-2007-123652.

[Non-Patent Document 1] Tomoharu Tanaka et al., "A Quick Intelligent Page-Programming Architecture and a Shielded Bitline Sensing Method for 3 V-only NAND Flash Memory", IEEE Journal of Solid-State Circuits, Vol. 29, No. 11, pp. 1366-1373, November 1994.

As the bit line masking technique shown in Non-Patent Document 1, when the NAND type flash memory is read/verified, the total bit line is grounded every other one as a function of the shield line. For the total bit line of the read data, it is usually possible to prevent interference of adjacent bit lines. The transistor for grounding the total bit line is disposed at the near end of the page buffer, or is disposed at the near end plus the far end (both ends of the total bit line).

With the miniaturization of process technology, the impedance of the total bit line and the capacitance capacity between adjacent bit lines are increasing. Since the grounded transistor is at the farthest and is in the middle of the total bit line, its shielding effect is weakened. As a result, the total bit line must be split to maintain its shielding effect. On the other hand, the division of the total bit line requires a new page buffer column, resulting in an increase in the size of the wafer, which is the main cause of the increase in cost. The details will be described below.

Fig. 10 is a circuit diagram showing the grounded transistor portions 10A and 10B constituting the conventional memory cell array, and Fig. 11 is a circuit operation timing chart showing Fig. 10. In Fig. 10, grounding transistors 21 and 22 are provided in the grounded transistor portions 10A and 10B at both ends of the total bit line GBL. Cc represents the capacitance capacity between adjacent total bit lines GBL. In Fig. 11, SGBL represents the total bit line that is masked but not read, DGBL represents the total bit line of the discharge from which the charge is discharged from the memory cell, and NDGBL indicates that the charge is not discharged from the memory cell. Total bit line.

In Fig. 10, for example, when the opposite gate string connected to the point Pb is discharged via the total bit line GBL, the coupling interference is overlapped with the point Pb of the adjacent total bit line GBL. The line between the points Pd, and the interference is further transmitted to the line between the point Pe-point Pf of the adjacent total bit line GBL. On the line between the point Pe-point Pf of the affected adjacent total bit line GBL, when the reverse is not performed, the interference amount is too large, as shown in Fig. 101. It shows that the bit line voltage drop will cause misreading problems.

Fig. 12 is a circuit diagram showing the grounded transistor portions 10A and 10B constituting another memory cell array associated with the conventional one. In order to solve the above problem, as shown in Fig. 12, the length of the total bit line GBL is divided into two halves, and a set of page buffers 14 is added in the middle, which can halve the impedance of the total bit line GBL. On the other hand, there is a problem of an increase in the size of the wafer.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above problems by providing a non-volatile semiconductor memory device for controlling an increase in wafer size and preventing misreading caused by a capacitance capacity between adjacent total bit lines GBL.

The non-volatile semiconductor memory device of the present invention includes a non-volatile memory cell array for recording data by setting a starting voltage for each memory cell transistor, wherein each memory cell transistor is connected in series Selecting a gate transistor between the two ends of the bit line; and a control circuit for reading the bit line and the data from the memory cell transistor through the total bit line connected to the plurality of bit lines, The method is characterized in that a switching element is used to connect the total bit line and the predetermined power line at one of the total bit lines.

In the above non-volatile semiconductor memory device, the switching element independently connects the even total bit line and the odd total bit line of the total bit line to respective predetermined power lines.

Furthermore, in the non-volatile semiconductor memory device, the switching element is adjacent to the total bit line for reading data and is connected to the total bit line for which data reading is not performed, and is turned on by the control circuit.

Further, in the above nonvolatile semiconductor memory device, the switching element is formed by the same element structure as the above-described selection gate transistor.

Furthermore, in the above non-volatile semiconductor memory device, the power supply line is a power supply line of a grounding level.

Further, in the above nonvolatile semiconductor memory device, the power supply line is a source line of the memory cell transistor.

Furthermore, in the above non-volatile semiconductor memory device, the memory cell array is composed of a plurality of memory cell transistors having opposite gate strings.

According to the nonvolatile semiconductor memory device of the present invention, the switching element is used to connect the total bit line and the predetermined power supply line at one of the above-mentioned total bit lines. The switching element is adjacent to the total bit line for reading data and is connected to the total bit line for which no data is read, and is turned on by the above control circuit. Therefore, it is possible to control the increase in the size of the wafer and prevent misreading caused by the capacitance capacity between adjacent total bit lines GBL.

The embodiments of the present invention are described below in conjunction with the drawings. In the following embodiments, the same or similar constituent elements are denoted by the same or similar symbols.

FIG. 1 is a view showing the overall structure of an ECU type electrically-erasable and erasable memory (Electrically-Erasable Programmable Read-Only Memory, hereinafter referred to as EEPROM) according to an embodiment of the present invention. Block diagram. Further, Fig. 2 is a circuit diagram showing the memory cell array 10 of Fig. 1 and its peripheral circuit configuration. First, the structure of the NAND type flash EEPROM related to this embodiment will be described below.

In the first embodiment, the NAND type flash EEPROM related to this embodiment includes a memory cell array 10, a control circuit 11 for controlling the operation thereof, a column decoder 12, a high voltage generating circuit 13, a data writing and reading circuit 14, The row decoder 15, the command register 17, the address register 18, the operation logic control unit 19, the data input/output buffer 50, and the data input/output terminal 51.

The memory cell array 10 of FIG. 2 is composed of a grounded transistor portion 10A including a plurality of grounded transistors 21, a cell array portion 10D, a grounded transistor portion 10C including a plurality of grounded transistors 23, and a cell array portion 10E, including The grounded transistor portion 10B of the plurality of grounded transistors 22 and the page buffer 14 are sequentially arranged. Here, the memory cell array 10 of this embodiment is specifically provided with a grounded transistor portion 10C. In one position (preferably in the middle position) of the total bit line GBL, the grounding transistor 23 is used as a switching element to connect the total bit line and the predetermined power line VIRPWRE or VIRPWRO to form the grounding transistor portion 10C. . Here, the grounding transistor 23 adjacent to the total bit line GBL for reading the data and connected to the total bit line GBL for which data reading is not performed is turned on by the control circuit 11 for The bit line GBL is grounded (preferably set to a low voltage close to a predetermined ground potential). Further, the grounding transistor 23 and the selection gate transistors 24, 25, 26, 27 are formed in the same element structure.

As shown in FIG. 2, in the cell array portions 10D and 10E of the memory cell array 10, the reverse gate string 10s is composed of a plurality of electrically rewriteable non-volatile memory cells having a stacked gate structure. Made in series. Each of the reverse gate strings 10s is formed by serially connecting a plurality of memory cell transistors 20, and the drain side thereof is connected to the total bit line GBL via the selection gate transistor 25 or 26 and the bit line BL. The source side is connected to the control line CSL which is the common source line via the selection gate transistor 24 or 27. Here, the total bit line GBL is connected to the page buffer 14 for reading and writing data. In addition, referring to FIG. 10, in this embodiment, although a plurality of dummy transistors are serially connected to form the inverse gate virtual string 10d, the present invention is not limited thereto, and may not be provided. Further, as shown in Fig. 13, the control gate CG and the floating gate FG are not connected to constitute the memory cell transistor 20. On the other hand, as shown in Fig. 14, the control gate CG and the floating gate FG are connected to constitute the selection gate transistors 24 to 27. The control gates of the respective anti-gate strings 10s juxtaposed in the column direction are each connected to the word line. Here, the range of memory cells selected by a word line is a page of writing and reading units. A page or its integer multiple range, that is, a range of a plurality of inverse gate strings 10s, is a block of data erasing units. The data writing and reading circuit 14 of FIG. 1 is used for writing and reading data of a page unit, and includes a sensing amplifier circuit (SA) and a shackle circuit (DL) disposed on each bit line. , hereinafter referred to as the page buffer.

The memory cell array 10 of Fig. 2 also has a simplified structure in which a plurality of bit lines can share a page buffer. In this case, the number of bit lines selectively connected to the page buffer is a unit of one page when the data is written or read. In Fig. 1, in order to select the word line and the bit line of the memory cell array 10, a column decoder 12 and a row decoder 15 are provided, respectively. Further, the control circuit 11 performs sequence control of data writing, erasing, and reading. The high voltage generating circuit 13 controlled by the control circuit 11 is configured to generate a boosted high voltage and an intermediate voltage used for data writing, erasing and reading.

The data input/output buffer 50 is used for input/output of data and input of address signals. That is, data is transferred between the data input/output terminal 51 and the page buffer 14 via the data input/output buffer 50. The address signals input from the data input/output terminal 51 are stored in the address register 18 and sent to the column decoder 12 and the row decoder 15 for decoding. The command for operation control is also input from the data input/output terminal 51. The input command is decoded and stored in the command register 17, whereby the control circuit 11 is controlled. Chip enable signal CEB, command latch enable signal CLE, address latch enable signal ALE, write enable signal WEB, read enable signal REB The external control signal is read to the operational logic control unit 19, and then an internal control signal is generated in accordance with the operational mode. The internal control signals are used for data lock, transfer, etc. control of the data input/output buffer 50, and are further transmitted to the control circuit 11 for operational control.

The memory cell array 10 constructed as described above is provided with a grounded transistor portion 10C between the cell array portions 10D and 10E. In one position (preferably in the middle position) of the total bit line GBL, the grounding transistor 23 is used as a switching element to connect the total bit line and the predetermined power line VIRPWRE or VIRPWRO to form the grounding transistor portion 10C. . Here, the grounding transistor 23 adjacent to the total bit line GBL for reading the data and connected to the total bit line GBL for which data reading is not performed is turned on by the control circuit 11 for The bit line GBL is grounded (preferably using the source line of the memory cell transistor 20, or may be set to a low voltage close to a predetermined ground potential). Further, the grounding transistor 23 and the selection gate transistors 24, 25, 26, 27 are formed in the same element structure. In the grounded transistor portion 10C of FIG. 2, each of the grounded transistors 23 is connected to the respective predetermined power lines VIRPWRE or VIRPWRO by the even total bit lines and the odd total bit lines of the total bit line GBL. Furthermore, each of the grounding transistors 23 can also be used to reset the bit line voltage. Further, in Fig. 2, element 28 is an isolation transistor.

The features of the memory cell array 10 related to this embodiment will be described in detail below. Fig. 3 is a circuit diagram showing the grounding of the total bit line GBL by the grounding transistor 23 provided in the memory cell array 10 of Fig. 1. As shown in Fig. 3, the grounding transistor portion 10C including a plurality of grounding transistors 23 is disposed in each of the total bit lines GBL to maintain the shielding effect. In order to make the memory cell array easy to implement, each of the grounded transistors 23 of the grounded transistor portion 10C has the same layout structure as the selected gate transistors 24, 25, 26, and 27. Although this configuration slightly increases the wafer area, the increased area is relatively small compared to the new page buffer column shown in FIG.

Fig. 4 is a view showing the voltage change of the total bit line in the memory cell array 10 of Fig. 1. In Fig. 4, SGBL represents the total bit line being shielded, DGBL represents the total bit line from which the charge is discharged from the memory cell, and NDGBL represents the total bit line in which the charge is not discharged from the memory cell. In other words, Fig. 4 is a comparative illustration of Fig. 11. In Fig. 3, the grounding transistor 23 is added to the point Pd at the center of the total bit line GBL. Therefore, as shown in Fig. 4, the waveform of the point Pd is substantially the same as the waveform of the point Pc (102 of Fig. 4). Further, the coupling interference transmitted on the line between the point Pe-point Pf is small enough to be ignored, and the page buffer 14 connected to the point Pe no longer causes data misreading. As a result, not only the increase in the size of the wafer is controlled, but also the shielding operation can be used to reduce the coupling interference of the total bit line GBL and prevent misreading.

Fig. 5 is a plan view showing the arrangement of the memory cell array 10 including the grounding transistor portion 10C of Fig. 2. As shown in FIG. 5, inside the memory cell array 10, the word line WL/bit line BL is formed with a predetermined line/space. On the premise of this, in order to optimize the process conditions, it is not recommended to arrange the peripheral transistors in the memory cell array 10 with different design rules. Within the memory cell array 10, the same component structure as the selected gate transistor used will be used as the grounded transistor 23 of the grounded transistor portion 10C. In other words, the grounding transistor 23 is constructed by the structure of the selection gate transistors 24 to 27, so that the inside of the memory cell array 10 can be made tight without causing a large increase in the processing time.

Fig. 6 is a plan view showing the arrangement of the memory cell array 10 including the grounding transistor portion 10C of Fig. 2 and its peripheral circuits. As shown in FIG. 6, as in the prior art, the grounded transistor portions 10A and 10B are disposed on the nearest and farthest ends of the page buffer 14 on the total bit line GBL, and are in the central portion of the memory cell array 10 ( The grounding transistor 23 of the grounded transistor portion 10C may be added to a plurality of positions in the middle.

Fig. 7 is a circuit diagram showing the grounding transistor portion 10A constituting the second drawing. The grounded transistor portion 10A is composed of grounded transistors Q1 and Q2 each connected to the bit lines BL0 and BL1, and is controlled by the gate voltage of the control line YBLE or YBLO, and is connected to the power line voltage VIRPWR. In other words, the grounding transistor of the grounding transistor portion 10A is a grounding transistor configured to be connected to the total bit line GBL at the distal end of the page buffer 14, and is laid out in accordance with the design rule of the peripheral transistor, compared to the memory unit. The process rules of array 10 have a larger size.

Fig. 8 is a circuit diagram showing the structure of the grounding transistor portion 10B of Fig. 2, the page buffer 14, and its peripheral circuits. The grounded transistor portion 10B is composed of grounded transistors Q11 and Q12 each connected to the bit lines BL0 and BL1, and is controlled by the gate voltage of the control line YBLE or YBLO, and is connected to the power line voltage VIRPWR. The bit lines BL0 and BL1 are connected to the page buffer 14 via the selection gate transistor Q13 or Q14, and the bit line control transistor Q15. The page buffer 14 is conventionally constructed of a latch circuit 14a including a latch L1 and a latch circuit 14b including a latch L2. The page buffer 14 is connected to the data input/output terminal 51 via the selection transistors CSL0 to CSL511, the data line 52, and the data input/output buffer 50. Further, similarly to the grounded transistor portion 10A, the grounded transistor portion 10B is constituted by a peripheral transistor, and is disposed on the side of the page buffer 14 of the total bit line GBL.

Fig. 9 is a timing chart showing the operation of the circuits of Figs. 2 to 8. In Fig. 9, SG denotes a control voltage for selecting a gate transistor. In the data reading operation of FIG. 9, 0V is supplied to the power line voltage VIRPWR (including VIRPWRE and VIRPWRO) for use as the source potential of the anti-gate string 10s. Further, 0 V of the same potential as the power line voltage VIRPWR is also supplied to the isolation electrode ISOLATION. Corresponding to the total bit line GBL for reading data, a high level is supplied to one of the control voltages YBLE/YBLO, and 0V of the same potential as the power line voltage VIRPWR is supplied to the other side for selection. One of the transistors. Here, when reading data from the memory unit, the bit line is precharged with a predetermined pre-charge voltage. Thereafter, the charge from the memory cell is discharged, and the detection voltage of the bit line and the predetermined starting voltage are compared to determine the data value in the memory cell. In this embodiment, the grounding transistor 23 is adjacent to the total bit line GBL for reading data, and is connected to the total bit line GBL for which no data is read, and is turned on by the control circuit 11 for shielding. Select the total bit line GBL. In this way, misreading caused by the capacitance capacity between adjacent total bit lines GBL can be prevented.

As described in detail above, in accordance with the non-volatile semiconductor memory device of the present invention, a switching element is used to connect the total bit line and the predetermined power line at one of the above-mentioned total bit lines. The switching element is adjacent to the total bit line for reading data and is connected to the total bit line for which no data is read, and is turned on by the above control circuit. Therefore, it is possible to control the increase in the size of the wafer and prevent misreading caused by the capacitance capacity between adjacent total bit lines GBL.

10. . . Memory cell array

10A, 10B, 10C. . . Grounded transistor section

10D, 10E. . . Cell array section

10d. . . Virtual transistor

10s. . . Reverse gate (NAND) string

11. . . Control circuit

12. . . Column decoder

13. . . High voltage generating circuit

14. . . Data write and read circuit (page buffer)

14a, 14b. . . Shackle circuit

15. . . Row decoder

17. . . Command register

18. . . Address register

19. . . Operational logic controller

20. . . Memory cell transistor

21, 22, 23, Q1, Q2, Q11, Q12. . . Grounded transistor

24, 25, 26, 27, Q13, Q14. . . Select gate transistor

28. . . Isolation transistor

50. . . Data input/output buffer

51. . . Data input/output

52. . . Data line

54. . . Pad

BL, BL0, BL1. . . Bit line

Cc. . . Capacitance capacity

CG. . . Control gate

CSL0～CSL511. . . Select transistor

FG. . . Floating gate

GBL. . . Total bit line

L1, L2. . . Shackle

Q15. . . Bit line control transistor

and

W

1 is a block diagram showing the overall structure of a NAND type flash EEPROM according to an embodiment of the present invention.

Fig. 2 is a circuit diagram showing the memory cell array 10 of Fig. 1 and its peripheral circuit configuration.

Fig. 3 is a circuit diagram showing the grounding of the total bit line GBL by the grounding transistor 23 provided in the memory cell array 10 of Fig. 1.

Fig. 4 is a view showing the voltage change of the total bit line in the memory cell array 10 of Fig. 1.

Fig. 5 is a plan view showing the arrangement of the memory cell array 10 including the grounding transistor portion 10C of Fig. 2.

Fig. 6 is a plan view showing the arrangement of the memory cell array 10 including the grounding transistor portion 10C of Fig. 2 and its peripheral circuits.

Fig. 7 is a circuit diagram showing the grounding transistor portion 10A constituting the second drawing.

Fig. 8 is a circuit diagram showing the structure of the grounding transistor portion 10B of Fig. 2, the page buffer 14, and its peripheral circuits.

Fig. 9 is a timing chart showing the operation of the circuits of Figs. 2 to 8.

Figure 10 is a circuit diagram showing the grounded transistor portions 10A and 10B constituting a conventional memory cell array.

Fig. 11 is a timing chart showing the operation of the circuit of Fig. 10.

Fig. 12 is a circuit diagram showing the grounded transistor portions 10A and 10B constituting another memory cell array associated with the conventional one.

Fig. 13 is a cross-sectional view showing the memory cell 20 constituting the memory cell of Fig. 2.

Fig. 14 is a cross-sectional view showing the selection of the gate transistors 24 to 27 in Fig. 2;

10. . . Memory cell array

10A, 10B, 10C. . . Grounded transistor section

10D, 10E. . . Cell array section

10d. . . NAND dummy string

10s. . . Counter brake

14. . . Page buffer

20. . . Memory cell transistor

21, 22, 23. . . Grounded transistor

24, 25, 26, 27. . . Select gate transistor

28. . . Isolation transistor

and

GBL. . . Total bit line

Claims (6)

A non-volatile semiconductor memory device includes: a non-volatile memory cell array, wherein a starting voltage is set for each memory cell transistor for recording data, wherein each memory cell transistor is serially selected a gate electrode is selected between the two ends of the bit line; and a control circuit is configured to read the bit line and the data from the memory cell transistor through the total bit line connected to the plurality of bit lines; The method is characterized in that, in one of the total bit lines, a switching element is used to connect the total bit line and a grounding level power line, and one end of the switching element is directly connected to the total bit line. The non-volatile semiconductor memory device of claim 1, wherein the switching element independently connects the even total bit line and the odd total bit line of the total bit line to respective ground level power sources. line. The non-volatile semiconductor memory device according to claim 1, wherein the switching element is adjacent to a total bit line for reading data and is connected to a total bit line for which data reading is not performed. The above control circuit is turned on. The non-volatile semiconductor memory device according to claim 1, wherein the switching element is formed by the same element structure as the selection gate transistor. The non-volatile semiconductor memory device according to claim 1, wherein the power supply line is a source line of the memory cell transistor. The non-volatile semiconductor memory device according to claim 1, wherein the memory cell array is composed of a plurality of memory cell transistors having a plurality of gates.