TWI428931B - Addressing connection circuit for 3d ic chip - Google Patents

Description

Three-dimensional integrated circuit wafer address connection circuit

The present invention relates to a three-dimensional integrated circuit wafer address connection circuit for selecting one of a plurality of wafers connected in a three-dimensional stack to allow an I/O terminal to be turned on or off from an internal circuit.

Due to the rapid development of integrated circuit technology, it has become a viable technology to integrate various digital analog circuits on a single chip. System-on-a-chip (SoC) technology is gradually being applied to a variety of high-performance chips, but as circuit design complexity increases and circuit performance requirements are limited by wafer yield and performance considerations, SoC wafer area The use of it is gradually limited. In recent years, due to advances in semiconductor chip packaging technology, wafer stacking technology has become more and more mature, so the three-dimensional integrated circuit wafer stacking technology has become a solution for replacing high-performance chips in the future by replacing SoC technology.

The integrated circuit chip through the through-silicone via (TSV) three-dimensional connection method can effectively reduce the chip area, and can reduce the length of the signal wiring to reduce the RC time delay and improve the circuit performance. Moreover, the stacked wafers can use different process technologies to make integration of heterogeneous wafers possible, and expand the application of integrated circuit wafers.

The through-wafer vias are connected between the stacked wafers, and the through-silicone vias can shorten the distance required for data transfer on the wafer, reduce the RC time delay, and the 3D IC is stacked for many layers of wafers, so that the area can be greatly increased. Zoom out.

FIG. 1 is a schematic cross-sectional view showing a conventional three-dimensional integrated circuit wafer composed of through-pass twinning. Referring to FIG. 1, a plurality of IC wafers 104 of the same type are packaged on a circuit substrate 100 in a stacked manner. The other side of the circuit substrate 100 has bonding bumps 108 for connection to external circuits. A plurality of I/O terminals on the plurality of IC wafers 104 are simultaneously connected using through-pass twinned vias 106. The encapsulant layer 102 encloses these wafers 104 for protection. In other words, the through-silicon vias 106 are connected in a vertical manner to the corresponding I/O terminals of a single wafer on a stacked wafer. Thus, the signal can be input from the through-silicone via 106 to each wafer.

FIG. 2 is a schematic diagram showing the operation mechanism of a conventional stacked wafer with through-twisted vias. Referring to FIG. 2, the stacking technique of the three-dimensional integrated circuit is exemplified by the case where four wafers constitute a stacked wafer structure. The I/O pad 120 on each of the wafers is used for signal transmission with the outside. Straight through crystal vias 122 simultaneously connect the corresponding I/O pads 120 on each wafer. When a plurality of chips of the same circuit are stacked together through the through-silicon vias 122, the signals are sent to the respective wafers through the input/output (I/O) pad 120 in an ascending path, as indicated by the arrows. In this way, although the structure can reduce the area and the length of the wiring, it is impossible to distinguish which piece of the chip is to be supplied. In order to be able to control the operation of individual wafers, it is necessary to make a circuit that controls the gate 124 to accurately transmit the signal to the internal circuit 126.

FIG. 3 is a schematic diagram showing another operational mechanism of a conventional stacked wafer with through-twisted vias. Referring to Figure 3, since a plurality of internal circuits are included in one wafer, they are transferred by different I/O pads and external circuits. For stacked wafers that are through the twinned vias, a plurality of through-silicon vias 130 are connected to the phase I/O endpoints on the wafer, respectively. Each of the plurality of through-silicon vias 130 is simultaneously coupled to the internal circuitry 132 on the respective wafers via control switches 134. For example, when the wafer 2 is to be transferred to the outside, the connection state of the control switch 134 corresponding to the wafer 2 is turned on to be connected to the internal circuit 132, and the other connection states of the control switch 134 are all open, so that the wafer and the wafer cannot be made. Internal signal transmission, its application is also more limited.

The present invention provides one. The three-dimensional integrated circuit wafer addressing circuit is mainly used for stacking three-dimensional integrated circuit chips by using through-pass twinning, and can control signal transmission between different wafers through the input and output terminals shared by the stacked chips.

The present invention provides a three-dimensional integrated circuit wafer address connection circuit disposed in each of a stacked wafer having a plurality of through-twisted vias (TSVs), each of which is directly connected to the through-silicon via The same signal endpoint on each of the wafers. The three-dimensional integrated circuit wafer address connection circuit includes a control unit, a memory unit, an address unit, and a ground circuit. The control unit is coupled between an output/input terminal and an internal circuit by the through-silicon via, wherein the control unit receives a conduction control signal to determine a conduction state of the control unit. The memory unit is configured to memorize the address information of the chip, wherein the memory unit receives the at least one output enable signal by the through-silicon vias. The addressing unit has a plurality of transmission gates connected to the memory unit, wherein the addressing unit receives a set of selected address signals by the through-silicon vias to turn on one of the transmission gates, wherein if When the transmission gate channel is consistent with the address information stored by the memory unit, the addressing unit outputs the output enable signal received by the memory unit to a node, and the node is coupled to the control unit to transmit the output The signal can be used as the conduction control signal. A ground circuit is coupled to the node, wherein the ground circuit provides a ground voltage to the node if the node does not receive the output enable signal.

The present invention provides an address connection circuit disposed on a wafer to couple between a first end point and a second end point. The address connection circuit includes a control unit, a memory unit, an address unit, and a ground circuit. The control unit is coupled between the first end point and the second end point, wherein the control unit receives a conduction control signal to determine a conduction state of the control unit. The memory unit is configured to store address information specific to the chip, and the memory unit receives at least one output enable signal. The addressing unit has a plurality of transmission gates connected to the memory unit. The addressing unit receives a set of selection address signals to cause one of the transmission gate channels to be turned on. If the transmitted transmission channel is consistent with the address information stored by the memory unit, the addressing unit outputs the output enable signal received by the memory unit to a node, and the node is coupled to the control unit to The output enable signal is transmitted as the conduction control signal. A ground circuit is coupled to the node, wherein the ground circuit provides a ground voltage to the node if the node does not receive the output enable signal.

The present invention further provides an address connection circuit disposed on a wafer, including a control unit, a memory unit, an address unit, and a ground circuit. The control unit is connected to a first end point and a second end point, and an input control end receives a driving signal to determine a conducting state. The memory unit has a plurality of channels, wherein one of the corresponding channels is conductive in the channels, and the memory unit receives an output enable signal output through the channel that is turned on. The addressing unit has a plurality of transmission channels respectively connected to the channels of the memory unit, and receives a selection address signal to turn on one of the transmission channels, wherein the transmission channels have a common output terminal, and the common output The endpoint is connected to the input control of the control unit. An impedance circuit couples the common output terminal to a ground voltage.

The above described features and advantages of the present invention will be more apparent from the following description.

Since the stacked wafers are connected through the through-silicon vias, the input and output signals between the wafers are connected together. In order to distinguish which chip is to be sent to the chip, the present invention provides a three-dimensional integrated circuit wafer addressing circuit. To select the transmission path of the signal between the stacked wafers.

The invention is illustrated by the following examples, but the invention is not limited to the examples. Some embodiments that are also mentioned may also be combined with each other as appropriate.

4 is a schematic diagram of a three-dimensional integrated circuit wafer address connection circuit according to an embodiment of the invention. Referring to FIG. 4, a schematic diagram of a three-dimensional integrated circuit wafer address connection circuit is provided at an I/O terminal in each wafer of a stacked wafer, and the connection state of an I/O terminal 300 to the internal circuit 212 can be controlled. I/O endpoints 300 having the same properties and other control signal endpoints in each of the stacked wafers are connected by through-pass twinned vias 208. Other control signal endpoints include, for example, an output enable signal endpoint (OE) 302, an enable control endpoint (CE) 304, and an address control endpoint (X1, X2...Xn) 306, etc., the number of which depends on Actually, for example, the address control endpoint 204 is an n-bit address to control the selection of 2 ⁿ wafers. Of course, the address control endpoint 204 can also be equal to one-to-one correspondence with the number of stacked chips. The Enable Control Endpoint (CE) 304 is also set as required by the design. Moreover, the I/O endpoint 300 and the internal circuit 212 are only described as an example. As will be apparent from the practical application of Figure 10 below, there will typically be multiple I/O terminals 300 on the wafer connected to separate internal circuits.

The control unit 204 is coupled between the I/O terminal 300 and the internal circuit 212 by a through-silicon via 208. The control unit 204 accepts a conduction control signal output from the addressing unit 202 to determine a conduction of the control unit 204. status.

The memory unit 200 is used to store address information of the wafer. The memory unit 200 receives at least one output enable signal (OE) through the through-silicon via. Memory unit 200, for example, utilizes channel 210 to store the address of the wafer. The sequential position at which channel 210 is turned on represents the address of the wafer.

The addressing unit 202 has a plurality of transmission gates connected to the memory unit 200. The addressing unit 202 receives a set of selection address signals (X1, X2 ... Xn) through the through-holes 208 to enable one of the transmission gates to be turned on. The transmission gate channel is formed, for example, by a plurality of transmission gates, but the conduction or disconnection of the transmission gate is controlled by the selection address signal (X1, X2...Xn). Thus, for example, only one transmission gate channel will be fully conductive.

If the turned-on transmission gate channel coincides with the address information memorized by the memory unit 200, the addressing unit 202 outputs the output enable signal (CE) received by the memory unit 202 to a node. The node is coupled to the control unit 204 to transmit an output enable signal (CE) as a conduction control signal to drive the control unit 204.

A ground circuit 206 is also coupled to the node, wherein if the node does not receive an output enable signal (CE), the ground circuit provides a ground voltage to the node.

Some implementation examples are described below. FIG. 5 is a schematic diagram of an address connection circuit for two stacked wafers according to an embodiment of the invention. Referring to FIG. 5, the wafer 250 (wafer 1) has two channels in the memory unit 200, wherein the channel MU-1 is turned on, and the portion that turns on the MU-2 is not turned on, for example, by erasing. In addition, the wafer 252 (wafer 2) is erased by the channel MU-1 of the memory unit 200 to disconnect the channel MU-1 to maintain the channel MU-1 conducting. In other words, the conduction states of the two channels MU-1 and MU-2 are stored corresponding to the address information of the respective wafers 250, 252.

The OE signal is, for example, 1 for output or input. If the address signal X is 0 at this time, the OE signal of the wafer 250 can be sent to the control unit 204 through the upper transmission gates of the channel MU-1 and the address unit 202, and the control unit 204 is turned on. Data can be transferred between the I/O terminals of the wafer and internal circuitry 212. Here, the control of the transmission gate is turned on when the input signal is 0, and is not turned on when the input signal is 1. The transmission gate of the other channel in the address unit 202 is a complementary signal for receiving the address signal X. Therefore, when X is 0, only the upper transmission gate is turned on, and is in conduction with the channel MU-1 of the memory unit 200.

In addition, on the chip 252, since the MU-1 of the memory cell 200 is erased and disconnected, and the address signal X in the address unit 202 is turned ON, the transmission gate above the bit is enabled, so that the OE signal cannot be sent. . At this time, the ground circuit 206 automatically turns off the transfer gate of the control unit 204, so that the data cannot be input or output to the wafer 252. Moreover, if the signal of the OE is 0, the wafer 250 and the chip 252 cannot input or output data regardless of the address signal X being 0 or 1, and are in an isolated state.

According to the same mechanism, the address signal X is 1 to select the chip 252, and the OE signal is transmitted to the control unit 204 to drive the conduction state of the control unit 204.

In the present embodiment, the control unit 204 is of a design using an analog circuit so that the control unit 204 is only conductive or non-conductive. However, the control unit 204 can also employ the design of a digital circuit. The design of the digital circuit allows for control of the direction of transmission. Moreover, the control unit 204 can also be regarded as a switching circuit in general, and is not limited to a specific circuit.

6 is a schematic diagram of an address connection circuit for four stacked wafers according to an embodiment of the invention. See Figure 6. Since four wafers are stacked together, the memory unit 200 has four channels ML1, ML2, ML3, and ML4, and the operation of selecting the first wafer is taken as an example.

In the present embodiment, the control unit 204' employs, for example, a three-state transmission gate buffer circuit that can control the input/output direction or the high impedance state. The addressing unit 202 utilizes the address signals of the XY two-element, and the group has four sets of transmission gate channels. The ground circuit 206 uses a simple resistor grounding method. In the present embodiment, the memory unit 200 has four channels, for example, designed by blocking circuits. The memory unit 200 with addressing may use a laser to cut the metal line, use a current blown metal line or a reticle type read only memory to block the path of the circuit to achieve the purpose of addressing, but the actual design It is not limited to the manner described. Here, the method of address memory is, for example, cutting off ML2, ML3, and ML4, leaving ML1 as a channel for conduction.

When the address signal is X=0, Y=0, only the first channel of the addressing unit 202 is turned on, which is consistent with the channel of the memory unit 200, thus forming a complete conduction path. The OE signal can be output to the control unit 204' via ML1, allowing the internal circuit 212 to be connected to the I/O endpoint.

Conversely, because the other wafers are blocked, the input of control unit 204' is forced to ground by ground circuit 206. At this time, the control unit 204' is in a high impedance state, and data cannot be output or input. Therefore, when the address X=0, Y=0, only the wafer 1 can operate.

Also, if the control unit 204' is a digital circuit design that allows for control of the transmission direction, another control signal DIR is also used to determine the direction of transmission of the control unit 204'.

Regarding the design of the memory unit 200, there are various ways to achieve it. Some embodiments will be described below. FIG. 7 is a schematic diagram showing a design change of the circuit of the memory unit 200 of FIG. 6. Referring to FIG. 7, the memory unit 200 uses, for example, a memory characteristic of a non-volatile memory (NVM) to make the memory unit 200 have a high-impedance open circuit and a low-impedance short-circuit state as the wafer address selection. Non-volatile memory can be divided into two types, one is a two-terminal element such as a memory unit 200', and a voltage or current is applied to both ends to change the state of the memory. By using XY addressing to open the corresponding transmission gate and applying voltage or current to the OE terminal, the memory can be written. The non-volatile memory elements are, for example, non-volatile memory elements such as STT-RAM, PCM, and RRAM. Another type of non-volatile memory component is a three-terminal component, as shown by memory cell 200'', except that the two endpoints of the original memory are turned on, and the third endpoint CE is required to perform the auxiliary write operation. The CE endpoint can be connected to the memory or adjacent to the memory without being connected to the memory endpoint, such as a non-volatile memory component such as Flash or MRAM.

8-9 are schematic diagrams showing an address connection circuit according to an embodiment of the invention. Referring to FIG. 8, in a practical application, the memory unit 200 is realized by, for example, a non-volatile memory element using a three-terminal element, so that it requires an auxiliary control of the CE end point to achieve a high impedance or low impedance state. Conducted and non-conducting channel control.

Referring to Figure 9, which is similar to the design of Figure 6, is for the selection of four wafers. The control unit 204 of Figure 6 is a design that employs a digital circuit. However, in the design of Fig. 9, the control unit 204' is not a design of a digital circuit but a design of an analog circuit.

If more wafers are stacked together, the number of channels of memory unit 200 and addressing unit 202 can be increased. Since one bit can correspond to two channels, the relationship between the number of bits n of the address signal and the number of wafers is preferably 2 ⁿ wafers. The transfer gates in addressing unit 202 may also employ other equivalent designs.

FIG. 10 is a schematic diagram showing the operation of a three-dimensional integrated circuit wafer address connection circuit according to an embodiment of the invention. Referring to FIG. 10, in comparison with the conventional operation of FIG. 3, the present embodiment employs a newly designed three-dimensional integrated circuit wafer address connection circuit, since the connection state between each of the through-silicon vias 130 and the internal circuit 132 can be conveniently selected. The present invention, as the direction of transmission of the arrows, allows for an internal transfer path between the wafers, as indicated by the path of the arrows, which makes it easier to improve the operational performance of the stacked wafers.

Moreover, the address connection circuit of the present invention is also not necessarily limited to application to a wafer structure stacked by through-silicon via. In practical applications, the circuit design of the present invention can be employed as long as there is an operational mechanism between the two points that requires a specific address to open the connection.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100. . . Circuit substrate

102. . . Sealing layer

104. . . Wafer

106. . . Straight through perforation

108. . . Solder pad

120. . . I/O pad

122, 130. . . Straight through perforation

124, 134. . . Control clearance

126, 132. . . Internal circuit

200, 200’, 200’’. . . Memory unit

202. . . Addressing unit

204, 204’. . . control unit

206. . . Ground circuit

208. . . Through crystal perforation

210. . . aisle

212. . . Internal circuit

300. . . I/O endpoint

302. . . Output enable signal endpoint

304. . . Enable control endpoint

306. . . Address control endpoint

FIG. 1 is a schematic cross-sectional view showing a conventional three-dimensional integrated circuit wafer composed of through-pass twinning.

FIG. 2 is a schematic diagram showing the operation mechanism of a conventional stacked wafer with through-twisted vias.

FIG. 3 is a schematic diagram showing another operational mechanism of a conventional stacked wafer with through-twisted vias.

4 is a schematic diagram of a three-dimensional integrated circuit wafer address connection circuit according to an embodiment of the invention.

FIG. 5 is a schematic diagram of an address connection circuit for two stacked wafers according to an embodiment of the invention.

6 is a schematic diagram of an address connection circuit for four stacked wafers according to an embodiment of the invention.

FIG. 7 is a schematic diagram showing a design change of the circuit of the memory unit 200 of FIG. 6.

8-9 are schematic diagrams showing an address connection circuit according to an embodiment of the invention.

FIG. 10 is a schematic diagram showing the operation of a three-dimensional integrated circuit wafer address connection circuit according to an embodiment of the invention.

200. . . Memory unit

202. . . Addressing unit

204. . . control unit

206. . . Ground circuit

208. . . Through crystal perforation

210. . . aisle

212. . . Internal circuit

300. . . I/O endpoint

302. . . Output enable signal endpoint

304. . . Enable control endpoint

306. . . Address control endpoint

Claims (26)

A three-dimensional integrated circuit wafer address connection circuit is disposed in each of a stacked wafers, the stacked wafer having a plurality of through-twisted vias (TSVs), each of the through-twisted vias being directly connected to each of the The same signal terminal on the chip includes: a control unit, wherein the pass-through transistor is coupled between an output/input terminal and an internal circuit, wherein the control unit receives a conduction control signal Determining a conduction state of the control unit; a memory unit for storing address information of the chip, wherein the memory unit receives at least one output enable signal by the through-silicon vias; a transmission gate is connected to the memory unit, wherein the addressing unit receives a set of selection address signals by the through-silicon vias to turn on one of the transmission gates, wherein if the transmission gate is turned on When the address information is consistent with the address information stored by the memory unit, the addressing unit outputs the output enable signal received by the memory unit to a node, and the node The control unit is coupled to transmit the output enable signal as the conduction control signal; and a ground circuit coupled to the node, wherein the ground circuit provides a ground voltage if the node does not receive the output enable signal Give the node. The three-dimensional integrated circuit chip address connection circuit according to claim 1, wherein the control unit is a digital circuit, and the conduction state comprises a directional conduction mode. The three-dimensional integrated circuit chip address connection circuit according to claim 1, wherein the control unit is an analog circuit, and the conduction state has two conduction modes of conduction and non-conduction. The three-dimensional integrated circuit chip address connection circuit of claim 1, wherein the memory unit comprises at least two channels, and only one of the channels is turned on to memorize the address information of the chip. The three-dimensional integrated circuit chip addressing connection circuit of claim 4, wherein the plurality of first ends of the transmission gates of the addressing unit are respectively connected to the channels of the memory unit, and the transmissions are A plurality of second ends of the gate channel are connected to the node, wherein the group selection address signals control the plurality of transmission gates of the transmission gate channels to determine that only one of the transmission gate channels is conductive. The three-dimensional integrated circuit chip address connection circuit according to claim 5, wherein the set of selection address signals is n-bit data, thereby generating a selection of 2 ⁿ channels. The three-dimensional integrated circuit wafer address connection circuit of claim 4, wherein the channels of the memory unit are composed of at least two metal lines, but only the metal lines corresponding to one of the wafers are turned on. The three-dimensional integrated circuit chip address connection circuit according to claim 4, wherein the channels of the memory unit are composed of at least two read-only memory cells, but only the one-only read of the wafer The data of the memory cell turns the channel on. The three-dimensional integrated circuit chip address connection circuit of claim 8, wherein the memory unit further receives an auxiliary signal by the through-silicon vias to control the read-only memory cells. The three-dimensional integrated circuit chip address connection circuit according to claim 1, wherein the ground circuit is an impedance circuit. The three-dimensional integrated circuit chip address connecting circuit of claim 1, wherein the stacked chip comprises 2 ⁿ chips, and the set of selected address signals is an n-bit signal to select one of the wafers. . The three-dimensional integrated circuit chip address connection circuit according to claim 1, wherein the control unit further receives a transmission direction control signal by the through-silicon vias to determine data when the control unit is turned on. Transmission direction. An address connection circuit is disposed on a chip to be coupled between a first end point and a second end point, and includes: a control unit coupled between the first end point and the second end point, The control unit receives a conduction control signal to determine a conduction state of the control unit; a memory unit for storing address information specific to the chip, the memory unit receiving at least one output enable signal; the address unit, Having a plurality of transmission gates connected to the memory unit, the addressing unit receiving a set of selection address signals to cause one of the transmission gate channels to be turned on, wherein if the transmission gate channel that is turned on is memorized by the memory unit When the address information is consistent, the addressing unit outputs the output enable signal received by the memory unit to a node, and the node is coupled to the control unit to transmit the output enable signal as the conduction control signal; A ground circuit is coupled to the node, wherein if the node does not receive the output enable signal, the ground circuit provides a ground voltage to the node. The address connection circuit of claim 13, wherein the control unit is a digital circuit, and the conduction state comprises a directional conduction mode. The address connection circuit of claim 13, wherein the control unit is an analog circuit, and the conduction state has two conduction modes of conduction and non-conduction. The address connection circuit of claim 13, wherein the memory unit comprises at least two channels, and only one of the channels is specifically turned on to memorize the address information of the wafer. The address connection circuit of claim 16, wherein the plurality of first ends of the transmission gates of the addressing unit are respectively connected to the channels of the memory unit, and the plurality of transmission gate channels are The second end is connected to the node, wherein the group selection address signal controls the plurality of transmission gates of the transmission gate channels to determine that only one of the transmission gate channels is conductive. The three-dimensional integrated circuit chip address connection circuit according to claim 17, wherein the set of selection address signals is n-bit data, thereby generating a selection of 2 ⁿ channels. The address connection circuit of claim 16, wherein the channels of the memory unit are composed of at least two metal lines, but only the metal lines corresponding to one of the wafers are turned on. The address connection circuit of claim 16, wherein the channels of the memory unit are composed of at least two read-only memory cells, but only the data of the read-only memory cell corresponding to one of the wafers is made. The channel is turned on. The address connection circuit of claim 20, wherein the memory unit further receives an auxiliary signal to control the read only memory cells. The address connection circuit of claim 13, wherein the ground circuit is an impedance circuit. The address connection circuit of claim 13, wherein the stacked chip comprises 2 ⁿ chips, and the set of selection address signals is an n-bit signal to correspondingly select one of the wafers. The address connection circuit of claim 13, wherein the control unit further receives a transmission direction control signal to determine a data transmission direction when the control unit is turned on. An address connection circuit is disposed on a chip, comprising: a control unit connected to a first end point and a second end point, and an input control end receiving a driving signal to determine a conducting state; a memory unit, There are a plurality of channels, wherein one of the corresponding channels in the channels is conductive, the memory unit receives an output enable signal through the channel output; the address unit has a plurality of transmission channels respectively connected to The channels of the memory unit receive a selected address signal to turn on one of the transmission channels, wherein the transmission channels have a common output terminal, and the common output terminal is connected to the input control of the control unit And an impedance circuit coupling the common output terminal to a ground voltage. The address connection circuit of claim 25, wherein the address connection circuit is also connected to a plurality of connection terminals corresponding to the other at least one of the wafers, wherein the address is turned on by the channel in the memory unit. The chips cooperate with the selected address signal to determine the conduction state of the control unit on the wafer.