TWI428882B - Source driver device and method of fabricating the same - Google Patents

Description

Source driver and method of forming same

The present invention relates to source drivers, and more particularly to source drivers for components having different threshold voltage values.

Flat panel display technology plays a pivotal role in the consumer entertainment electronics industry. A conventional flat-panel display, such as a liquid crystal display, exhibits an image by changing the alignment direction of the liquid crystal molecules by driving the wafer set to output a voltage, and forming a displayed image by the transmittance of each dot. The driving chip mainly includes two parts of a source driver and a gate driver. When a pixel is colored, a gate transistor switch is controlled by a gate driver, and the source driver inputs three primary color signals of R, G, and B, respectively. The gate driver is responsible for the switching action of each column of the display. When the display performs the scanning operation column by column, the gate driver cooperates with opening an entire column of switches to allow the source driver to perform signal input. The source driver is responsible for the input action of each pixel of the display. When the gate driver opens an entire column of switches, the source driver immediately inputs the column data voltage to provide the signal required for displaying the screen. When the display gradually increases the resolution, brightness and reaction speed, the more the driver chip needs to develop toward the high frequency and high voltage, in order to meet the high speed scanning frequency and fast driving demand. One way to improve the switching frequency of the transistor elements within the wafer is to lower the threshold voltage of the transistor element, i.e., to employ a low voltage component in the driver wafer. However, the low threshold voltage of the low voltage component also causes gate leakage current, which in turn increases the power consumption of the driver wafer, especially the source driver with a large number of transistors. The conventional drive wafer structure, as shown in FIG. 1, includes a low voltage logic region 20 and a high voltage region 30. The low voltage logic region 20 includes logic circuit regions that require high speed operations, such as a logic controller 21, a shift register (Level Shift Register) 22, a data register 23, and a data latch (Data). Latch) 24, etc., so the above region uses a low voltage transistor element having a low threshold voltage value to increase the operating speed to pursue operational efficiency; and the high voltage region 30 includes a circuit region requiring a large driving voltage, such as a digital analog converter ( Digital/Analog Converter 31 and Output Buffer 32, etc., so the above region uses a high voltage transistor element having a higher threshold voltage value to achieve lower power loss. However, in order to further optimize the performance of the driving chip, the low voltage logic region 20 can be further subdivided into circuit regions having different design requirements, such as regions with low power loss, regions with high operating current, and high processing speeds. Area and so on. While conventional low voltage logic regions 20 typically use transistor elements of the same threshold voltage value, there is no need for performance optimization in cutting-edge display technology.

Accordingly, the present invention provides a source driver including a high voltage circuit region; a first low voltage logic circuit region including a plurality of first transistor elements, wherein the first transistor elements are configured to have a first threshold voltage value to meet a first operational requirement; a second low voltage logic circuit region electrically coupled to the first low voltage logic circuit region, the second low voltage logic circuit region including a plurality of second transistor components, wherein the The second transistor element is configured to have a second threshold voltage value to comply with a second operational requirement; wherein the first threshold voltage value is not equal to the second threshold voltage value.

The invention further provides a method for forming a source driver, comprising: a substrate; performing a first well ion implantation on the first portion of the substrate to form at least one high voltage component well region; and the second portion of the substrate Performing a second well region ion implantation to form at least one first low voltage component well region; performing a third well region ion implantation on the third portion of the substrate to form at least one second low voltage component well region, wherein The concentrations of the ion implantation in the first, second, and third well regions are different; forming a plurality of the plurality of high-voltage component well regions, at least one first low-voltage component well region, and at least one second low-voltage component well region a gate structure, a second gate structure, and a third gate structure; forming a plurality of sources and a plurality of drain electrodes under the first gate structure, the second gate structure, and the third gate structure, respectively A plurality of first transistor elements, a plurality of second transistor elements, and a plurality of third transistor elements are defined in the first and second low voltage component well regions and the high voltage component well region, respectively.

The invention further provides a method for forming a source driver, comprising: a substrate; performing a first well ion implantation on the first portion of the substrate to form at least one high voltage component well region; and the second portion of the substrate Performing a second well region ion implantation to form at least a first low voltage component well region; forming a plurality of first gate structures, a second gate structure, and a third gate structure on the substrate, wherein the first The gate structure and the second gate structure are respectively located on the at least one high voltage component well region and the at least one first low voltage component well region; performing a first lightly doped ion implantation to be below the second gate structure Forming a plurality of first lightly doped drains; performing a multi-stage third ion implantation on the third portion of the substrate to form at least one second low voltage component well region and a plurality of second lightly doped drain electrodes Forming a plurality of sources and a plurality of drains respectively in the first gate structure, the second gate structure, and the third gate structure to respectively separate the high voltage component well region and the first and second low voltage components Well area defines a number of first a crystal element, a plurality of second transistor elements, and a plurality of third transistor elements; wherein the impurity concentrations of the high voltage component well region, the first low voltage component well region, and the second low voltage component well region are different, and the first The lightly doped drain is different from the impurity concentration of the second lightly doped drain.

2A is a schematic diagram of a source driver 100 of the present invention. The source driver 100 includes at least one high voltage circuit region 110 and a low voltage circuit region 120, wherein the high voltage circuit region 110 and the low voltage circuit region 120 are functionally coupled to each other. In some embodiments, the low voltage circuit region 120 can be further divided into two regions, including a first low voltage logic circuit region 120-1 and a second low voltage logic circuit region 120-2, wherein the first low voltage logic circuit region 120-1 and The second low voltage logic circuit regions 120-2 are functionally coupled to each other. The transistor elements in the first low voltage logic circuit region 120-1 and the second low voltage logic circuit region 120-2 have different threshold voltages to respectively conform to the first low voltage logic circuit region 120-1. The first operational requirement and the second operational requirement preset by the second low voltage logic circuit region 120-2. In other embodiments, as shown in FIG. 2B, the low voltage circuit region 120 can be further divided into N regions, including a first low voltage logic circuit region 120-1 to an Nth low voltage circuit region 120-N, wherein the first low voltage logic The circuit region 120-1 to the Nth low voltage circuit region 120-N are functionally coupled to each other, where N is a positive integer greater than one. The transistor elements in the first low voltage circuit region 120-1 to the Nth low voltage circuit region 120-N respectively have different threshold voltage values to respectively meet predetermined different operational requirements.

3A through 3C are schematic views showing the manufacturing process of the source driver 350 of the present invention. For the sake of brevity, only a portion of the transistor elements that make up the source driver 350 are shown in the drawings. First, as shown in FIG. 3A, a substrate 300 is provided, and an isolation region 301 is formed on the substrate 300, and then a doping process is performed to form a plurality of well regions, including a high voltage well region 310, a first low pressure well region 320 and a first Two low pressure well zones 330.

In some embodiments, the substrate 300 can be a germanium substrate. The substrate 300 may also optionally include a semiconductor element such as crystalline germanium or germanium, or the compound semiconductor includes tantalum carbide, gallium nitride, gallium arsenide, indium phosphide, indium arsenide, and/or gallium antimonide; and an alloy compound. It includes SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP, or a combination of the above materials. The substrate 300 can also be an insulating layer (SOI), a doped epitaxial layer, or a multilayer compound semiconductor structure.

Isolation regions 301 are used to isolate several regions, including different well regions on substrate 300. In some embodiments, the isolation region 301 can use electrical isolation techniques such as local oxidation (LOCOS), shallow trench isolation (STI), or deep trench isolation (DTI) to isolate the transistor component activity. Area (Active Area). In one embodiment, the step of forming shallow trench isolation includes a lithography process, and forming a trench on the substrate using dry etching or wet etching; and forming one or several dielectric layers by chemical vapor deposition Fill the groove.

The high pressure well region 310, the first low pressure well region 320, and the second low pressure well region 330 may be doped using plasma implantation (PLAD) or ion implantation. Each of the above-mentioned Mitsui districts includes an N-type well region and a P-type well region, and are independently doped using N-type impurities such as phosphorus or arsenic, and P-type impurities such as boron or BF _{2 ,} respectively. The well region of the same doping type in the high pressure well region 310, the first low pressure well region 320 and the second low pressure well region 330 of the present invention has different doping concentrations, by changing the first low pressure well region 320 and the second low pressure region. The well region doping concentration of well region 330 is such that the low voltage logic circuit region has transistor elements of different threshold voltage values. In a specific embodiment, a reverse grade well doping process is performed in the P-type well region by ion implantation of different energies. The P-type impurity concentration of the high-pressure well region 310 is about 1.0e+12 to 5.0e+12, and the P-type impurity concentration of the first low-pressure well region 320 is about 1.0e+12 to 1.0 per square centimeter. e+13, the P-type impurity concentration of the second low-pressure well region 330 is about 1.5e+12 to 1.5e+13 per square centimeter. In addition, in the high-pressure well region 310, high-pressure DDD (Double Diffused Drain) region 317 is simultaneously doped. After the doping of each process step is completed, the doping impurities may be diffused to a desired depth range through a suitable thermal process to form a high-pressure well region 310 (including the high-voltage DDD region 317) as shown in FIG. 3A, The first low pressure well region 320 and the second low pressure well region 330.

Next, as shown in FIG. 3B, gate structures G1, G2, and G3 are formed on the high voltage well region 310, the first low pressure well region 320, and the second low pressure well region 330, respectively. Each of the gate structures includes a gate dielectric layer and a gate electrode layer. First, gate dielectric layers 311, 321 and 331 are formed on the high voltage well region 310, the first low pressure well region 320 and the second low voltage well region 330, respectively. The gate dielectric layers 321 and 331 located above the first low pressure well region 320 and the second low voltage well region 330, respectively, have the same thickness. The gate dielectric layer 311 on the high voltage well region 310 has a higher thickness than the gate dielectric layers 321 and 331 and is resistant to high voltage. The gate dielectric layers 311, 321 and 331 may be made of an insulating material such as tantalum nitride, hafnium oxide, tantalum carbide, niobium oxynitride or niobium-doped tantalum carbide, or high dielectric constant materials such as HfO2, HfON and HfSiON. -K material). The gate dielectric layers 311, 321 and 331 can use dual gate thermal oxidation (Dual Gate Oxide), plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), sub-atmospheric chemical gas. Formation by techniques such as phase deposition (SACVD), atomic layer deposition (ALD), or plasma enhanced atomic layer deposition (PEALD).

Gate electrode layers 312, 322, and 332 are formed over gate dielectric layers 311, 321, and 331, respectively, to form gate structures G1, G2, and G3. The gate electrode layer described above can be grown to a suitable thickness using any suitable process. In some embodiments, the gate electrode layers 312, 322, and 332 can be a polysilicon layer or a metal layer.

As shown in FIG. 3C, respectively, between the gate structure G2 (the gate electrode layer 322 + the gate dielectric layer 321) and the isolation region 301, and the gate structure G3 (the gate electrode layer 332 + the gate) Between the dielectric layer 331) and the isolation region 301, lightly doped drain layers 323 and 333 are doped. The lightly doped drain layers 323 and 333 here have the same doping concentration. The spacer layers 314, 324, and 334 are then formed along the sidewalls of the gate structures G1, G2, and G3; then a high concentration doping process is performed between the spacer layers 314, 324, and 334 and the isolation region 301, respectively, to form a drain region. The source regions 315, 325, and 335 are formed to form the transistor elements 316, 326, and 336. The transistor elements 316, 326, and 336 include a plurality of N-type transistor elements and a P-type transistor element, respectively. For the sake of brevity, only some of the transistor components are shown in the figure.

The drain region and the source regions 315, 325, and 335 may use a plasma doping method or an ion beam implantation method, and select a suitable doping impurity such as an N-type impurity such as phosphorus depending on whether the transistor element is N-type or P-type. Or arsenic, or P-type impurities such as boron or BF ₂ , and implant at the appropriate impurity concentration.

A spacer is formed along the sidewall of the gate structure. In one embodiment, a dielectric layer can be deposited over the gate structure and substrate 300, and then the dielectric layer is etched to form patterned spacer layers 314, 324, and 334. The dielectric layer that can be used to form the spacer layers 314, 324, and 334 can include, for example, tantalum nitride, hafnium oxide, tantalum carbide, hafnium oxynitride, nitride silicon carbide (SiCN), or other suitable materials, as well as the above. Various combinations of materials. The dielectric layer can be plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), sub-atmospheric chemical vapor deposition (SACVD), atomic layer deposition (ALD), or plasma strengthening. The formation of technologies such as atomic layer deposition (PEALD).

Finally, an ohmic contact metal electrode (not shown) is formed on the drain and source of the transistor elements 316, 326, and 336, respectively, to form the drain and source of the transistor elements 316, 326, and 336. External electrical connections, and a back end of line, are used to functionally couple the transistor elements 316, 326, and 336 with metal wire layers (not shown) to form the source driver 350. The above process method utilizes different doping concentrations in the well region to cause the low voltage circuit regions in the source driver 350 to have transistor elements of different threshold voltages to achieve various design requirements.

The present invention provides another method of forming source driver 450, shown in Figures 4A through 4C. For the sake of brevity, only a portion of the transistor elements that make up the source driver 450 are shown in the drawings. First, a substrate 400 is provided, and an isolation region 401 is formed thereon, followed by a doping process to respectively form a high voltage well region 410 having different doping concentrations, a first low pressure well region 420 and a second low pressure well region 430, and a high voltage. DDD (Double Diffused Drain) area 417, as shown in Figure 4A. The above steps are substantially the same as the embodiment of the above FIG. 3A. Next, as shown in FIG. 4B, the pattern is defined by the lithography process and the gate structures G1, G2, and G3 are formed, including the gate dielectric layers 411, 421, and 431, and the gate electrode layers 412, 422, and 432. The above steps are substantially the same as the embodiment of the above FIG. 3B.

Next, as shown in FIG. 4C, respectively, between the gate structure G2 (the gate electrode layer 422 + the gate dielectric layer 421) and the isolation region 401, and the gate structure G3 (the gate electrode layer 432 + the gate electrode The lightly doped drain layers 423 and 433 are doped between the electrical layer 431) and the isolation region 401. The lightly doped drain layers 423 and 433 here have different doping concentrations. Spacer layers 414, 424, and 434 are then formed on the sidewalls of the gate structures G1, G2, and G3, respectively. A high concentration doping process is then performed between spacer layers 414, 424, and 434 and isolation region 401, respectively, to form drain and source regions 415, 425, and 435, and to form transistor elements 416, 426, and 436.

The process of lightly doping the drain layers 423 and 433 may use a plasma doping method or an ion beam implantation method, and select a suitable doping impurity such as an N type impurity such as phosphorus or an N type or a P type. Arsenic, or P-type impurities such as boron or BF ₂ . Or with an opposite type of lightly doped bungee layer. The source driver of the present invention is formed with different threshold voltages by using the first low-pressure well region 420 and the second low-voltage well region 430 of different doping concentrations, and the lightly doped drain layers 423 and 433 of different doping concentrations. The value of the low-voltage transistor component achieves fine-tuning component characteristics to meet the design requirements of different circuit regions in the low-voltage logic circuit region. In some embodiments, the impurity concentration of the lightly doped drain layers 423 and 433 may range from about 1.0e+13 to 7.0e+14 per square centimeter.

The high-density doping process of the drain region and the source regions 415, 425, and 435 may adopt a plasma doping method or an ion beam implantation method, and select a suitable doping impurity for the N-type or P-type according to the transistor component. For example, an N-type impurity such as phosphorus or arsenic, or a P-type impurity such as boron or BF _{2 is} implanted at a suitable impurity concentration to form transistor elements 416, 426, and 436. The above transistor element includes an N-type element and a P-type element. The transistor elements 426 and 436 of the same doping type have different threshold voltage values to meet the design requirements of different circuit regions in the low voltage logic circuit region.

Finally, a metal electrode (not shown) having an ohmic contact is formed on the drain and source of the transistor elements 416, 426, and 436, respectively, to form an external electrical connection, and a back end process is performed. Of line), the transistor elements 416, 426, and 436 are functionally coupled using a metal wire layer (not shown) to form the source driver 450. The above process method utilizes changing the doping concentration of the well region and the lightly doped drain to cause the low voltage circuit regions in the source driver 450 to have different critical voltage transistor components to achieve various design requirements.

The present invention provides another method of forming source driver 550, shown in Figures 5A through 5C. For the sake of brevity, only a portion of the transistor elements that make up the source driver 550 are shown in the drawings. First, as shown in FIG. 5A, a substrate 500 is provided, and an isolation region 501 is formed thereon, followed by a doping process to respectively form a high voltage well region 510 having different doping concentrations, a first low pressure well region 520, and a high voltage. DDD area 517.

Next, as shown in FIG. 5B, the pattern is defined by the lithography process to form the gate structures G1, G2, and G3, respectively. The gate structures G1, G2, and G3 include gate dielectric layers 511, 521, and 531 and gate electrode layers 512, 522, and 532, respectively, wherein the gate structures G1, G2 are located in the high voltage well region 510 and the first low pressure well region, respectively. Above 520.

Next, as shown in FIG. 5C, the lightly doped gate layer 523 is doped between the gate structure G2 (the gate electrode layer 522 + the gate dielectric layer 521) and the isolation region 501. Between the gate structure G3 (the gate electrode layer 532 + the gate dielectric layer 531) and the isolation region 501, a second low-voltage well region 530 and a lightly doped gate layer 533 are formed in the same doping process step. The lightly doped drain layers 533 and 523 here have different doping concentrations. The second low pressure well region 530 here is different from the first low pressure well region 520. Then, spacer layers 514, 524, and 534 are formed along the sidewalls of the gate structures G1, G2, and G3; then a high concentration doping process is performed between the spacer layers 514, 524, and 534 and the isolation region 501, respectively, to form a drain region. And source regions 515, 525, and 535, and constitutes transistor elements 516, 526, and 536. The transistor elements 516, 526, and 536 each include a plurality of N-type elements and P-type elements, respectively. For the sake of simplicity, only a portion of the transistor elements are shown.

The doping step of forming the lightly doped drain region 533 and the second low pressure well region 530 can be performed continuously in the same process hierarchy. The high energy ion beam implantation method is used to change the incident angle and energy of the ion beam, so that the concentration and distribution of impurities in each doping step meet the requirements of the transistor element. The doping concentration of the first low-pressure well region 520 and the second low-pressure well region 530 are different, and the doping concentrations of the lightly doped bungee regions 523 and 533 are also different, so that the same doping type of electricity in different well regions is different. Crystal elements have different threshold voltage values. In one embodiment, an ion beam having an energy of about 80 to 550 KeV is implanted to form a second low pressure well region 530. The impurity concentration of the second low pressure well region 530 is approximately 5.0e+12 to 3.0e+13 per square centimeter. The lightly doped drain regions 523 and 533 can be formed by plasma doping or ion beam implantation, wherein the impurity concentration of the lightly doped drain region 523 is different from the impurity concentration of the lightly doped drain region 533, thereby further Accurately adjust the critical voltage value of the transistor component.

The formation of the drain region and the source regions 515, 525, and 535 may use a plasma doping method or an ion beam implantation method, and select a suitable dopant impurity such as an N-type impurity as the N-type or P-type of the transistor element. Phosphorus or arsenic, or P-type impurities such as boron or BF ₂ , are implanted at an appropriate impurity concentration.

Finally, a metal electrode (not shown) having an ohmic contact is formed on the drain and source of the transistor elements 516, 526, and 536, respectively, to form an external electrical connection, and a back end process is performed. Of line), the transistor elements 516, 526, and 536 are functionally coupled using a metal wire layer (not shown) to form the source driver 550. The above process method utilizes an additional doping step to form well regions having different doping concentrations and lightly doped drains, such that the low voltage circuit regions in the source driver 550 have different threshold voltages of the transistor elements to achieve various differentities. Design requirements.

In summary, the source driver and the manufacturing method thereof disclosed by the present invention utilize different doping concentration of the well region to change the threshold voltage value of the low voltage logic component, thereby optimizing the performance of the low voltage logic circuit, and further The doping concentration of the lightly doped drain region of the low voltage logic element is changed to more precisely modulate the threshold voltage value of the low voltage logic element. The method construction of the embodiment has been described in detail in the foregoing, and it should be understood that various modifications, substitutions and changes may be made without departing from the spirit and scope of the invention. Furthermore, the scope of the invention is not limited to the embodiments of the process, the machine, the production, and the combination of the method, the means and the steps described in the specification. Those of ordinary skill in the relevant art can achieve substantially the same results in accordance with the embodiments disclosed above or in combination with any technical method that has been developed or not yet developed. Accordingly, the scope of patent protection includes the embodiments of the processes, the machines, the production, and the combinations of methods, means and steps described in the context. Each of the patent claims represents a separate embodiment, and thus various patent claims and combinations of various embodiments are within the scope of the patent protection.

20. . . Low voltage logic region

twenty one. . . Logic controller

twenty two. . . Shift register

twenty three. . . Data register

twenty four. . . Data latch

30. . . High pressure area

31. . . Digital analog converter

32. . . Output buffer

100. . . Source driver

110. . . High voltage circuit area

120. . . Low voltage circuit area

120-1. . . First low voltage circuit area

120-2. . . Second low voltage circuit area

120-N. . . Nth low voltage circuit area

300. . . Substrate

301. . . quarantine area

310. . . High pressure well area

311. . . Gate dielectric layer

312. . . Gate electrode layer

314. . . Bungee region and source region

315. . . Spacer

316. . . Transistor element

317. . . High voltage DDD area

320. . . First low pressure well area

321. . . Gate dielectric layer

322. . . Gate electrode layer

323. . . Lightly doped bungee zone

324. . . Bungee region and source region

325. . . Spacer

326. . . Transistor element

330. . . Second low pressure well area

331. . . Gate dielectric layer

332. . . Gate electrode layer

333. . . Lightly doped bungee zone

334. . . Bungee region and source region

335. . . Spacer

336. . . Transistor element

350. . . Source driver

400. . . Substrate

401. . . quarantine area

410. . . High pressure well area

411. . . Gate dielectric layer

412. . . Gate electrode layer

414. . . Bungee region and source region

415. . . Spacer

416. . . Transistor element

417. . . High voltage DDD area

420. . . First low pressure well area

421. . . Gate dielectric layer

422. . . Gate electrode layer

423. . . Lightly doped bungee zone

424. . . Bungee region and source region

425. . . Spacer

426. . . Transistor element

430. . . Second low pressure well area

431. . . Gate dielectric layer

432. . . Gate electrode layer

433. . . Lightly doped bungee zone

434. . . Bungee region and source region

435. . . Spacer

436. . . Transistor element

450. . . Source driver

500. . . Substrate

501. . . quarantine area

510. . . High pressure well area

511. . . Gate dielectric layer

512. . . Gate electrode layer

514. . . Bungee region and source region

515. . . Spacer

516. . . Transistor element

517. . . High voltage DDD area

520. . . First low pressure well area

521. . . Gate dielectric layer

522. . . Gate electrode layer

523. . . Lightly doped bungee zone

524. . . Bungee region and source region

525. . . Spacer

526. . . Transistor element

530. . . Second low pressure well area

531. . . Gate dielectric layer

532. . . Gate electrode layer

533. . . Lightly doped bungee zone

534. . . Bungee region and source region

535. . . Spacer

536. . . Transistor element

550. . . Source driver

G1, G2, G3. . . Gate structure

Figure 1 is a schematic diagram showing the structure of a source driving chip;

2A and 2B are schematic views of a source driving chip of the present invention;

3A to 3C are views showing a manufacturing process of the source driver 350 of the present invention;

4A to 4C are views showing a manufacturing process of the source driver 450 of the present invention;

5A to 5C are views showing a manufacturing process of the source driver 550 of the present invention;

100. . . Source driver

110. . . High voltage circuit area

120. . . Low voltage circuit area

120-1. . . First low voltage circuit area

120-2. . . Second low voltage circuit area

120-N. . . Nth low voltage circuit area

Claims (13)

A source driver includes: a high voltage circuit region; a first low voltage logic circuit region, the first low voltage logic circuit region including a plurality of first transistor components, wherein the first transistor components are configured to have a first a threshold voltage value to meet a first operational requirement; and a second low voltage logic circuit region electrically coupled to the first low voltage logic circuit region, the second low voltage logic circuit region including a plurality of second transistor components, wherein The second transistor elements are configured to have a second threshold voltage value to comply with a second operational requirement; wherein the first threshold voltage value is not equal to the second threshold voltage value. The source device of claim 1, wherein the first low voltage logic circuit area comprises a logic controller, a level shift register, and a data register. And Data Latch. The source device of claim 1, wherein the second low voltage logic circuit area comprises a logic controller, a level shift register, and a data register. And Data Latch. The source driver according to claim 1, wherein the high voltage circuit region includes a digital analog converter and an output buffer. The source driver of claim 1, wherein the first low voltage logic circuit region further comprises a plurality of first well regions having a first doping concentration to form the first transistor element; The second low voltage logic circuit region further includes a plurality of second well regions having a second doping concentration to form the second transistor element; wherein the first doping concentration is not equal to the second doping concentration. The source driver of claim 1, wherein the first low voltage logic circuit region further comprises a plurality of first lightly doped drains having a third doping concentration; The second low voltage logic circuit region further includes a plurality of second lightly doped drains having a fourth doping concentration; wherein the third doping concentration is not equal to the fourth doping concentration. The source driver of claim 1, further comprising at least one additional circuit region electrically coupled to the first and second circuit regions, respectively, wherein the additional circuit regions respectively comprise a plurality of transistor elements, Wherein the above-mentioned transistor component in the additional circuit region is configured to have a third threshold voltage value to meet a third operational requirement, the third operational requirement being different from the first and second operational requirements. The source driver of claim 1, wherein the first operation requirement is that the operating clock of the first low voltage logic circuit region is not lower than a first frequency; The operating power consumption of the two low voltage logic circuit regions is lower than a first power. A method of forming a source driver includes: a substrate; performing a first well region ion implantation on a first portion of the substrate to form at least one high voltage component well region; and a second portion of the substrate Performing a second well ion implantation, Forming at least one first low-voltage component well region; performing a third well region ion implantation on a third portion of the substrate to form at least one second low-voltage component well region, wherein the first, second, and The concentration of the ion implantation in the Mitsui area is different; forming a plurality of first gate structures respectively on the at least one high voltage component well region, the at least one first low voltage component well region, and the at least one second low voltage component well region a second gate structure and a third gate structure; and a plurality of sources and a plurality of drain electrodes respectively formed under the first gate structure, the second gate structure and the third gate structure, respectively The first and second low voltage component well regions and the high voltage component well region define a plurality of first transistor elements, a plurality of second transistor elements, and a plurality of third transistor elements. The method of forming a source driver according to claim 9, wherein before forming the source and the drain, the method further comprises: performing a first lightly doped ion on the first transistor. Deploying to form a plurality of first Lightly Doped Drain regions; and performing a second lightly doped ion implantation on the second transistor elements to form a plurality of second lightly doped regions a drain region; wherein the concentration of the first lightly doped ion implant is different from the concentration of the second lightly doped ion implant. The method of forming a source driver according to claim 9, wherein the at least one first low-voltage component well region, the at least one second low-voltage component well region, and the at least one high-voltage component well region respectively comprise at least one N-type a well region and at least one P-type well region, and the first transistor element, the second transistor element and the third transistor element respectively comprise a plurality of N-type MOS field-effect transistors and a plurality of P-type gold oxides Half field effect transistor. A method of forming a source driver includes: a substrate; performing a first well region ion implantation on a first portion of the substrate to form at least one high voltage component well region; and a second portion of the substrate Performing a second well region ion implantation to form at least one first low voltage component well region; forming a plurality of first gate structures, a second gate structure, and a third gate structure on the substrate, wherein The first gate structure and the second gate structure are respectively located on the at least one high voltage component well region and the at least one first low voltage component well region; performing a first lightly doped ion implantation to the second gate Forming a plurality of first lightly doped drains under the polar structure; performing a multi-stage third ion implantation on a third portion of the substrate to form at least one second low voltage component well region and a plurality of second light Doping the drain electrode; and forming a plurality of sources and a plurality of drains respectively in the first gate structure, the second gate structure, and the third gate structure to respectively be in the high voltage component well region and the first , the second low-voltage component well area definition a first transistor component, a plurality of second transistor components, and a plurality of third transistor components; wherein the impurity concentrations of the high voltage component well region, the first low voltage component well region, and the second low voltage component well region are different, And the impurity concentration of the first lightly doped drain and the second lightly doped drain is different. The method of forming a source driver according to claim 12, wherein the at least one high voltage component well region, the at least one second low voltage component well region, and the at least one first low voltage component well region respectively comprise at least one N type a well region and at least one P-type well region, and the first transistor element, the second transistor element and the third transistor element comprise a plurality of N-type MOS field-effect transistors and a plurality of P-type MOS fields Effect transistor.