TWI426627B - Light-emitting diode - Google Patents

Description

Light-emitting diode

The invention relates to a light-emitting diode, in particular to a light-emitting diode having a three-dimensional nanostructure array.

High-efficiency blue, green and white light-emitting diodes made of GaN semiconductor materials have longevity, energy saving, green environmental protection, etc., and have been widely used in large-screen color display, automotive lighting, traffic signals, and plural media. In the fields of display and optical communication, especially in the field of lighting, it has broad potential for development.

A conventional light-emitting diode generally includes an N-type semiconductor layer, a P-type semiconductor layer, an active layer disposed between the N-type semiconductor layer and the P-type semiconductor layer, and a P-type electrode (usually a transparent electrode) disposed on the P-type semiconductor layer. And an N-type electrode disposed on the N-type semiconductor layer. When the light-emitting diode is in an active state, positive and negative voltages are respectively applied to the P-type semiconductor layer and the N-type semiconductor layer, so that holes existing in the P-type semiconductor layer and electrons existing in the N-type semiconductor layer are Photons are generated by recombination in the active layer, and photons are emitted from the light-emitting diodes.

However, the light extraction efficiency of the prior art light-emitting diodes (the light extraction efficiency generally means that the light generated in the active layer is released from the inside of the light-emitting diode) is low, mainly due to the semiconductor (usually nitrogen). The refractive index of gallium is greater than the refractive index of air, and the large angle light from the active layer is totally reflected at the interface between the semiconductor and the air, so that most of the large-angle light is confined inside the light-emitting diode until it is heated. Dissipate in other ways. This is very disadvantageous for the light-emitting diode.

In order to solve the above problems, the prior art improves the light-emitting rate of the light-emitting diode by controlling the growth mode of the gallium nitride. However, the method is complicated in process and high in cost. In the prior art, there is also a method of changing the incident angle of light by using a surface roughening or a surface patterning light emitting surface of the light emitting diode to improve the light extraction rate of the light emitting diode. However, this method can only change the incident angle of the light to a small extent, and the large-angle light with a large incident angle cannot be effectively extracted, which affects the light-emitting rate of the light-emitting diode.

In view of this, it is necessary to provide a light-emitting diode having a high light extraction efficiency.

a light emitting diode comprising: a substrate; a first semiconductor layer, an active layer and a second semiconductor layer are sequentially stacked on one side of the substrate, and the first semiconductor layer is disposed adjacent to the substrate; The first electrode is electrically connected to the first semiconductor layer; a second electrode is electrically connected to the second semiconductor layer; and further comprising a plurality of three-dimensional nanostructures disposed in an array on the surface of the second semiconductor layer away from the substrate And the three-dimensional nanostructure is a stepped structure, and each of the stepped structures includes at least two layers of a mesa structure.

a light emitting diode comprising: a substrate; a first semiconductor layer, an active layer and a second semiconductor layer are sequentially stacked on one side of the substrate, and the first semiconductor layer is disposed adjacent to the substrate; The first electrode is electrically connected to the first semiconductor layer; a second electrode is electrically connected to the second semiconductor layer; and further comprising a plurality of three-dimensional nanostructures disposed in an array on the surface of the first semiconductor layer in contact with the substrate And the three-dimensional nanostructure is a stepped structure, and each of the stepped structures includes at least two layers of a mesa structure.

In comparison with the prior art, in the light-emitting diode of the present invention, a plurality of three-dimensional nanostructures are arranged in an array to form a three-dimensional nanostructure array. Since the three-dimensional nanostructure of the present invention has a stepped structure, which corresponds to at least two layers of a three-dimensional nanostructure or a two-layer photonic crystal structure, the extraction efficiency of the large-angle light of the light-emitting diode can be more effectively improved. Alternatively, when a large-angle light encounters a three-dimensional nanostructure array during propagation to the substrate, it is reflected by the three-dimensional nanostructure array to become a small angle light. On the one hand, the large angle light becomes a small angle light to improve the light extraction efficiency of the light emitting diode. On the other hand, the large angle light becomes a small angle light, which can reduce the propagation path of the light inside the light emitting diode, thereby reducing the light in the light. Loss during the propagation process.

10,20,30,40‧‧‧Lighting diodes

11,21,31,41‧‧‧second electrode

12,22,32,42‧‧‧Base

13,23,33,43‧‧‧first electrode

14,24,34,44‧‧‧First semiconductor layer

15,45‧‧‧Three-dimensional nanostructure

152‧‧‧First round table

154‧‧‧Second round table

16,26,36,46‧‧‧active layer

17,27,37,47‧‧‧Three-dimensional nanostructure array

18,28,38,48‧‧‧second semiconductor layer

452‧‧‧First round table space

454‧‧‧Second round table space

FIG. 1 is a schematic structural view of a light emitting diode according to a first embodiment of the present invention.

2 is a cross-sectional view of the light-emitting diode of FIG. 1 taken along line II-II.

3 is a scanning electron micrograph of a three-dimensional nanostructure array of a light-emitting diode according to a first embodiment of the present invention.

4 is a test result of light extraction efficiency of a light-emitting diode according to a first embodiment of the present invention.

FIG. 5 is a schematic structural diagram of a light emitting diode according to a second embodiment of the present invention.

FIG. 6 is a schematic structural diagram of a light emitting diode according to a third embodiment of the present invention.

FIG. 7 is a schematic structural diagram of a light emitting diode according to a fourth embodiment of the present invention.

Figure 8 is a cross-sectional view of the light-emitting diode of Figure 7 taken along line VIII-VIII.

In order to further illustrate the present invention, the following specific embodiments are taken in conjunction with the accompanying drawings. The detailed description is as follows.

Referring to FIG. 1 , a first embodiment of the present invention provides a light emitting diode 10 including a substrate 12 , a first semiconductor layer 14 , an active layer 16 , a second semiconductor layer 18 , and a first electrode 13 . a second electrode 11 and a three-dimensional nanostructure array 17.

The first semiconductor layer 14 , the active layer 16 , and the second semiconductor layer 18 are sequentially stacked on one side of the substrate 12 . The first electrode 13 is electrically connected to the first semiconductor layer 14. The second electrode 11 is electrically connected to the second semiconductor layer 18. The three-dimensional nanostructure array 17 may be disposed on a surface of the second semiconductor layer 18 away from the substrate 12, or/and a surface of the first semiconductor layer 14 in contact with the substrate 12, or/and the substrate 12 is in contact with the first semiconductor layer 14. The surface. In this embodiment, the three-dimensional nanostructure array 17 is disposed on a surface of the second semiconductor layer 18 away from the substrate 12.

The substrate 12 has a supporting role. The substrate 12 has a thickness of 300 to 500 micrometers and is made of sapphire, gallium arsenide, indium phosphide, lithium metaaluminate, lithium gallate, aluminum nitride, tantalum, tantalum carbide and tantalum nitride. One or a mixture thereof. In this embodiment, the substrate 12 has a thickness of 400 microns and the material is sapphire.

Alternatively, a buffer layer (not shown) may be disposed between the substrate 12 and the first semiconductor layer 14 and in contact with the substrate 12 and the first semiconductor layer 14, respectively, when the first semiconductor layer 14 is adjacent to the substrate 12. The surface is in contact with the buffer layer. The buffer layer is advantageous for improving the growth quality of the material and reducing the lattice mismatch. The buffer layer has a thickness of 10 nm to 300 nm, and the material thereof may be gallium nitride or aluminum nitride.

The first semiconductor layer 14 is a stepped structure. The first semiconductor layer 14 includes a first surface, a second surface, and a third surface. The three surfaces are parallel to each other. The second surface and the third surface are both disposed opposite to the first surface. The first semiconductor layer 14 The second surface has a different height than the third surface such that the first semiconductor layer 14 has a step. The second surface is the lower height surface of the step, and the third surface is the higher height surface of the step. The distance between the second surface and the first surface is smaller than the third surface. When the first semiconductor layer 14 is disposed on one side of the substrate 12, the first surface of the first semiconductor layer 14 is disposed adjacent to the substrate 12. The active layer 16 and the second semiconductor layer 18 are sequentially disposed on the third surface of the first semiconductor layer 14. Preferably, the contact area of the active layer 16 and the third surface of the first semiconductor layer 14 is equal to the area of the third surface of the first semiconductor layer 14. The second semiconductor layer 18 completely covers the surface of the active layer 16 remote from the substrate 12. Optionally, the third surface and the second surface of the first semiconductor layer 14 may be located at a plane, that is, the second surface and the third surface are the same height. At this time, the active layer 16 and the second semiconductor layer 18 are sequentially stacked. A portion of the surface of the first semiconductor layer 14 is disposed to form a stepped structure. The first electrode 13 is disposed on the second surface of the first semiconductor layer 14 .

The first semiconductor layer 14 and the second semiconductor layer 18 are respectively one of two types of an N-type semiconductor layer and a P-type semiconductor layer. Specifically, when the first semiconductor layer 14 is an N-type semiconductor layer, the second semiconductor layer 18 is a P-type semiconductor layer; when the first semiconductor layer 14 is a P-type semiconductor layer, the second semiconductor layer 18 is an N-type Semiconductor layer. The N-type semiconductor layer functions to provide electrons, and the P-type semiconductor layer functions to provide holes. The material of the N-type semiconductor layer is one of a material such as N-type gallium nitride, N-type gallium arsenide, and N-type copper phosphide or a mixture thereof. The material of the P-type semiconductor layer is one of a material such as P-type gallium nitride, P-type gallium arsenide, and P-type copper phosphide or a mixture thereof. The first semiconductor layer 14 has a thickness of 1 micrometer to 5 micrometers. The second semiconductor layer 18 has a thickness of 0.1 micrometer to 3 micrometers. In this embodiment, the first semiconductor layer 14 is an N-type semiconductor layer, and the distance between the first surface and the third surface of the first semiconductor layer 14 is 0.3 μm, and the distance between the first surface and the second surface is 0.1 μm. . First semiconductor layer 14 The material is N-type gallium nitride. The second semiconductor layer 18 is a P-type semiconductor layer, and the second semiconductor layer 18 has a thickness of 0.3 μm and the material is P-type gallium nitride.

The active layer 16 is disposed on the third surface of the first semiconductor layer 14. The active layer 16 is a quantum well structure comprising one or a plurality of quantum well layers. The active layer 16 is used to provide photons. The material of the active layer 16 is one of gallium nitride, indium gallium nitride, indium gallium aluminum nitride, arsenic oxide, aluminum arsenide, indium gallium phosphide, indium phosphide or indium gallium arsenide or The mixture has a thickness of from 0.01 micrometers to 0.6 micrometers. In this embodiment, the active layer 16 has a two-layer structure including an indium gallium nitride layer and a gallium nitride layer having a thickness of 0.03 μm. The distance between the second surface of the first semiconductor layer 14 and the surface of the second semiconductor layer 18 away from the substrate 12 is 0.8 micrometers.

The first electrode 13 and the second electrode 11 may be one of two types of an N-type electrode or a P-type electrode. The second electrode 11 is of the same type as the second semiconductor layer 18. The first electrode 13 is of the same type as the first semiconductor layer 14. The second electrode 11 and the first electrode 13 are at least one layer structure and have a thickness of 0.01 micrometer to 2 micrometers. The material of the first electrode 13 and the second electrode 11 includes one of titanium, aluminum, nickel and gold or any combination thereof. Preferably, the second electrode 11 is an N-type electrode, and the second electrode 11 has a two-layer structure including a titanium layer having a thickness of 150 angstroms and a gold layer having a thickness of 2000 angstroms. The first electrode 13 is a P-type electrode, and the first electrode 13 has a two-layer structure including a nickel layer having a thickness of 150 angstroms and a gold layer having a thickness of 1000 angstroms. In this embodiment, the first electrode 13 is disposed on the second surface of the first semiconductor layer 14, and the second electrode 11 is disposed on a portion of the surface of the second semiconductor layer 18 away from the substrate 12.

The three-dimensional nanostructure array 17 includes a plurality of three-dimensional nanostructures 15. The material of the three-dimensional nanostructure 15 or the material defining the three-dimensional nanostructure 15 may be the same as the material of the second semiconductor layer 18 to form a unitary structure, or a material of the second semiconductor layer 18. different. The plurality of three-dimensional nanostructures 15 are disposed in an array on the surface of the second semiconductor layer 18. The array form arrangement means that the plurality of three-dimensional nanostructures 15 can be arranged in an equidistant determinant arrangement, a concentric annular arrangement or a hexagonal dense arrangement. Moreover, the plurality of three-dimensional nanostructures 15 arranged in an array form a single pattern or a plurality of patterns. The single pattern may be a triangle, a parallelogram, a body, a diamond, a square, a rectangle, or a circle. The plurality of patterns may include a patterned array of a plurality of identical or different single patterns. The distance between the two adjacent three-dimensional nanostructures 15 is equal, that is, the distance between the adjacent two first circular tables 152 is equal, ranging from 10 nm to 1000 nm, preferably 10 nm to 30 Nano. In this embodiment, the plurality of three-dimensional nanostructures 15 are arranged in a hexagonal densely packed pattern to form a single square pattern, and the distance between two adjacent three-dimensional nanostructures 15 is about 30 nm.

The three-dimensional nanostructure 15 is a stepped structure. The three-dimensional nanostructure 15 may be a stepped convex structure or a stepped concave structure. The stepped protrusion structure is an entity of a stepped protrusion extending outward from the surface of the second semiconductor layer 18. The stepped recessed structure is a space in which a stepped recess formed in the second semiconductor layer 18 is recessed from the surface of the second semiconductor layer 18. The stepped protrusion structure or the stepped recess structure may be a plurality of layered structures, such as a plurality of layers of triangular prisms, a plurality of layers of quadrangular prisms, a plurality of layers of hexagonal prisms or a plurality of layers of circular tables. Preferably, the stepped protrusion structure or the stepped recess structure is a plurality of layered truncated cone structures. The fact that the stepped recessed structure is a plurality of layers of the truncated cone structure means that the space of the stepped recess is a plurality of truncated cone shapes. The maximum dimension of the stepped convex structure or the stepped concave structure is 1000 nm or less, that is, the length, the width and the height are less than or equal to 1000 nm. Preferably, the stepped protrusion structure or the stepped recess structure has a length, a width and a height ranging from 10 nm to 500 nm.

Referring to FIG. 2 and FIG. 3, in the embodiment, the three-dimensional nanostructure 15 is a double-layered truncated cone structure with a stepped protrusion. Specifically, the three-dimensional nanostructure 15 includes a first circular table 152 and a second circular table 154 disposed on the surface of the first circular table 152. The first circular stage 152 is disposed adjacent to the second semiconductor layer 18. The side of the first circular stage 152 is perpendicular to the surface of the second semiconductor layer 18. The side of the second circular table 154 is perpendicular to the lower face of the first circular table 152. The first circular table 152 and the second circular table 154 form a stepped convex structure, and the second circular table 154 is disposed within the range of the first circular table 152. Preferably, the first circular table 152 is disposed coaxially with the second circular table 154. The first circular table 152 and the second circular table 154 are integrally formed, that is, the second circular table 154 is a truncated cone structure extending from the top surface of the first circular table 152.

The diameter of the bottom surface of the first circular table 152 is larger than the diameter of the bottom surface of the second circular table 154. The bottom surface of the first truncated cone 152 has a diameter of 30 nm to 1000 nm and a height of 50 nm to 1000 nm. Preferably, the first circular table 152 has a bottom surface diameter of 50 nm to 200 nm and a height of 100 nm to 500 nm. The bottom surface of the second circular table 154 has a diameter of 10 nm to 500 nm and a height of 20 nm to 500 nm. Preferably, the second circular table 154 has a bottom surface diameter of 20 nm to 200 nm and a height of 100 nm to 300 nm. In this embodiment, the first circular table 152 is disposed coaxially with the second circular table 154. The bottom surface of the first truncated cone 152 has a diameter of 380 nm and a height of 105 nm. The bottom surface of the second truncated cone 154 has a diameter of 280 nm and a height of 55 nm.

It can be understood that the three-dimensional nanostructure 15 can further include a third circular table (not shown) disposed on the surface of the second circular table 154. Preferably, the third circular table is disposed coaxially with the first circular table 152 and the second circular table 154.

When the large-angle light emitted by the second semiconductor layer 18 encounters the three-dimensional nanostructure array 17 during the exit, the three-dimensional nanostructure array 17 is diffracted to change the exit angle of the photon. Thereby, the extraction of the large-angle light of the light-emitting diode 10 is realized, and the light extraction efficiency of the light-emitting diode 10 is improved. Since the three-dimensional nanostructure 15 of the three-dimensional nanostructure array 17 of the present invention has a stepped structure, which is equivalent to including at least two layers of a three-dimensional nanostructure or a two-layer photonic crystal structure, the light of the light-emitting diode 10 can be more effectively improved. Take out the efficiency. Referring to FIG. 4, the light extraction efficiency of the light-emitting diode 10 provided by the present invention is five times that of the light-emitting diode of the prior art in which the three-dimensional nanostructure array is not disposed.

Referring to FIG. 5 , a second embodiment of the present invention provides a light emitting diode 20 including a substrate 22 , a first semiconductor layer 24 , an active layer 26 , a second semiconductor layer 28 , and a first electrode 23 . a second electrode 21 and a three-dimensional nanostructure array 27. The structure of the light-emitting diode 20 in the second embodiment of the present invention is similar to that of the light-emitting diode 10 in the first embodiment, except that the three-dimensional nanostructure array 27 is disposed on the first semiconductor layer 24. The surface in contact with the substrate 22.

Referring to FIG. 6 , a third embodiment of the present invention provides a light emitting diode 30 including a substrate 32 , a first semiconductor layer 34 , an active layer 36 , a second semiconductor layer 38 , and a first electrode 33 . a second electrode 31 and a three-dimensional nanostructure array 37. The structure of the light-emitting diode 30 in the third embodiment of the present invention is similar to that of the light-emitting diode 10 in the first embodiment, except that the three-dimensional nanostructure array 37 is disposed on the substrate 32 and the first The surface of the semiconductor layer 34 contacts.

It can be understood that, in the second embodiment and the third embodiment of the present invention, the three-dimensional nanostructure arrays 37, 47 are respectively disposed on the surface of the first semiconductor layer 24 in contact with the substrate 22 or the substrate 32 is in contact with the first semiconductor layer 34. The surface, so when the large angle light encounters the three-dimensional nanostructure arrays 37, 47 during propagation to the substrates 22, 32, it will be reflected by the three-dimensional nanostructure arrays 37, 47 into small angle light. On the one hand, large angle light becomes a small angle The light can improve the light-emitting efficiency of the light-emitting diodes 20, 30. On the other hand, the large-angle light becomes a small-angle light to reduce the propagation path of the light inside the light-emitting diodes 20, 30, thereby reducing the light propagation process. Loss in the middle. When the buffer layer is disposed between the first semiconductor layers 24, 34 and the substrates 22, 32, the three-dimensional nanostructure arrays 37, 47 can be respectively disposed on the first semiconductor layer in the second embodiment and the third embodiment of the present invention. 24 a surface in contact with the buffer layer or a surface in contact with the buffer layer.

Referring to FIG. 7 and FIG. 8 , a fourth embodiment of the present invention provides a light emitting diode 40 including a substrate 42 , a first semiconductor layer 44 , an active layer 46 , a second semiconductor layer 48 , and a first An electrode 43, a second electrode 41 and a three-dimensional nanostructure array 47. The structure of the light-emitting diode 40 in the fourth embodiment of the present invention is similar to that of the light-emitting diode 10 in the first embodiment, except that the three-dimensional nanostructure array 47 includes a plurality of three-dimensional nanostructures 45. And the three-dimensional nanostructure 45 is a stepped recess structure, that is, a recessed space defined by the second semiconductor layer 48. The shape of the three-dimensional nanostructure 45 is a double-decked space, specifically including a first circular-shaped space 452, and a second circular-shaped space 454 communicating with the first circular-shaped space 452. The first truncated cone shaped space 452 is disposed coaxially with the second truncated cone shaped space 454. The first truncated cone shaped space 452 is disposed coaxially with the second truncated cone shaped space 454. The second frustum-shaped space 454 is disposed adjacent to the surface of the second semiconductor layer 48. The diameter of the second truncated space 454 is larger than the diameter of the first truncated space 452.

In summary, the present invention has indeed met the requirements of the invention patent, and has filed a patent application according to law. However, the above description is only a preferred embodiment of the present invention, and it is not possible to limit the scope of the patent application of the present invention. Equivalent modifications or variations made by those skilled in the art in light of the spirit of the invention are intended to be included within the scope of the following claims.

10‧‧‧Lighting diode

11‧‧‧second electrode

12‧‧‧Base

13‧‧‧First electrode

14‧‧‧First semiconductor layer

15‧‧‧Three-dimensional nanostructure

152‧‧‧First round table

154‧‧‧Second round table

16‧‧‧Active layer

17‧‧‧Three-dimensional nanostructure array

18‧‧‧Second semiconductor layer

Claims (14)

a light emitting diode comprising: a substrate; a first semiconductor layer, an active layer and a second semiconductor layer are sequentially stacked on one side of the substrate, and the first semiconductor layer is disposed adjacent to the substrate; The first electrode is electrically connected to the first semiconductor layer; a second electrode is electrically connected to the second semiconductor layer: wherein the plurality of three-dimensional nanostructures are further arranged in an array on the surface of the second semiconductor layer away from the substrate And the three-dimensional nanostructure is a stepped structure, each of the stepped structures includes a first circular table and a second circular table disposed on the surface of the first circular table, the side of the first circular table being perpendicular to a surface of the second semiconductor layer, a side of the second truncated cone being perpendicular to a bottom surface of the first truncated cone. The light-emitting diode according to claim 1, wherein the three-dimensional nanostructure is a stepped convex structure or a stepped concave structure provided on a surface of the second semiconductor layer. The light-emitting diode of claim 2, wherein the stepped protrusion structure or the stepped recess structure has a dimension of less than or equal to 1000 nm. The light-emitting diode of claim 1, wherein the three-dimensional nanostructure is a plurality of stepped truncated cone structures. The light-emitting diode of claim 4, wherein the first circular table is disposed adjacent to the second semiconductor layer, and a diameter of a bottom surface of the first circular table is larger than a diameter of a bottom surface of the second circular table. The light-emitting diode of claim 5, wherein the first circular table and the second circular table are coaxially disposed and form an integral structure. The light-emitting diode of claim 5, wherein the three-dimensional nanostructure further comprises a third truncated cone disposed on the surface of the second truncated cone. The illuminating diode of claim 1, wherein the plurality of three-dimensional nanostructures are disposed in the second semiconductor in an equidistant determinant arrangement, a concentric annular arrangement or a hexagonal dense arrangement. Layer surface. The light-emitting diode of claim 1, wherein the three-dimensional nanostructure forms a unitary structure with the second semiconductor layer. The light-emitting diode according to Item 1, wherein the distance between the adjacent two-dimensional three-dimensional nanostructures is from 10 nm to 1000 nm. The light-emitting diode of claim 1, further comprising a plurality of three-dimensional nanostructures disposed in an array on a surface of the first semiconductor layer in contact with the substrate. The light-emitting diode of claim 1, further comprising a plurality of three-dimensional nanostructures disposed in an array on a surface of the substrate in contact with the first semiconductor layer. The light-emitting diode of claim 1, wherein the plurality of three-dimensional nanostructures arranged in an array form a single pattern or a plurality of patterns. a light emitting diode comprising: a substrate; a first semiconductor layer, an active layer and a second semiconductor layer are sequentially stacked on one side of the substrate, and the first semiconductor layer is disposed adjacent to the substrate; The first electrode is electrically connected to the first semiconductor layer; a second electrode is electrically connected to the second semiconductor layer; and further comprising a plurality of three-dimensional nanostructures disposed in an array on the surface of the first semiconductor layer in contact with the substrate And the three-dimensional nanostructure is a stepped structure, each of the stepped structures includes a first circular table and a second circular table disposed on the surface of the first circular table, the side of the first circular table being perpendicular to a surface of the second semiconductor layer, a side of the second truncated cone being perpendicular to a bottom surface of the first truncated cone.