TWI425492B - Liquide crystal display device and data driver - Google Patents

Description

Liquid crystal display device and data driver

The present invention relates to a liquid crystal display device and a data driver for the liquid crystal display device.

The liquid crystal display device has been widely used in electronic devices such as televisions, notebook computers, mobile phones, and personal digital assistants because of its small size, light weight, thin thickness, low power consumption, no flicker, and low radiation.

The liquid crystal display device generally includes a liquid crystal display panel, a scan driver for driving the liquid crystal display panel for display, and a data driver. The data driver is mainly used to convert the data signals of the serial digits into grayscale voltages of parallel analogy, and provide the grayscale voltage to the liquid crystal display panel. The data driver includes a digital analog converter, and the digital analog converter further includes a plurality of conversion units, each conversion unit is configured to convert the digital data signal into a corresponding analog gray scale voltage.

Please refer to FIG. 1 , which is a schematic structural diagram of a conversion unit of a digital analog converter of a data driver in a prior art liquid crystal display device. The conversion unit 10 typically includes a resistor string 11 and a selector 12. The resistor string 11 is used to provide a resistor string 11 of various gray scale voltages. The selector 12 is configured to receive the plurality of gray scale voltages, and select, according to the data signals of each digit, the gray scale voltage corresponding to the data signals of the digits from the plurality of gray scale voltages received. The selector 12 includes a plurality of switch groups 13 that form a plurality of levels. Each level of the switch group 13 corresponds to one bit of the data signal bit D _x , wherein each switch of the switch group 13 of each level is controlled by the bit D _x of the corresponding data signal. When the conversion unit 10 is in operation, the resistor string 11 provides a plurality of gray scale voltages, and the digits D _x of the data signals of the digits control the conduction and the end of each switch in each level switch group 13 to be used for each digit. The gray scale voltage corresponding to the data signal is selected and output.

However, according to the conversion unit 10 architecture of one of the aforementioned digital analog converters, when the data signal is 6 bits, the resistor string 11 needs to be composed of 2 ⁶ = 64 resistors, and the number of switches required by the selector 12 is 64 + 32 + 16+8+4+2=126, if the number of output terminals of the data driver is 720, that is, the number of conversion units 10 of the digital analog converter of the data driver is 720, the digital analog converter in the data driver The number of resistors used is 720×64=46,080, and the number of switches is 720×126=90,720. Therefore, when the number of output terminals is large, the number of resistors and switches is very large, and the occupied area is also very large. Further, with the improvement of the color requirement of the display screen of the liquid crystal display device, the higher order 8-bits and 10 bit data driver can provide more order gray scale voltage, but this will cause the digital analog converter in the data driver. The required number of resistors and switches is significantly increased, and the area is significantly increased, which also leads to an increase in manufacturing cost of the liquid crystal display device and the data driver.

In order to solve the problem of the number of resistors and switches required for the data driver of the prior art liquid crystal display device, it is necessary to provide a liquid crystal display device and a data driver with a small number of switches.

A liquid crystal display device includes a liquid crystal display panel and a data driver. The data driver is configured to receive a digital data signal and apply an analog gray scale voltage to the liquid crystal display panel. The data driver includes a digital analog converter, wherein the digital analog converter includes at least one conversion unit, and the conversion unit is configured to convert the received digital signal into a corresponding analog gray scale voltage. The conversion unit includes a first selector, a second selector, and a processor, the first selector is configured to receive m gray scale voltages and select one of the gray scale voltages as a first voltage according to the data signals of the digits And outputting the first voltage to the processor, the second selector is configured to receive n gray scale voltages and select one of the gray scale voltages as a second voltage according to the data signals of the digits, and output the second voltage to The processor, wherein m and n are natural numbers. The processor is configured to generate an analog grayscale voltage corresponding to the data signal of the digit according to the first voltage and the second voltage.

A data driver that includes a digital analog converter. The digital analog converter is configured to receive a digital data signal and output an analog gray scale voltage. The digital analog converter includes at least one conversion unit for converting the received digital signal into a corresponding analog gray scale voltage. The conversion unit includes at least two selectors and a processor. For any of the selectors, the selector receives a plurality of gray scale voltages, and selects a voltage from the plurality of gray scale voltages received according to the data signals of the digits. Provided to the processor. The processor generates an analog grayscale voltage corresponding to the data signal of the digit according to the voltage provided by the at least two selectors.

Compared with the prior art, in the liquid crystal display device and the data driver of the present invention, since the first voltage has m kinds, and the second voltage has n kinds, the processor can process the first voltage and the second voltage. The gray scale voltage of the m×n type is generated. Therefore, the liquid crystal display device and the data driver of the present invention can select two smaller digit selectors (the first selector and the second selector) for generating higher bits. The number selector can produce an analogous number of gray scale voltages. Since the total number of switches of the two smaller number of selectors is typically less than the total number of switches of the selector having a higher number of bits than the first and second selectors, the number of total switches used by the digital analog converter is less. .

The preferred embodiments of the present invention are described in detail below with reference to the accompanying drawings.

Please refer to FIG. 2 , which is a schematic structural view of a liquid crystal display device according to a preferred embodiment of the present invention.

The liquid crystal display device 100 includes a liquid crystal display panel 120, a driving circuit 110 for driving the liquid crystal display panel 120, and a power supply circuit 150 for supplying operating power to the driving circuit 110.

The driving circuit 110 includes a timing controller 112, a scan driver 116, and a data driver 114. The timing controller 112 is configured to receive image data, and generate a timing signal and a digital data signal according to the image data, and provide the timing signal to the data driver 114 and the scan driver 116 to control the working timing, and the digital position The data signal is provided to the data driver 114. The scan driver 116 receives the timing signal and sequentially outputs a series of scan pulses to the liquid crystal display panel 120. The data driver 114 receives the data signals and timing signals of the digits to generate a plurality of analog gray scale voltages, and applies the plurality of analog gray scale voltages to the liquid crystal display panel 120.

The liquid crystal display panel 120 includes a plurality of mutually parallel scan lines 124, a plurality of data lines 122 that are parallel to each other and vertically insulated from the scan lines 124, and a plurality of lines defined by the intersection of the plurality of scan lines 124 and the data lines 122. Prime 126. The plurality of scan lines 124 are configured to receive a series of scan pulses output by the scan driver 116. The plurality of data lines 122 are configured to receive a plurality of analog gray scale voltages output by the data driver 114, and apply a plurality of analog gray scale voltages to the plurality of data lines 122 under the control of the series of scan pulses. To the plural pixels 126.

Please refer to FIG. 3 together. FIG. 3 is a schematic structural diagram of a data driver of the liquid crystal display device shown in FIG. The data driver 114 includes a data receiver 130, a shift register 131, a line latch 133, a level shifter 135, a digital analog converter 137, and an output register 139.

The data receiver 130 is configured to receive the digital signal output by the timing controller 112. The digital signal of the digital signal is a series of digital signals including R Data, G Data and B Data.

The shift register 131 receives the timing signal output by the timing controller 112, and latches the data signal of the serial number received by the data receiver 130 bit by bit to the line lock under the control of the timing signal. A parallel digital signal is formed in the memory 133.

The line latch 133 latches the data signal of the digit corresponding to the pixel 126 on the scan line 124 (hereinafter referred to as the line data signal, that is, the data signal of the parallel digit formed by the shift register 131). And providing the line data signal to the level shifter 135. The data signal of each line includes a plurality of digital data signals, and the data signals of the plurality of digits are output in parallel, and the data signals of each digit correspond to one pixel 126 on one scan line 124.

The level shifter 135 is configured to perform level conversion on the data signal of each digit of the line data signal, specifically, converting the input data signal of the lower level into a higher level digital signal. The data signal is output to the digital analog converter 137 in parallel with the converted digital signal. In another variant embodiment of the data driver 114 of the present invention, the data driver 114 may not include the level shifter 135, and the line latch 133 may provide the line data signal directly to the digital analog converter 137.

The digital analog converter 137 is configured to convert the received data signal of each digit into a corresponding gray scale voltage, and the plurality of analog gray scale voltages corresponding to the plurality of digital data signals of the line data signal The output is parallel to the output register 139. The digital analog converter 137 includes a plurality of conversion units 1371. Each of the conversion units 1371 corresponds to receiving and processing a data signal of one digit of the line data signal, that is, converting the data signal of the digit to a corresponding analog gray scale voltage.

The output register 139 is configured to apply a plurality of analog gray scale voltages corresponding to the line data signals to the plurality of data lines 122 of the liquid crystal display panel 120. The output register 139 includes a plurality of output terminals 1391 connected to the plurality of data lines 122, respectively.

Please refer to FIG. 4, which is a schematic structural diagram of an embodiment of a conversion unit 1371 of a digital analog converter 137 of the data driver 114 shown in FIG. The conversion unit 1371 includes a voltage providing device 140, a first selector 144, a second selector 164, and a processor 170.

The voltage providing device 140 is configured to provide the first selector 144 with a plurality of (set to m) gray scale voltages and a plurality of (set to n) gray scale voltages for the second selector 164. In the embodiment, the voltage providing device 140 is integrated in the converting unit 1371. However, in other modified embodiments, the voltage providing device 140 may be disposed in the power circuit 150 or other circuits. m and n are natural numbers and are usually greater than or equal to two.

The voltage providing device 140 includes a first resistor string 142 and a second resistor string 162. Specifically, in the embodiment, the first resistor string 142 is configured to provide the first selector 144 with the m gray scale voltages, and the second resistor string 162 is configured to provide the second selector 164 with the n kinds of gray scale voltages.

The first selector 144 is configured to receive the m gray scale voltages and select one of the m gray scale voltages as a first voltage according to the data signals of the digits, and output the first voltage to the processing. 170. The first selector 144 can be a multiplexer. Specifically, the first selector 144 can control the k-bits of the data signals of the digits (assuming that the data signals of the digits are s bits) The first voltage is outputted below. The second selector 164 is configured to receive the n gray scale voltages, and select one of the n gray scale voltages as a second voltage according to the data signals of the digits, and output the second voltage to the Processor 170. The second selector 164 can also be a multiplexer. Specifically, the second selector 164 can output the second voltage under the control of the data signal (s-k) bits of the digit.

Specifically, the range of values of m and n can be set as needed, preferably, m ≧ 2 ^k ; n ≧ 2 ^(sk) , where 0 < k < s, and s and k are natural numbers. Generally, the value of s can be: 2≦s≦10, preferably s=6 or s=8 or s=10.

The processor 170 is configured to generate an analog grayscale voltage corresponding to the data signal of the digit according to the first voltage and the second voltage. Specifically, the processor 170 first performs scaling processing on the first voltage and the second voltage, and then adds or subtracts the scaled first voltage and the second voltage to generate the data signal of the digit. Corresponding to the analog gray scale voltage, the voltage V _out output by the processor 170 is expressed as V _out = aV _msb + bV _lsb . Where V _msb represents the first voltage, V _lsb represents the second voltage, and a and b are scaling factors.

In one embodiment, the processor 170 includes an adder that first scales the first voltage and the second voltage, and then adds the scaled first voltage and the second voltage to Generates an analog grayscale voltage corresponding to the data signal of the digit. Since the first voltage has m kinds and the second voltage has n kinds, the processor 170 can generate m×n gray scales by performing scaling processing on the first voltage and the second voltage. Voltage.

Specifically, in this embodiment, the adder of the processor 170 can include a first resistor 171, a second resistor 173, a third resistor 175, a fourth resistor 177, and an operational amplifier 179. The first resistor 171 is electrically connected to the positive input end of the operational amplifier 179 , and the other end is electrically connected to the output end of the first selector 144 as a first input end of the processor 170 . The second resistor 173 is electrically connected to the positive input end of the operational amplifier 179 , and the other end is electrically connected to the output end of the second selector 164 as a second input end of the processor 170 . The third resistor 175 is electrically connected to the negative input terminal of the operational amplifier 179, and the other end is electrically connected to the output terminal of the operational amplifier 179. One end of the fourth resistor 177 is electrically connected to the negative input terminal of the operational amplifier 179, and the other end is grounded. Therefore in accordance with the circuit configuration of the processor 170, the computing equation can infer the processor 170 of the output voltage V _out:

Wherein, V _msb represents the first voltage, V _lsb represents the second voltage, R1 represents the first resistor 171, R2 represents the second resistor 173, R3 represents the third resistor 175, and R4 represents the fourth resistor 177.

When R1 = R2 and R3 = R4, that is, when a and b are equal to 1, the output voltage of the processor 170 is V _out = V _msb + V _lsb . Of course, in other modified embodiments, the condition of R1=R2 and R3=R4 may not be set, then V _out may be expressed as V _out =aV _msb +bV _lsb , where a and b are scaling factors, and the a The value of b is related to R1, R2, R3, and R4, and the values of R1, R2, R3, and R4 can be set according to actual needs.

In another embodiment, the processor 170 includes a subtractor that performs a subtraction process on the first voltage and the second voltage to generate an analog grayscale voltage corresponding to the data signal of the digit. Since the first voltage has m kinds and the second voltage has n kinds, the processor 170 can generate m×n gray scale voltages by subtracting the first voltage and the second voltage.

Specifically, please refer to FIG. 5 , which is a schematic structural diagram of a conversion unit 1371 of the digital analog converter 137 of the data driver 114 shown in FIG. 3 . The processor 170 includes a first resistor 181, a second resistor 183, a third resistor 185, a fourth resistor 187, and an operational amplifier 189. The first resistor 181 is electrically connected to the positive input end of the operational amplifier 189 , and the other end is electrically connected to the output end of the first selector 144 as a first input end of the processor 170 . One end of the second resistor 183 is electrically connected to the positive input end of the operational amplifier 189, and the other end is grounded. The third resistor 185 has one end connected to the negative input terminal of the operational amplifier 189 and the other end connected to the output terminal of the operational amplifier 189. The fourth resistor 187 is electrically connected to the negative input terminal of the operational amplifier 189 , and the other end is electrically connected to the output terminal of the second selector 164 as a second input end of the processor 170 . Therefore in accordance with the circuit configuration of the processor 170, the computing equation can infer the processor 170 of the output voltage V _out:

Wherein, V _msb represents the first voltage, V _lsb represents the second voltage, R1 represents the first resistor 181, R2 represents the second resistor 183, R3 represents the third resistor 185, and R4 represents the fourth resistor 187.

When R1=R2 and R3=R4, that is, when a and b are equal to 1, the output voltage of the processor 170 is V _out = V _msb - V _lsb . Of course, in other modified embodiments, the condition of R1=R2 and R3=R4 may not be set, and V _out may be expressed as V _out =aV _msb -bV _lsb , where a and b are scaling multiples, and The values of a and b are related to R1, R2, R3, and R4, and the values of R1, R2, R3, and R4 can be set according to actual needs.

Therefore, in the data driver 114, since the first voltage has m kinds, and the second voltage has n kinds, the processor 170 can generate the m×n type ratio gray by processing the first voltage and the second voltage. Order voltage.

Therefore, the two smaller number of selectors (the first selector 144 and the second selector 164) can be selected in the liquid crystal display device 100 and the data driver 114 for generating the analog gray scale voltage that the higher order selector 12 can generate. number. Since the total number of switches of the selectors of the two smaller digits is usually smaller than the total number of switches of the selector 12 having a higher number of digits than the first selector 144 and the second selector 164, the liquid crystal display device 100 and the data The number of total switches used by the digital analog converter 137 in the driver 114 is small. The reduction in the total number of switches can contribute to the reduction of the area of the data driver 114 and the reduction of the manufacturing cost, and can also meet the need for higher-order 8-bits, 10-bit data drivers as the color requirements of the display screen of the liquid crystal display device increase. Claim.

Further, in the liquid crystal display device 100 and the data driver 114 of the present invention, a first resistor string 142 and a second resistor string 162 for providing a plurality of gray scale voltages may be selected, and the first resistor string 142 is used for the first selection. The 144 provides m gray scale voltages, and the second resistor string 162 is used to provide the second selector 164 with n gray scale voltages. Since the number of total resistances required for the first resistor string 142 and the second resistor string 162 that provide less gray scale voltage is m+n, the prior art provides a single resistor string 11 for a plurality of gray scale voltages. The total number of resistors is m x n, and m x n is usually much larger than m + n. Therefore, the number of total resistances used by the digital analog converter 137 in the liquid crystal display device 100 and the data driver 114 is small.

The technical effects of the foregoing embodiments are exemplified below.

As stated in the background section, the number of resistors required by prior art digital analog converters is 720 x 64 = 46,080 and the number of switches is 720 x 126 = 90,720, only when using 6 bit data signals. However, if a higher order 8 bits or even a 10 bit data signal is used, the number of resistors and the number of switches required for the digital analog converter is much larger than the number of resistors and the number of switches required for the digital analog converter using the 6 bit data signal.

In contrast, in the data driver 114 of the embodiment, when the data signal of 10 bits is used, the present invention divides the 10 bit data signal into a high 5 bit data signal (D ₉ D ₈ D ₇ D ₆ D ₅ ) and a low ₅ bit data signal ( D ₄ D ₃ D ₂ D ₁ D ₀ ), the high 5 bit data signal and the low 5 bit data signal respectively control the first selector 144 and the second selector 164, since the first selector 144 is one m selected The multiplexer and the second selector 164 are a single multiplexer, so m and n are both equal to 32. At this time, the first resistor string 142 provides 32 gray scale voltages, the second resistor string 162 also provides 32 gray scale voltages, and the first selector 144 receives 32 gray scale voltages provided by the first resistor string 142. And selecting one of the gray scale voltages as a first voltage output to the processor 170 according to the high 5bits data signal. The second selector 164 receives the 32 gray scale voltages provided by the second resistor string 162, and selects one of the gray scale voltages as a second voltage output to the processor 170 according to the low 5 bit data signal. The processor 170 can generate 32×32=1024 gray scale voltages by adding or subtracting the first voltage and the second voltage. Therefore, by using the foregoing method, the number of resistances required by the conversion unit 1371 is 32 × 2 + 4 = 68, and the number of switches is (32 + 16 + 8 + 4 + 2) × 2 = 124. Since the digital analog converter 137 includes at least one of the conversion units 1371, if the number of output terminals of the data driver 114 is 720, the number of conversion units 1371 of the digital analog converter 137 is also 720, that is, the digital analog conversion The number of resistors included in the 137 is 720 x 68 = 48960, and the number of switches is 720 x 124 = 89280.

By comparison, it is found that the number of resistors and switches required for the data driver 114 of the present embodiment for the data signal of the digits of 10 bits is the number of resistors and switches required by the data driver of the prior art for the data signal of the digits of 6 bits. Quite, and much smaller than the number of resistors and switches required by the data driver of the prior art using 10 bits of data signals.

However, the present invention is not limited to the foregoing embodiment. Please refer to FIG. 6, which is a schematic structural diagram of a conversion unit 1371 of a digital analog converter 137 of a data driver 114 shown in FIG. The main difference between the present embodiment and the foregoing preferred embodiment is that the voltage supply device 240 can further include only one resistor string 242, and the resistor string 242 can respectively provide the m gray scale voltages and the n gray scale voltages, specifically The resistor string 242 supplies the m gray scale voltages to the first selector 144 and provides the n gray scale voltages to the second selector 164.

Compared with the foregoing preferred embodiment, only one resistor string 242 is used in the embodiment to provide the m selector gray voltages for the first selector 144 and the n gray scale voltages for the second selector 164. . Therefore, by using the present embodiment, the total number of resistors used by the digital analog converter 137 in the liquid crystal display device 100 and the data driver 114 is further reduced.

Further, the present invention is not limited to the foregoing embodiments. In other modified embodiments, the conversion unit 1371 is not limited to include two selectors, and the conversion unit 1371 includes at least two selectors, for example, the conversion unit 1371. Y selectors can be included.

Specifically, the Y selectors, the selectors receiving the i m _i species gray scale voltage, and selects a grayscale voltage from the received gray levels of m _i based on the voltages of the digital data signals as the first The i selectors select the voltage V _i . The processor 170 of the selection of Y from the selected voltage V V _Y scaling processing were performed after ₁ ~ addition or subtraction processing to generate data signals corresponding to the number of bits of the analog gray scale voltage, so that the The voltage V _out output by the processor 170 can be expressed as V _out = a ₁ V ₁ + a ₂ V ₂ ... + a _i V _i ... + a _Y V _Y , where 2 ≦ Y, 1 ≦ i ≦ Y, | a ₁ |, |a ₂ |...|a _i |...|a _Y | is the zoom factor.

The voltage providing device 240 can provide the m _i gray scale voltages for the i th selector of the Y selectors.

A gray scale voltage to the output by the i-th selector selects lines in the data of the digital signal of which the voltage of the K _i m gray levels from the next received control bits of a _i as the voltage V _i the processor 170, so that the range of the m _i is be ≧ m _i 2 ^ki, wherein the data signals may be x bits, and _{k 1 + k 2 ... + k} i ... + k Y ≧ x, x and k _i is a natural number.

Since the voltage V _i selected by the _ith selector has m _i , the processor 170 performs scaling or subtraction on the voltages V ₁ VV _Y selected by the Y selectors respectively. The process can produce gray scale voltages of m ₁ × m ₂ ... × m _i ... × m _Y .

For example, when the data signal of 12 bits is used, preferably, in other modified embodiments, the conversion unit 1371 may include two 6-bit control selectors, and may also include three 4-bit control selectors. It can include four 3bits controlled selectors. The following description will be made by taking a selector including three 4-bits control in the conversion unit 1371 as an example.

Please refer to FIG. 7 , which is a schematic structural diagram of a conversion unit 1371 of a digital analog converter 137 of another modified embodiment of the data driver 114 shown in FIG. 3 . The conversion unit 1371 includes a voltage providing device 240, a first selector 144, a second selector 164, a third selector 166, and a processor 170. The main difference between this embodiment and the foregoing preferred embodiment is that the present embodiment uses three 4-bits controlled selectors, namely, a first selector 144, a second selector 164 and a third selector 166. Specifically, the first selector 144 selects one of the 16 gray scale voltages as one of the 16 gray scale voltages received under the control of 4 bits (D ₁₁ D ₁₀ D ₉ D ₈ ) of the 12-bit data signal. The voltage V _{1 is} output to the processor 170, and the second selector 164 is selected from the received 16 gray scale voltages under the control of 4 bits (D ₇ D ₆ D ₅ D ₄ ) of the 12-bit data signal. One of the gray scale voltages is output to the processor 170 as a voltage V ₂ , and the third selector 166 receives the received data under the control of 4 bits (D ₃ D ₂ D ₁ D ₀ ) of the _{12- bit} data signal. One of the 16 gray scale voltages is selected as a voltage V3 to be output to the processor 170.

Compared with the foregoing preferred embodiment, in the case of using 12 bits of the data signal, the preferred embodiment will use two 6-bits controlled selectors. In contrast, this embodiment uses three 4-bits controlled selectors. Since the number of switches required by the three 4-bit control selectors is much smaller than the number of switches required by the two 6-bit control selectors, the liquid crystal display device 100 and the data driver 114 of the present invention are used in the present embodiment. The number of switches used by the digital analog converter 137 is further reduced.

10, 1371‧‧‧ conversion unit

11, 242‧‧‧resistance string

12‧‧‧Selector

13‧‧‧ switch group

100‧‧‧Liquid crystal display device

150‧‧‧Power circuit

120‧‧‧LCD panel

114‧‧‧Data Drive

124‧‧‧ scan line

122‧‧‧Information line

126‧‧ ‧ pixels

130‧‧‧ data receiver

131‧‧‧Shift register

133‧‧‧Line latch

137‧‧‧Digital Analog Converter

139‧‧‧Output register

1391‧‧‧ Output

142‧‧‧First resistor string

162‧‧‧second resistor string

144‧‧‧First selector

164‧‧‧Second selector

170‧‧‧ processor

171,181‧‧‧First resistance

173, 183‧‧‧ second resistor

175, 185‧‧‧ third resistor

177, 187‧‧‧ fourth resistor

179, 189‧‧‧Operational Amplifier

140, 240‧‧‧ voltage supply device

166‧‧‧ third selector

1 is a schematic structural diagram of a conversion unit of a digital analog converter of a data driver in a prior art liquid crystal display device.

2 is a schematic structural view of a preferred embodiment of a liquid crystal display device of the present invention.

3 is a schematic structural view of a data driver of the liquid crystal display device shown in FIG. 2.

FIG. 4 is a schematic structural diagram of a conversion unit of a digital analog converter of an embodiment of the data driver shown in FIG.

FIG. 5 is a schematic structural diagram of a conversion unit of a digital analog converter according to another embodiment of the data driver shown in FIG.

FIG. 6 is a schematic structural diagram of a conversion unit of a digital analog converter according to a modified embodiment of the data driver shown in FIG. 3. FIG.

FIG. 7 is a schematic structural diagram of a conversion unit of one of the digital analog converters of another modified embodiment of the data driver shown in FIG.

1371‧‧‧Conversion unit

140‧‧‧Voltage supply device

142‧‧‧First resistor string

162‧‧‧second resistor string

144‧‧‧First selector

164‧‧‧Second selector

170‧‧‧ processor

171‧‧‧First resistance

173‧‧‧second resistance

175‧‧‧ third resistor

177‧‧‧fourth resistor

179‧‧‧Operational Amplifier

Claims (22)

A liquid crystal display device comprising a liquid crystal display panel and a data driver, the data driver for receiving a digital data signal and applying an analog gray scale voltage to the liquid crystal display panel, the data driver comprising a digital analog converter, wherein the data bit The analog converter includes at least one conversion unit, and the conversion unit is configured to convert the received data signal into a corresponding analog gray scale voltage, wherein the conversion unit includes a first selector, a second selector, and a processor. The first selector is configured to receive m gray scale voltages and select one of the gray scale voltages as a first voltage according to the data signals of the digits, and output the first voltage to the processor, the second selector is configured to receive n kinds of gray scale voltages and selecting one of the gray scale voltages as a second voltage according to the data signals of the digits, and outputting the second voltage to the processor, wherein m and n are natural numbers, and the processor is configured according to the The first voltage and the second voltage generate an analog gray scale voltage corresponding to the data signal of the digit. The liquid crystal display device of claim 1, wherein the processor performs a scaling process on the first voltage and the second voltage, and then performs addition or subtraction processing to generate a digital signal corresponding to the digit. Analogous to the gray scale voltage, the voltage V _{out of} the processor output is expressed as V _out = aV _msb + bV _lsb , where V _msb represents the first voltage, V _lsb represents the second voltage, and |a| and |b| Zoom factor. The liquid crystal display device of claim 2, wherein the processor comprises an adder, the adder performs scaling processing on the first voltage and the second voltage, and then performs addition processing to generate the digital data. The signal corresponds to the analog grayscale voltage. The liquid crystal display device of claim 3, wherein the adder comprises a first resistor, a second resistor, a third resistor, a fourth resistor and an operational amplifier, the first resistor is electrically terminated The first input end of the processor is electrically connected to the output end of the first selector, and the other end is electrically connected to the positive input end of the operational amplifier. The other end is electrically connected to the output end of the second selector, and the other end of the third resistor is electrically connected to the negative input end of the operational amplifier, and the other end is electrically connected to the output of the operational amplifier. The fourth resistor is electrically connected to the negative input terminal of the operational amplifier and the other end is grounded. The liquid crystal display device of claim 2, wherein the processor comprises a subtractor, the subtractor processes the first voltage and the second voltage, and then performs a subtraction process to generate the digital data. The signal corresponds to the analog grayscale voltage. The liquid crystal display device of claim 5, wherein the subtractor comprises a first resistor, a second resistor, a third resistor, a fourth resistor and an operational amplifier, the first resistor is electrically terminated The first input end of the processor is electrically connected to the output end of the first selector, and the other end of the second resistor is electrically connected to the positive input end of the operational amplifier. The other end is connected to the negative input terminal of the operational amplifier, and the other end is connected to the output end of the operational amplifier. The fourth resistor is electrically connected to the negative input end of the operational amplifier, and the other end is used as the The second input of the processor is electrically connected to the output of the second selector. The liquid crystal display device of claim 1, wherein the conversion unit comprises a voltage supply device, the voltage supply device is configured to provide the m types of gray scale voltages for the first selector and for the second selection The n gray scale voltages are provided. The liquid crystal display device of claim 7, wherein the voltage supply device comprises a first resistor string and a second resistor string, wherein the first resistor string is used to provide the m type for the first selector a gray scale voltage, the second resistor string is used to provide the n selectors with the n gray scale voltages. The liquid crystal display device of claim 7, wherein the voltage supply device comprises a resistor string, the resistor string provides the m types of gray scale voltages for the first selector and provides the second selector n kinds of gray scale voltages. The liquid crystal display device of claim 1, wherein the digital data signal has s bits, and the first selector is under the control of k bits of the digital data signal. Selecting one of the m gray scale voltages as the first voltage output to the processor, and the second selector is from the n gray scales under the control of the data signal of the digits and the other sk bits One of the voltages is selected as the second voltage output to the processor, where 0 < k < s, and s and k are natural numbers. The liquid crystal display device of claim 10, wherein the values of m and n are respectively: m ≧ 2 ^k ; n ≧ 2 ^(sk) . The liquid crystal display device of claim 1, wherein the data driver further comprises a data receiver, a shift register, a line latch and an output register, the data receiver is configured to receive a data signal of a serial number, the shift register is used for latching the data signal of the serialized digit received by the data receiver bit by bit into the line latch to form a parallel digital signal signal. The line latch supplies the parallel digital data signal to the digital analog converter, the digital analog converter includes a plurality of conversion units, and the plurality of conversion units convert the parallel digital information signals into a plurality of analogies The gray scale voltage is supplied to the output register, and the output register is used to apply the plurality of analog gray scale voltages to the liquid crystal display panel. The liquid crystal display device of claim 12, wherein the data driver further comprises a level shifter for level-shifting the digital signal outputted by the line latch. The converted digital signal is output to the digital analog converter in parallel. The liquid crystal display device of claim 1, wherein the liquid crystal display device further comprises a timing controller and a scan driver, and the timing controller generates the timing signal and the data signal of the digit according to the received image data. And providing a timing signal to the data driver and the scan driver to control the working timing, and providing the data signal of the digit to the data driver, the scan driver receiving the timing signal and sequentially outputting a series of scan pulses to the liquid crystal display panel. The liquid crystal display device of claim 1, wherein the liquid crystal display device comprises a liquid crystal display panel comprising a plurality of scanning lines parallel to each other, a plurality of parallel lines and vertically insulated from the scanning lines An intersecting data line and a plurality of pixels defined by the intersection of the scan line and the data line, wherein the plurality of scan lines are used to receive a series of scan pulses of the scan driver output, and the plurality of data lines are used to receive the data driver output The plurality of analog gray scale voltages, and under the control of the series of scan pulses, apply a plurality of analog gray scale voltages to the plurality of pixels respectively. A data driver comprising a digital analog converter for receiving a digital data signal and outputting an analog gray scale voltage, the digital analog converter comprising at least one conversion unit, the conversion unit is configured to receive The digitized data signal is converted into a corresponding analog gray scale voltage, wherein the conversion unit includes at least two selectors and a processor, and for any one of the selectors, the selector receives a plurality of gray scale voltages, and according to The data signal of the digit is selected from the plurality of gray scale voltages received to the processor, and the processor generates an analog gray scale voltage corresponding to the data signal of the digit according to the voltage provided by the at least two selectors. The data driver of claim 16, wherein the number of the at least two selectors is Y, wherein the i-th selector receives m _i gray scale voltages, and receives the data signals according to the digits. m _i species after selecting a gray-scale voltage selected by the gray scale voltage as the selection of the i th voltage V _i, the processor is selected from the Y selectors of the voltages V V _Y scaling processing were ₁ Then, adding or subtracting processing is performed to generate an analog gray scale voltage corresponding to the data signal of the digit, and the voltage V _{out of} the processor output is expressed as V _out = a ₁ V ₁ + a ₂ V ₂ ... + a _i V _i ...+a _Y V _Y , where 2≦Y,1≦i≦Y,|a ₁ |, |a ₂ |...|a _i |...|a _Y | is a scaling factor. The data driver according to claim 17, wherein the processor includes an adder that performs scaling processing on the voltages V ₁ to V _Y selected from the Y selectors, respectively. The addition process is performed to generate an analog gray scale voltage corresponding to the data signal of the digit. The data driver of claim 17, wherein the processor includes a subtractor that scales the voltages V ₁ to V _Y selected from the Y selectors and then performs subtraction. Processing to generate an analogous grayscale voltage corresponding to the data signal of the digit. The data driver of claim 17, wherein the data signal of the digit has x bits, and the i-th selector is controlled by k _i bits in the data signal of the digit the select m gray levels _i where a voltage in the gray scale voltage as an output voltage V _i to the processor, _{wherein, k 1 + k 2 ... +} k i ... + k Y ≧ x, and x _i and K is Natural number. The data driver according to claim 20, wherein the value of the m _i is: m _i ≧ 2 ^ki . The data driver of claim 17, wherein the conversion unit comprises a voltage supply device for providing the m _i gray scales for the i th selector of the Y selectors Voltage.