TWI424505B - Method for forming the tft panel - Google Patents

Description

Method for manufacturing thin film transistor substrate

The present invention relates to a method of fabricating a Thin Film Transistor (TFT) substrate.

Low temperature poly-Si TFTs (LTPS-TFTs) can be used to make peripheral driving on glass substrates in addition to pixel control switching elements of active matrix liquid crystal display (AMLCD). Peripheral driving circuits. Therefore, the current-voltage characteristics of low-temperature polysilicon thin film transistors are very important. They must have a large driving current, a large carrier mobility, and a sub-threshold. Swing) Small and small leakage current characteristics. The simultaneous application of the n-type TFT and the p-type TFT forms a complementary MOS transistor, which can be widely applied to a peripheral driving circuit of a liquid crystal display substrate or an organic light emitting display (OLED) substrate, and can also be applied to organic A pixel control switching element of the light-emitting display substrate.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a partial schematic view of a prior art thin film transistor substrate. The thin film transistor substrate 1 includes an n-type TFT 55, first and second storage capacitors (not shown) adjacent to the n-type TFT 55, and a P-type TFT 66. The thin film transistor substrate 1 includes a substrate 11 , a buffer layer 12 disposed on the substrate 11 , a polysilicon film 14 , a gate insulating film 15 , and four metal lines 16 spaced apart from each other, and a dielectric layer 17 . A flat layer 19 and an Indium-TinOxide (ITO) film 199. Wherein the thin film transistor shown in Figure 1 The metal wires 16 at the two ends of the substrate 1 are the gate metal wires of the n-type TFT 55 and the p-type TFT 66, respectively, and the middle two metal wires 16 are the electrodes of the first and second storage capacitors. The thin film transistor substrate 1 further includes four electrodes 181, 182, 183, and 184 whose one end is connected to the polysilicon film 14 and whose other end is disposed on the surface of the dielectric layer 17, and the four electrodes 181, 182, 183, and 184 are respectively n. The source TFT and the drain of the p-type TFT 66, wherein the n-type TFT drain 182 and the p-type TFT source 183 are connected to the indium tin oxide film 199. The polysilicon film 14 includes an n-type TFT contact region 141, first and second storage capacitor contact regions 142, 143, and a P-type TFT contact region 144. The n-type TFT contact region 141 includes a source contact region 145, a via 146, and a drain contact region 147. The p-type TFT contact region 144 includes a source contact region 148, a via 149, and a drain contact region 140.

2 to 16 are flowcharts showing a method of manufacturing the thin film transistor substrate 1 shown in Fig. 1. The specific steps of the method for fabricating the thin film transistor substrate 1 are as follows: Step S101: The buffer layer 12 and the amorphous germanium film 13 are sequentially formed on the substrate 11, as shown in FIG.

Step S102: An amorphous germanium film 13 is melted and crystallized by excimer laser annealing to form a polycrystalline germanium film 14, as shown in FIG.

Step S103: forming an active layer, that is, an AS island pattern.

Applying a photoresist to the surface of the polysilicon film 14, aligning the polysilicon film 14 with a first mask, irradiating the first mask with ultraviolet rays in parallel, and developing the polysilicon film 14 to form an active layer pattern, that is, a pattern of a polysilicon film 14 including an n-type TFT contact region 141, first, The second storage capacitor contact regions 142, 143 and the p-type TFT contact region 144 are as shown in FIG.

Step S104: The source contact region 145 of the n-type TFT is heavily doped with the drain contact region drain contact region 147 and the first storage capacitor contact region 142. A photoresist is coated on the surface of the patterned polysilicon film 14, and a second mask is used to irradiate and develop the photoresist to expose the p-type TFT contact region 144, the region of the second storage capacitor contact region 143, and the n-type TFT. The channel 146 is occluded, and the source contact region 145 in the n-type TFT contact region 141 is heavily doped with the drain contact region 147 and the first storage capacitor contact region 142 using ion implantation, as shown in FIG.

Step S105: The source contact region 148 of the p-type TFT is heavily doped with the drain contact region 140 and the second storage capacitor contact region 143.

Etching the residual photoresist of the upper step, and recoating the photoresist on the pattern surface of the polysilicon film 14, the third mask, the photoresist resisting and developing the photoresist, and the contact region 141 of the n-type TFT and the first storage capacitor contact region The region of 142 and the channel 149 of the p-type TFT are shielded, and the source contact region 148 of the p-type TFT is heavily doped with the drain contact region 140 and the second storage capacitor contact region 143 by ion implantation, as shown in FIG. .

Step S106: etching the remaining photoresist of the upper step to form a gate insulating film 15 on the heavily doped polysilicon film 14, as shown in FIG.

Step S107: A gate metal film 16' is formed on the gate insulating film 15, as shown in FIG.

Step S108: forming the metal line 16.

Coating a photoresist on the surface of the gate metal film 16', using a fourth mask, utilizing The ultraviolet rays are irradiated and developed to form metal lines 16 corresponding to the n-type TFT channels 146, the p-type TFT channels 149, and the first and second storage capacitor contact regions 142, 143, respectively, by blocking of the metal lines 16. Self-aligned doped (LDD), as shown in Figure 9. This doping has substantially no effect on the source contact region 148 of the p-type TFT and the drain contact region 140.

Step S109: forming a dielectric layer. As shown in FIG. 10, a dielectric film 17' is formed on the surface of the gate insulating film 15 and the metal line 16, and a fifth mask (the mask technique is usually applied with a photoresist on the surface of the patterned object, and irradiated with ultraviolet rays. The process of developing a pattern, which will not be described hereinafter, forms the dielectric layer 17 and fabricates the connection channel as shown in FIG. This connection channel connects the polysilicon film 14 to the surface of the dielectric layer 17.

Step S110: The electrode metal wire is formed into a film.

An electrode metal line film 18 is formed on the surface of the dielectric layer 17 and the connection channel. As shown in FIG. 12, the electrode metal line film 18 is patterned by using a sixth mask, that is, an n-type TFT and a p-type TFT are formed. The four electrodes 181, 182, 183, 184 of the source and the drain are as shown in FIG.

Step S111: The flat layer is formed into a film.

A flat layer film is formed, a flat layer film pattern is formed by using a seventh mask to form a flat layer 19, and openings are formed in the surfaces of the n-type TFT drain 182 and the p-type TFT source 183, as shown in FIG.

Step S112: forming a conductive film, that is, an Indium-TinOxide (ITO) film.

An indium tin oxide film 199 is formed on the surface of the flat layer 19 and the opening, as shown in the figure 15 is shown. The indium tin oxide film 199 is patterned by the eighth mask to form the thin film transistor substrate 1 as shown in FIGS. 1 and 16.

The conventional polycrystalline and occluded masks have a complicated process for fabricating a thin film transistor substrate, and the manufacturing cost is high.

In view of the above, it is necessary to provide a basic method for fabricating a thin film transistor having a simple mask manufacturing step and a low manufacturing cost.

A method for fabricating a thin film transistor substrate, comprising the steps of: providing a substrate on which a polycrystalline germanium film is formed; and forming a polycrystalline germanium film pattern comprising source contacts of a plurality of first type of thin film transistors a source contact region and a drain contact region of the plurality of second type thin film transistors; and a source contact region and a drain contact region of the first type of thin film transistor are heavily doped; Forming a gate insulating film on the surface of the polysilicon film, forming a gate metal line thereon; self-aligning heavily doping the source contact region and the drain contact region of the second type of thin film transistor; in the gate insulating film and Forming a dielectric layer on a surface of the gate metal line; forming a connection channel connecting the polysilicon film to a surface of the dielectric layer; forming an electrode metal line in the connection channel; wherein the first type of thin film transistor and the second type of thin film transistor The heavy doping compensates each other.

A method for fabricating a thin film transistor substrate, comprising the steps of: providing a substrate on which a polycrystalline germanium film is formed; and forming a polycrystalline germanium film pattern comprising source contacts of a plurality of first type of thin film transistors Zone and drain contact regions, storage capacitor contact regions, source contact regions and gate contact regions of a plurality of second type of thin film transistors; for the first type of film The source contact region of the transistor is heavily doped with the drain contact region and the storage capacitor contact region; a gate insulating film is formed on the surface of the polysilicon film to form a gate metal line thereon; and a second type of thin film transistor source is formed The contact region and the drain contact region are self-aligned heavily doped; a dielectric layer is formed on the surface of the gate insulating film and the gate metal line; and a connection channel is formed to connect the polysilicon film to the surface of the dielectric layer; The channels form electrode metal lines; wherein the first type of thin film transistors and the second type of thin film transistors are mutually doped to compensate each other.

Compared with the prior art, the manufacturing method of the thin film transistor substrate of the present invention successfully reduces the eight mask manufacturing processes originally required to six masks, and the reduction of the number of masks makes the manufacturing steps have greater advantages in cost; The number of films is reduced, and the surface is relatively flat after forming. Therefore, the flat layer can be omitted to make the thickness of the thin film transistor substrate relatively thin, and the photoresist is not required to be formed multiple times during heavy doping, but is compensated for the doping of the two types of thin film transistors. The method saves the production steps.

Figure 17 is a partial structural schematic view of a thin film transistor substrate of the present invention. The thin film transistor substrate 2 includes an n-type TFT 77, a storage capacitor (not shown) adjacent to the n-type TFT 77, and a p-type TFT 88. The thin film transistor substrate 2 includes a substrate 21, a buffer layer 22 disposed on the substrate 21, a polysilicon film 24, a gate insulating film 25, and a three-gate metal line 26 spaced apart from each other. Layer 27 and an indium tin oxide film 29. The metal wires 26 at the two ends of the thin film transistor substrate 2 shown in FIG. 17 are the gate metal wires of the n-type TFT 77 and the p-type TFT 88, respectively, and the intermediate metal wires 26 are electrodes for storing capacitance, and the thin film transistor substrate 2 further includes a storage capacitor. The electrode 285 and one end are connected to the polysilicon film 24, and the other end is disposed on the surface of the dielectric layer 27. The four electrodes 281, 282, 283, and 284 are the source and drain of the n-type TFT 77 and the p-type TFT 88, respectively. The drain 282 of the n-type TFT and the source 283 of the p-type TFT and the storage capacitor electrode 285 are connected to the indium tin oxide film 29. The polysilicon film 24 includes an n-type TFT contact region 241, a storage capacitor contact region 242, and a P-type TFT contact region 243. The n-type TFT contact region 241 includes a source contact region 245, a via 246, and a drain contact region 247. The p-type TFT contact region 243 includes a source contact region 248, a channel 249, and a drain contact region 240.

18 to 27 are flowcharts showing a method of manufacturing the thin film transistor substrate 2 shown in Fig. 17. The specific steps of the method of manufacturing the thin film transistor substrate 2 are as follows: Step S201: A polysilicon film 24 is formed on the substrate 21.

A buffer layer 22 is formed on the substrate 21, and the material of the buffer layer 22 is usually tantalum nitride and tantalum oxide, as shown in FIG. An amorphous germanium film 23 is formed on the buffer layer 22 as shown in FIG. The amorphous germanium film 23 is melted and crystallized by excimer laser annealing to form a polycrystalline germanium film 24.

Step S202: forming an active layer, that is, a polysilicon film pattern.

Applying a photoresist to the surface of the polysilicon film 24, aligning the polysilicon film 24 with a first mask, irradiating the first mask with ultraviolet rays in parallel, and developing the polysilicon film 24 to form an active layer pattern, that is, A pattern of the polysilicon film 24 including an n-type TFT contact region 241, a storage capacitor contact region 242, and a p-type TFT contact region 243, as shown in FIG.

Step S203: The source contact region 248 of the P-type TFT is heavily doped with the drain contact region 240 and the storage capacitor contact region 242.

The residual photoresist of step 202 is etched to form a coating pattern as shown in FIG. 21, that is, the photoresist of the n-type TFT contact region 241 is 2 unit thickness, and the storage capacitor contact region 242 has a photoresist of 1 unit thickness, and the p-type TFT The source contact region 248 and the drain contact region 240 are 1 unit thickness, and the p-type TFT channel 249 region photoresist thickness is 2 unit thickness. The photoresist is a half-tone photoresist, that is, according to how much energy is absorbed. Photoresist, as shown in Figure 21. The second mask exposes and develops the photoresist. After exposure and development, the photoresist of the n-type TFT contact region 241 is 1 unit thickness, the storage capacitor contact region 242 has no photoresist, and the p-type TFT source contact region 248 is in contact with the drain. The region 240 has no photoresist, and the p-type TFT channel 249 region photoresist has a unit thickness. The p-type TFT source contact region 248 and the drain contact region 240 and the storage capacitor contact region 242 are heavily doped by the blocking of the photoresist. , as shown in Figure 22.

Step S204: removing the residual photoresist, forming a gate insulating film 25 on the buffer layer 22 and the surface of the polysilicon film 24, as shown in FIG.

Step S205: forming a gate metal line 26.

A gate metal film is formed on the surface of the gate insulating film 25, and the photoresist is exposed and developed by a third mask, and the gate metal film is exposed and developed in the n-type TFT channel 246, the storage capacitor contact region 242, and the p-type. The gate of the TFT channel 249 is formed with a gate metal line 26, wherein the corresponding area of the storage capacitor contact region 242 is an electrode for storing capacitance, which is collectively referred to as a gate metal line 26 for convenience of expression.

Step S206: self-aligned heavily doping the n-type TFT source contact region 245 and the drain contact region 247.

Blocking the n-type TFT source contact region 245 by the gate metal line 26 Self-aligned n-type heavily doping with the gate contact region 247; although the source contact region 248 of the p-type TFT and the gate contact region 240 are heavily doped at the same time, since the P-type doping has been performed twice as long Therefore, the source contact region 248 and the drain contact region 240 of the p-type TFT are still twice as large as normal doping, as shown in FIG.

Step S207: Forming the dielectric layer 27.

A dielectric film is formed on the surface of the gate insulating film 25 and the gate metal line 26, and a photoresist is coated thereon, and a fourth mask is used to form a dielectric layer 27 to form a connection channel after exposure and development, as shown in FIG. 25. The connection channel connects the polysilicon film 24 to the surface of the dielectric layer 27, and at the same time, the storage capacitor electrode to the surface of the dielectric layer 27 also forms a channel.

Step S208: The electrode metal wire is formed into a film.

An electrode metal wire film is formed on the surface of the dielectric layer 27 and the connection channel, and a photoresist is applied thereon, and the electrode metal wire film 28 is patterned by using a fifth mask, and an n-type TFT and a p-type TFT are formed after exposure and development. The four electrodes 281, 282, 283, 284 of the source and drain electrodes and the storage capacitor electrode 285 are as shown in FIG.

Step S209: forming a conductive film, that is, an Indium-Tin-Oxide (ITO) film.

An indium tin oxide film 29 is formed on the surfaces of the four electrodes 281, 282, 283, and 284 and the storage capacitor electrode 285. The coating photoresist is patterned by using the sixth mask to form the indium tin oxide film 29, and the indium tin oxide film 29 is formed after exposure and development. A thin film transistor substrate 2 as shown in FIGS. 17 and 27 is formed on the surface of the drain 282 of the n-type TFT, the electrode 285 of the storage capacitor, and the source 283 of the p-type TFT.

The p-type TFT is doped with trivalent boron ions, and the n-type TFT is doped with pentavalent phosphorus ions.

The method for compensating doping of p-type TFT and n-type TFT of the invention succeeds in reducing the manufacturing process of the eight masks originally required to six masks, and the reduction of the number of masks makes the manufacturing steps less advantageous in terms of cost. The number of masks is reduced, and the surface of the substrate is relatively flat after forming. Therefore, the flat layer can be omitted to make the thickness of the thin film transistor substrate relatively thin; when heavily doping, it is not necessary to form a photoresist multiple times, but for the p-type TFT and the n-type TFT. The method of compensating doping saves the fabrication steps of doping.

The introduction of the storage capacitor in the present invention means that the capacitor can be formed together while forming the TFT, and the FPC is saved in the peripheral driving circuit applied to the liquid crystal display substrate or the organic light-emitting display substrate, thereby further saving the component cost.

The present invention is not limited to the above embodiment, and the n-type TFT may be heavily doped twice, and then the p-type TFT is heavily doped once, and then the thin film transistor substrate is formed by the n-type TFT. The two heavily doped neutralizations still have one-fold heavy doping after mutual compensation.

In summary, the present invention has indeed met the requirements of the invention patent, and has filed a patent application according to law. However, the above description is only the preferred embodiment of the present invention, and the scope of the present invention is not limited to the above-described embodiments, and equivalent modifications or variations made by those skilled in the art in light of the spirit of the present invention are It should be covered by the following patent application.

Thin film transistor substrate ‧‧‧2

Substrate ‧‧21

Buffer layer ‧‧22

Amorphous film ‧‧23

Polycrystalline film ‧‧24

Gate insulating film ‧‧‧25

Gate metal wire ‧‧26

Dielectric layer ‧‧27

Indium tin oxide film ‧‧‧29

N-type TFT‧‧‧77

P-type TFT‧‧‧88

P-type TFT 汲 contact area ‧‧ ‧240

N-type TFT contact area ‧‧‧241

Storage Capacitor Contact Area ‧‧242

P-type TFT contact area ‧‧‧243

N-type TFT source contact area ‧‧‧245

N-type TFT channel ‧‧‧246

N-type TFT 汲 contact area ‧‧‧247

P-type TFT source contact area ‧‧‧248

P-type TFT channel ‧‧‧249

Storage Capacitor ‧‧‧285

Four electrodes ‧‧‧281, 282, 283, 284

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a partial schematic view of a prior art thin film transistor substrate.

2 to 16 are flowcharts showing a method of manufacturing the thin film transistor substrate shown in Fig. 1.

Figure 17 is a partial structural schematic view of a thin film transistor substrate of the present invention.

18 to 27 are flowcharts showing a method of manufacturing the thin film transistor substrate shown in Fig. 17.

Thin film transistor substrate ‧‧‧2

Substrate ‧‧21

Buffer layer ‧‧22

Polycrystalline film ‧‧24

Gate insulating film ‧‧‧25

Gate metal wire ‧‧26

Dielectric layer ‧‧27

Indium tin oxide film ‧‧‧29

N-type TFT‧‧‧77

P-type TFT‧‧‧88

P-type TFT 汲 contact area ‧‧ ‧240

N-type TFT contact area ‧‧‧241

Storage Capacitor Contact Area ‧‧242

P-type TFT contact area ‧‧‧243

N-type TFT source contact area ‧‧‧245

N-type TFT channel ‧‧‧246

N-type TFT 汲 contact area ‧‧‧247

P-type TFT source contact area ‧‧‧248

P-type TFT channel ‧‧‧249

Storage Capacitor ‧‧‧285

Four electrodes ‧‧‧281, 282, 283, 284

Claims (10)

A method for fabricating a thin film transistor substrate, comprising the steps of: providing a substrate on which a polycrystalline germanium film is formed; and forming a polycrystalline germanium film pattern comprising source contacts of a plurality of first type of thin film transistors a source contact region and a drain contact region of the plurality of second type thin film transistors; and a source contact region and a drain contact region of the first type of thin film transistor are heavily doped; Forming a gate insulating film on the surface of the polysilicon film, forming a gate metal line thereon; self-aligning heavily doping the source contact region and the drain contact region of the second type of thin film transistor; in the gate insulating film and Forming a dielectric layer on a surface of the gate metal line; forming a connection channel connecting the polysilicon film to a surface of the dielectric layer; forming an electrode metal line in the connection channel; wherein the first type of thin film transistor and the second type of thin film transistor The heavy doping is mutually compensated, wherein the source contact region and the drain contact region of the first type of thin film transistor are double doped twice, and the second type of thin film transistor source The self-aligned heavy doping amount of the polar contact region and the drain contact region is doubled. The method for fabricating a thin film transistor substrate according to claim 1, wherein the polysilicon film pattern further comprises a plurality of channel regions between the source contact region and the drain contact region, and the second type of film is electrically The photoresist in the contact area of the crystal is 1 unit thickness, and the source contact area and the drain contact area of the first type of thin film transistor have no photoresist, and the photoresist of the first type of thin film transistor channel is 1 unit thickness, and the light is utilized. The occlusion of the resist heavily heavily doped the source and drain contact regions of the first type of thin film transistor. The manufacturer of the thin film transistor substrate according to claim 1 of the patent application scope The method of forming a polycrystalline germanium film comprises forming a buffer layer on a substrate, forming an amorphous germanium film on the buffer layer, and melting the amorphous germanium film into a polycrystalline germanium film by excimer laser annealing. The method for producing a thin film transistor substrate according to any one of claims 1 to 3, wherein the first type of thin film transistor is a p type thin film transistor, and the second type of thin film transistor is an n type Thin film transistor. The method for producing a thin film transistor substrate according to any one of claims 1 to 3, wherein the first type of thin film transistor is an n type thin film transistor, and the second type of thin film transistor is a p type Thin film transistor. A method for fabricating a thin film transistor substrate, comprising the steps of: providing a substrate on which a polycrystalline germanium film is formed; and forming a polycrystalline germanium film pattern comprising source contacts of a plurality of first type of thin film transistors Region and drain contact region, storage capacitor contact region, source contact region and drain contact region of a plurality of second type thin film transistors; source contact region and drain contact region of the first type of thin film transistor And the storage capacitor contact region is heavily doped; a gate insulating film is formed on the surface of the polysilicon film, and a gate metal line is formed thereon; and the second type of thin film transistor source contact region and the drain contact region are self-aligned Heavy doping; forming a dielectric layer on the surface of the gate insulating film and the gate metal line; forming a connection channel connecting the polysilicon film to the surface of the dielectric layer; forming an electrode metal line in the connection channel; wherein the first type of film The doping of the transistor with the second type of thin film transistor is mutually compensated, wherein the source contact region and the drain contact region of the first type of thin film transistor are heavily doped 2 times, the second type of the thin film transistor source contact region and drain contact regions The self-aligned heavy doping amount is 1 time. The method for fabricating a thin film transistor substrate according to claim 6, wherein the polysilicon film pattern further comprises a plurality of channel regions between the source contact region and the drain contact region, and the second type of thin film is electrically The photoresist in the crystal contact area is 1 unit thickness, and the storage capacitor contact area has no photoresist. The first type of thin film transistor source contact area and the drain contact area have no photoresist, and the first type of thin film transistor channel area resist For one unit thickness, the first type of thin film transistor source contact region and the drain contact region and the storage capacitor contact region are heavily doped by blocking of the photoresist. The method for producing a thin film transistor substrate according to claim 6, wherein the step of forming a polysilicon film comprises forming a buffer layer on the substrate, forming an amorphous germanium film on the buffer layer, and using excimer laser annealing, The amorphous ruthenium film is melted and crystallized to form a polycrystalline ruthenium film. The method for producing a thin film transistor substrate according to any one of claims 6 to 8, wherein the first type of thin film transistor is a p type thin film transistor, and the second type of thin film transistor is an n type Thin film transistor. The method for producing a thin film transistor substrate according to any one of claims 6-8, wherein the first type of thin film transistor is an n type thin film transistor, and the second type of thin film transistor is a p type Thin film transistor.