TWI423006B - Frequency modulation method executed under operation system - Google Patents

Description

Frequency modulation method performed under the operating system

The present invention relates to a frequency modulation method performed under an operating system, and more particularly to a frequency modulation method for improving the operating frequency of an information processing device without restarting.

The processing efficiency of information processing devices depends directly on the frequency of their operation. Therefore, in the modern society where every second counts, over-frequency setting of information processing devices is a fairly common processing mode. The so-called overclocking setting is to increase the operating frequency of the specific hardware of the information processing device, such as the central processing unit or the image processor, to a higher than the rated frequency value, thereby increasing the operating frequency of the information processing device as a whole.

In the overclocking setting mode of the conventional information processing device, the user needs to enter the basic input/output system (BIOS) of the information processing device to perform the lifting operation for the operating frequency of the specific hardware when the information processing device is turned on. After the upgrade is completed, the user needs to restart the information processing device to enter the operating system (OS), so that the information processing device can operate at a higher operating frequency. In order to serve users who are unfamiliar with the operation mode of the basic input/output system, there is also an information processing available on the market for the user to directly increase the operating frequency of the specific hardware in the operating system, and then restart after the upgrade is completed. Device.

However, the current overclocking setting method, whether for the user to set in the basic input/output system or in the operating system, restarts It is an inevitable step after the completion of the work frequency increase, but since restarting means that the user must end the related work at hand, the current overclocking setting method is often quite inconvenient for the user. Secondly, since the current overclocking setting method does not adjust the power supply of the information processing device correspondingly, even if the user has completed the overclocking setting in the basic input/output system or the operating system, and the restart has been completed, the information is completed. The processing device is often unable to perform the actual operation at a higher operating frequency due to factors such as insufficient power supply or instability, and thus is equivalent to the failure of the overclocking setting. Furthermore, since the current overclocking setting method lacks a convenient and stable frequency release mechanism, when the user wants to reduce the operating frequency back to the original rated value, it usually needs to be completed through a cumbersome frequency reduction step. In order to increase the user's operational burden.

In view of the deficiencies of the prior art, the object of the present invention is to provide a frequency modulation method for efficiently and stably increasing the operating frequency of an information processing device without restarting.

In order to achieve the foregoing and other objects, the present invention provides a frequency modulation method performed under an operating system, which is applied to an embedded controller, a clock generator, a central processing unit, a system bus, and an image processor. In the information processing device, the frequency modulation method executed under the operating system includes the following steps: (1) causing the information processing device to receive an overclocking control signal input by the user; and (2) causing the embedded controller Upgrading the voltage level of the central processing unit, the system bus and the image processor according to the overclocking control signal received by the information processing device; and (3) The embedded controller adjusts the operating frequency of the central processing unit, the system bus, and the image processor according to the overclocking control signal received by the information processing device, thereby increasing the operating frequency of the information processing device. .

The frequency modulation method performed by the operating system includes the following steps: (4) when the information processing device receives the input of the down-conversion control signal, the shutdown signal, the restart signal, the sleep signal or the sleep signal, The clock generator reduces the operating frequency of the central processing unit, the system bus, and the image processor; and (5) the operating frequency of the central processing unit, the system bus, and the image processor is reduced to After a predetermined rating, the embedded controller is caused to lower the voltage level of the central processing unit, the system bus, and the image processor, thereby reducing the operating frequency of the information processing device.

Furthermore, in an embodiment of the present invention, the information processing device provides a user interface for setting an input signal related to the down-conversion control signal, the shutdown signal, the restart signal, the sleep signal, or the sleep signal. The input signal is such that the embedded controller causes the clock generator to gradually reduce the operating frequencies of the central processing unit, the system bus, and the image processor in a phased manner.

Therefore, the present invention can increase the central processing unit, system bus, and image processing of the information processing device when the user wants to increase the operating frequency of the information processing device by the interaction of the embedded controller and the clock generator. The voltage level of the device is then increased by the operating frequency of the central processing unit, system bus and image processor of the information processing device, and is adjusted in stages, so that the information processing device can be stably operated without restarting the information processing device. Information office The operating frequency of the device is increased to the overclocking setting desired by the user. Further, the present invention can be embedded by the user when the user wants to adjust the operating frequency of the information processing device back to the original rated value, that is, when the overclocking mode is restored to the normal mode, or when the information processing device is finished operating. The interaction between the controller and the clock generator first adjusts the operating frequency of the central processing unit, the system bus and the image processor of the information processing device, and then lowers the central processing unit, system bus and image processor of the information processing device. The voltage level, and because the present invention adjusts the system frequency at different speeds in the overclocking mode and from the overclocking mode to the normal mode, the system can maintain stable operation during the frequency modulation process.

The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure. Of course, the invention may be embodied or applied by other different embodiments.

Please refer to FIG. 1 to FIG. 3 for a clear understanding of the frequency modulation method performed by the operating system in the present invention. FIG. 1 is a flowchart showing the frequency modulation method performed by the operating system in the present invention. FIG. 2 is a block diagram of a power supply system to which the frequency modulation method performed under the operating system of the present invention is applied, and FIG. 3 is a frequency system to which the frequency modulation method performed by the operating system of the present invention is applied. Block diagram. It should be noted that the frequency modulation method performed by the operating system in the present invention is applied to an embedded controller (EC) 1, a clock generator 2, and a central processing unit. (CPU) 3, system The information processing device (not shown) of the bus bar 4 and the image processor (VGA) 5, and the information processing device can be, for example, a desktop computer, a notebook computer or a tablet computer. Of course, in other embodiments of the embodiment, the information processing device may optionally not have a video processor (VGA) 5.

In step S11, the information processing device is configured to receive the overclocking control signal input by the user, and the overclocking control signal may include the overclocking setting value that the user desires to set. In order to provide better operability, before performing step S11, the singapore information processing device provides a user interface (not shown) for the user to set the overclocking control signal, thereby performing information processing when performing step S11. The device can receive the overclocking control signal input by the user through the user interface. Specifically, the user interface may be a window type application executed in the operating system, and an input box, an input button, or an input menu, for example, is input for the user to input the overclocked setting value to be set, and then performed. Step S12.

In step S12, the embedded controller 1 is configured to raise the voltage level of the central processing unit 3, the system bus 4, and the image processor 5 according to the overclocking control signal received by the information processing device. For example, the embedded controller The system can adjust the voltage level of the central processing unit 3, the system bus 4 and the image processor 5 to the overclocking setting value included in the corresponding overclocking control signal. In actual implementation, the voltage level is hard. Body design, and the embedded controller 1 only sets the voltage level up or down. Therefore, as shown in Figure 2, the embedded controller 1 can pass through the control chip (such as V-Core Control IC) and pulse width. Pulse Width Modulation (PWM) To raise the voltage level of the central processing unit 3, and at the same time, through the pulse width shifter to increase the voltage level of the video random memory (V-RAM), the system memory (system memory), the north bridge chip and the south bridge chip. Then, the step of adjusting the voltage levels of the system bus 4 and the image processor 5 is completed, and then proceeds to step S13.

In step S13, the embedded controller 1 is caused to increase the operating frequency of the central processing unit 3, the system bus 4, and the image processor 5 according to the overclocking control signal received by the information processing device. The embedded controller 1 enables the clock generator 2 to gradually increase the operating frequencies of the central-center processor 3, the system bus 4 and the image processor 5 in a phased manner to maintain the overall operation of the information processing device. Stability. In a specific implementation, the clock generator 2 can gradually increase the CPU 3, the system bus 4, and the image processor in a phased manner by, for example, increasing the speed of 1 Hz (1 Hz/40 ms) every 40 milliseconds. The operating frequency of 5 until the operating frequency of the central processing unit 3, the system bus 4 and the image processor 5 has reached the overclocking setting included in the overclocking control signal. The circuit system relationship of the clock generator 2, the central processing unit 3, the system bus 4, and the image processor 5 in the operating frequency modulation processing is as shown in FIG.

It can be seen from the description of the foregoing steps S11 to S13 that the present invention can be used in the environment of the operating system by the embedded controller 1 and the pulse generator 2, and the user can conveniently adjust the central processing unit of the information processing device first. 3. The voltage level of the system bus 4 and the image processor 5 is adjusted, and the operating frequency of the central processing unit 3, the system bus 4 and the image processor 5 of the information processing device is adjusted to perform so-called overclocking setting. This stable and effective Improve the overall operating frequency of the information processing device and complete the so-called overclocking setting.

Furthermore, after the overclocking setting is completed, if the user wants to adjust the operating frequency of the information processing device back to the original rated value, or if the user wants to end or suspend the use of the information processing device whose operating frequency has been increased, The invention may also optionally perform a process flow diagram as shown in FIG.

As shown in FIG. 4, in step S14, the information processing device is configured to receive the down-conversion control signal input by the user, or to cause the information processing device to receive different sleep/standby state start signals, such as: shutdown signal, restart Signal, sleep signal or sleep signal. In order to provide better operability, before the step S14 is performed, the re-commissioning includes the user interface step of the information processing device for the user to input the down-clocking signal, whereby the information processing device can be borrowed when performing step S14. Receiving, by the user interface, a down-conversion control signal input by the user, or by using the user interface to cause the embedded controller of the information processing device to receive a so-called shutdown signal, a restart signal, a sleep signal or a sleep signal, and then proceeding Go to step S15. Specifically, the user interface provided by the information processing device before the step S14 is performed may be the same as the user interface provided by the information processing device before the step S11 is performed, and the down-conversion control signal input by the user may be “end”. The overclock mode command, except for the down-converted signal input by the user, the shutdown signal, restart signal, sleep signal, or sleep signal received by the embedded controller can be a Cold boot defined by ACPI OSPM-model. /Shutdown (S0->S5) command, Warm boot/restart command, Sleep/Sleep (S0->S3) command, and Hibernate/Sleep (S0->S4) instructions defined by ACPI OSPM-model, then proceed to the step S15.

In step S15, the embedded controller 1 causes the clock generator 2 to downgrade the central processing unit 3 and the system according to the down-conversion control signal, the shutdown signal, the restart signal, the sleep signal or the sleep signal received by the information processing device. The operating frequency of bus 4 and image processor 5. For example, the embedded controller 1 can cause the clock generator 2 to gradually and stably reduce the operating frequencies of the central processing unit 3, the system bus 4, and the image processor 5 back to the original state in a phased manner. Rating to maintain the stability of the overall information processing device. In a specific implementation, when the information processing device receives the down-conversion control signal, the sleep signal, or the sleep signal input by the user, the embedded controller 1 can cause the clock generator 2 to decrease, for example, every 80 milliseconds. The first speed of the Hertz (2Hz/80ms) is used to reduce the operating frequency of the central processing unit 3, the system bus 4 and the image processor 5 in a phased manner until the central processing unit 3 and the system bus 4 And the operating frequency of the image processor 5 has returned to the original rated operating frequency. In addition, when the information processing device receives the shutdown signal or the restart signal input by the user, the embedded controller 1 can cause the clock generator 2 to decrease by 2 Hz (2 Hz/560 ms) every 560 milliseconds, for example. The second speed is adjusted to reduce the operating frequency of the central processing unit 3, the system bus 4 and the image processor 5 in a phased manner until the central processing unit 3, the system bus 4 and the image processor 5 work. The frequency has returned to the original rated operating frequency. Thereby, the present invention can flexibly provide different mode of lowering according to different state transition modes, thereby enabling the information processing system to maintain the sleep/standby state transition defined by the ACPI OSPM-model in a stable operating system environment. And does not cause the operating system that was originally in operation to produce If a mistake occurs or a crash occurs, it proceeds to step S16.

In step S16, the embedded controller 1 is configured to downgrade the central processing unit 3, the system bus 4, and the image processing according to the down-conversion control signal, the shutdown signal, the restart signal, the sleep signal, or the sleep signal received by the information processing device. The voltage level of the device 5. For example, as shown in FIG. 2, the embedded controller 1 can adjust the voltage level of the central processing unit 3 to the original rated value through the control chip and the pulse width shifter, and simultaneously transmit the pulse. The width adjuster reduces the voltage level of the video random memory (V-RAM), system memory (System Memory), north bridge chip and south bridge chip back to the original rated value, thereby completing the system bus 4 and image processing. The overall voltage level of the device 5 is reduced.

As can be seen from the contents of the above steps S14 to S16, the present invention reduces the operating frequency of the central processing unit, the system bus and the image processor of the information processing device by the embedded controller and the pulse generator. The voltage level of the central processing unit, system bus, and image processor of the information processing device is gradually and stably stabilized by the user through a simple operation mode by means of phase frequency modulation. The operation frequency of the information processing device is adjusted back to the original rating.

It is worth mentioning that the entire operation process of the present invention has two main control processes, one is that the user actively decides to overclock or downrate through the user interface; the second is the embedded controller. Actively determine the input signal related to the shutdown signal, restart signal, sleep signal or sleep signal, and the basis for judging these different behaviors is to judge the system related state according to the status flag or status code, not the operating frequency.

Next, the processing flow of a specific embodiment of the frequency modulation method performed by the operating system according to the present invention, such as the fifth (A) and the fifth (B), will be described in detail in conjunction with the processing steps shown in the first and fourth figures. As shown in the figure, first step S20 is executed to determine whether the information processing device operates under the operating system (OS), and if so, proceeds to step S21; otherwise, the processing step of the frequency modulation method executed by the operating system in the present invention is terminated. .

In step S21, it is determined whether the information processing apparatus performs the power-on or restart operation, and if yes, the process proceeds to step S28; otherwise, the process proceeds to step S22.

In step S22, it is determined whether the information processing apparatus performs a sleep or a sleep operation. If yes, the process proceeds to step S28; otherwise, the process proceeds to step S23. It should be noted that the order of execution of the step S22 and the step S21 may be interchanged, that is, not limited thereto.

In step S23, it is determined whether the information processing apparatus executes the overclocking mode, and if so, the process proceeds to step S24; otherwise, the processing procedure of the frequency modulation method executed by the operating system in the present invention is terminated.

In step S24, during the processing of the overclocking mode by the information processing apparatus, it is determined whether the voltage level of the central processing unit, the system bus, and the image processor has been upgraded to the voltage level required for overclocking. If the bit has been upgraded, the process goes to step S26; otherwise, the process goes to step S25, that is, the voltage levels of the central processing unit, the system bus and the image processor are raised, and then the entire processing cycle is restarted until the overclocking is reached. The required voltage level is up.

In step S26, determining the central processing unit, the system bus and the image Whether the operating frequency of the processor reaches the set overclocking setting value, and if so, the processing steps of the frequency modulation method performed by the operating system in the operating system can be ended; otherwise, if the operating frequency required for overclocking has not been reached, Step S27, that is, the operating frequency of the central processing unit, the system bus, and the image processor is upgraded, and then the entire processing cycle is restarted until the set overclocking setting value is reached, and the present invention is terminated in the operating system. The processing steps of the frequency modulation method performed below.

In the step S28, the step S21 or the step S22 is continued, that is, when the information processing device performs the shutdown, restart, sleep or sleep operation, it is determined whether the information processing device is in the overclocking mode, and if so, proceeds to the step S29; otherwise, the processing steps of the frequency modulation method performed by the present invention under the operating system can be ended.

It is explained here that whether the foregoing information processing device is in the overclocking mode is determined according to the state flag value in the embedded controller. For example, when the user completes the overclocking mode setting, the embedded controller The status flag value is set, so that when the information processing device performs a shutdown, restart job, sleep job, or hibernation operation, the presence or absence of the status flag value or its value is "1" or "0. ", to know the operating frequency mode of the information processing device in the current state.

In step S29, when the information processing apparatus performs the shutdown, restart operation, sleep operation or sleep operation, it is determined whether the operating frequency of the central processing unit, the system bus, and the image processor has been reduced to the original amount. The value, if yes, proceeds to step S31; otherwise, proceeds to step S30, that is, the operating frequency of the central processing unit, the system bus, and the image processor The rate is subjected to the down-conversion process, and then the entire processing cycle is restarted until the original nominal value is restored, and the processing steps of the frequency modulation method performed by the present invention under the operating system can be restarted. It should be noted that the present invention is reduced in different ways to the original rating in response to different state transition conditions. As described above, if the information processing device is in a sleep or sleep state, the embedding The controller 1 can cause the clock generator 2 to down, for example, 2 Hz (2 Hz/80 ms) every 80 milliseconds; further, if the information processing device is in a shutdown state or a restart state, the embedded controller 1 The clock generator 2 can be adjusted to, for example, 2 Hz (2 Hz/560 ms) every 560 milliseconds.

In step S31, it is determined whether the voltage levels of the central processing unit, the system bus, and the image processor have been adjusted to the original rated value. If the original rated value has been restored, the present invention can be terminated. The processing steps of the frequency modulation method performed under the operating system; otherwise, proceeding to step S32, the voltage levels of the central processing unit, the system bus, and the image processor are lowered, and the entire processing flow is restarted, and then The entire processing cycle is restarted until the original nominal value is restored, and the processing steps of the frequency modulation method performed by the present invention under the operating system can be terminated.

In order to further clarify that the frequency modulation method performed by the operating system of the present invention utilizes phase adjustment, please refer to FIG. 6 for explaining that the present invention performs phase adjustment with voltage level and operating frequency. The timing diagram includes the processing of the overclocking mode and the down mode, that is, the processing of the overclocking mode from the time point t ₁ to the time point t ₃ , and from the time point t ₃ to the time point t ₄ The process for the down mode. It should be noted that since Fig. 6 is a timing relationship diagram between the two operations of adjusting the voltage level and adjusting the operating frequency, there is no specific unit on the vertical axis.

As shown in the figure, before the time point t ₁ , the voltage levels of the central processing unit 3 , the system bus 4 and the image processor 5 are the rated voltage value V ₁ , and the central processing unit 3 , the system bus 4 and the image The operating frequency of the processor 5 is the nominal frequency value H ₁ . At times t ₁ the current point, the information processing apparatus based receiving user input of the control signal OC, the embedded system controller 1 then raised central processor 3, the voltage level of the system bus 4, and the image processor 5 To the set voltage value V ₂ , in other words, the time point t ₁ when the lower system represents the voltage level has been raised. During the time point t ₁ to the time point t ₂ , the embedded controller 1 causes the clock generator 2 to gradually increase the operating frequency of the central processing unit 3, the system bus 4, and the image processor 5 to the set frequency value H. ₂ , while the time point t ₂ now represents the working frequency has been increased. At the time point t ₃ , the information processing device receives the down-conversion control signal, the shutdown signal, the restart signal, the sleep signal or the sleep signal, and the embedded controller 1 starts to connect the central processing unit 3 and the system bus 4 And the operating frequency of the image processor 5 is gradually reduced back to the rated frequency value H ₁ . At the time point t ₄ , the embedded controller 1 adjusts the voltage levels of the central processing unit 3, the system bus 4, and the image processor 5 back to the rated voltage value V ₁ , that is, the time point t _{4 .} The lower system represents the voltage level and the operating frequency have been reduced.

In other words, before the time point t _1, the operating frequency of the information processing apparatus based rating is maintained, i.e., the information processing apparatus is in the general state of the system (Normal State) below. During the time point t ₁ to t ₂ , the operating frequency of the information processing device is gradually increased to the user's overclocking setting value, that is, the information processing device is in the up state of the up-converted state (Dynamic State); ₂ to t ₃ rooms, operating frequency coefficient information processing apparatus is maintained at the set value OC user, i.e. the information processing apparatus based OC is at a steady state has been (steady state); time point t ₃ to t ₄ rooms, The operating frequency of the information processing device is gradually reduced back to the original rated value, that is, the information processing device is in the state of frequency reduction (Dynamic State); after the time point t ₄ , the operating frequency of the information processing device It is back to the rated value, that is, the information processing device is in the normal state (Normal State). It is worth mentioning that, in actual implementation, in order to maintain the overall system stability of the information processing device, the interval from time point t ₁ to time point t ₂ can be set to 3.2 seconds, and the interval from time point t ₃ to time point t ₄ . It can be set to 8.8 seconds.

Therefore, compared with the prior art, the present invention can stably and effectively improve the overall operating frequency of the information processing device without requiring a restart, so that the overclocking setting of the user is not caused by insufficient or unstable power supply. The factor failed. Furthermore, the present invention can be used in an environment of an operating system for the user to simply and quickly change the operating frequency of the information processing device in different manners depending on different states such as sleep, hibernation, shutdown, or restart. Downgrading back to the original rating provides more convenient operation than conventional techniques.

However, the above-described embodiments are merely illustrative of the principles and effects of the invention and are not intended to limit the invention. Modifications and variations of the above-described embodiments can be made by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as described later. Please list the scope of the patent.

1‧‧‧ embedded controller

2‧‧‧ clock generator

3‧‧‧Central processor

4‧‧‧System Bus

5‧‧‧Image Processor

t ₁ , t ₂ , t ₃ , t ₄ ‧‧‧

H ₁ ‧‧‧Rated frequency value

H ₂ ‧‧‧Set frequency value

V ₁ ‧‧‧ rated voltage

V ₂ ‧‧‧Set voltage value

S11 to S16‧‧‧ steps

S20 to S32‧‧‧ steps

1 is a flow chart of a frequency modulation method performed under the operating system of the present invention; and FIG. 2 is a block diagram of a power supply system applying the frequency modulation method performed by the operating system of the present invention; FIG. A frequency system block diagram of a frequency modulation method performed by the operating system of the present invention; FIG. 4 is a process flow diagram of another embodiment of the frequency modulation method performed by the operating system of the present invention; 5(A) and 5(B) are flowcharts of a process of a specific embodiment of the frequency modulation method performed by the operating system of the present invention; and FIG. 6 is a process executed by the operating system of the present invention The frequency modulation method is a timing diagram of phase adjustment with voltage level and operating frequency.

S11 to S13‧‧‧ steps

Claims (17)

A frequency modulation method performed under an operating system is applied to an information processing device having an embedded controller, a clock generator, a central processing unit, and a system bus, wherein the frequency of execution under the operating system The modulation method includes the following steps: (1) causing the information processing device to receive an overclocking control signal input by the user; and (2) causing the embedded controller to raise the central processor according to the overclocking control signal received by the information processing device And the voltage level of the bus bar of the system; and (3) causing the embedded controller to gradually increase the central processor according to the overclocking control signal received by the information processing device in a phased manner, and The operating frequency of the system bus. The frequency modulation method performed under the operating system according to the first aspect of the patent application, wherein before the step (1), the information processing device is configured to provide a user interface for setting the overclocking control signal. The frequency modulation method performed by the operating system, as described in claim 1, wherein the information processing device further includes an image processor, and in step (2), the embedded controller is further configured according to the The overclocking control signal received by the information processing device raises the voltage level of the image processor, and in step (3), the embedded controller sequentially causes the clock generator to selectively step through the phased manner. Increase the operating frequency of the image processor. The frequency of execution under the operating system as described in item 1 of the patent application scope The rate modulation method comprises the following steps: (4) when the information processing device receives the input of the down-conversion control signal, the shutdown signal, the restart signal, the sleep signal or the sleep signal, the clock generator is adjusted to decrease the The operating frequency of the central processing unit and the system bus; and (5) causing the embedded controller to downgrade the central processing after the operating frequency of the central processing unit and the system bus is reduced to a predetermined rating And the voltage level of the bus bar of the system. The frequency modulation method performed by the operating system, as described in claim 4, wherein the information processing device provides a user interface for setting and down-clocking control signals, shutdown signals, and restart signals. The input signal related to the sleep signal or the sleep signal, and the input signal is used to cause the clock generator to lower the operating frequency of the central processing unit and the system bus. The frequency modulation method performed by the operating system, as described in claim 5, wherein the information processing device includes an image processor, and the input signal repeats and causes the clock generator to lower the image. The working frequency of the processor, and in the step (5), the embedded controller repeats and causes the embedded controller to lower the voltage level of the image processor. The frequency modulation method performed by the operating system, as described in claim 4, wherein the information processing device provides a user interface for setting and down-clocking control signals, shutdown signals, and restart signals. Input signal related to sleep signal or sleep signal, and the input The incoming signal is that the embedded controller causes the clock generator to gradually reduce the operating frequency of the central processing unit and the system bus bar in a phased manner. The frequency modulation method performed by the operating system, as described in claim 7, wherein the information processing device includes an image processor, and the input signal is used to make the clock generator pass through the stage. The way to gradually reduce the operating frequency of the image processor. The frequency modulation method performed under the operating system as described in claim 4, wherein in the step of adjusting the operating frequency of the central processing unit and the system bus, the clock generator When the input signal received by the information processing device is a down-conversion control signal, a sleep signal or a sleep signal, the embedded controller causes the clock generator to lower the central processing unit and the system at a first rate of decrease The working frequency of the bus, and when the input signal received by the information processing device is a shutdown signal or a restart signal, the embedded controller causes the clock generator to lower the center at a second lowering speed The processor, and the operating frequency of the system bus. The frequency modulation method performed under the operating system, as described in claim 9, wherein the information processing device includes an image processor, and the embedded controller repeats and causes the clock generator to The one or second downshift speed reduces the operating frequency of the image processor. The frequency modulation method performed under the operating system as described in claim 9, wherein the embedded controller causes the clock generator to pass the phased manner at the first or second speed reduction speed Step down The central processor, and the operating frequency of the system bus. The frequency modulation method performed under the operating system, as described in claim 11, wherein the information processing device further includes an image processor, and the embedded controller repeats and causes the clock generator to pass through the stage. The mode reduces the operating frequency of the image processor at the first or second rate of decrease. The frequency modulation method performed under the operating system according to claim 9 is wherein the first speed reduction speed is greater than the second speed reduction speed. A frequency modulation method performed under an operating system is applied to an information processing device having an embedded controller, a clock generator, a central processing unit, a system bus, and an image processor, wherein the operating system The frequency modulation method performed includes the following steps: (1) causing the information processing device to receive the overclocking control signal input by the user; and (2) causing the embedded controller to increase according to the overclocking control signal received by the information processing device. The central processing unit, the system bus, and the voltage level of the image processor; and (3) causing the embedded controller to raise the center of the clock generator according to the overclocking control signal received by the information processing device The operating frequency of the processor and the bus of the system, and the embedded controller together causes the clock generator to selectively increase the operating frequency of the image processor in a stepwise manner. A frequency modulation method performed under an operating system is applied to The information processing device has an embedded controller, a clock generator, a central processing unit, and a system bus, wherein the information processing device provides a user interface for setting and down-clocking control signals, shutdown signals, Resetting the input signal related to the signal, the sleep signal or the sleep signal, wherein the frequency modulation method performed under the operating system comprises the following steps: (1) causing the information processing device to receive the overclocking control signal input by the user; (2) Causing the embedded controller to raise the voltage level of the central processing unit and the bus bar of the system according to the overclocking control signal received by the information processing device; (3) causing the embedded controller to receive the overclocking according to the information processing device The control signal causes the clock generator to increase the operating frequency of the central processing unit and the system bus; and (4) receiving, by the information processing device, the down control signal, the shutdown signal, the restart signal, When the sleep signal or the sleep signal is input, the clock generator is caused to lower the operating frequency of the central processing unit and the system bus; and (5) The processor and the operating frequency of the system bus to a predetermined nominal cut, enabling the cut embedded controller of the central processing unit and the voltage level of the bus system. A frequency modulation method performed under an operating system is applied to an information processing device having an embedded controller, a clock generator, a central processing unit, and a system bus, wherein the information processing device provides a The user interface is configured to set an input signal related to the down-conversion control signal, the shutdown signal, the restart signal, the sleep signal, or the sleep signal, and the frequency modulation method performed under the operating system includes the following steps: (1) The information processing device receives the overclocking control signal input by the user; (2) causing the embedded controller to raise the voltage level of the central processing unit and the system bus bar according to the overclocking control signal received by the information processing device; (3) causing the embedded controller to cause the clock generator to raise the operating frequency of the central processing unit and the system bus according to the overclocking control signal received by the information processing device; (4) receiving at the information processing device When the down-conversion control signal, the shutdown signal, the restart signal, the sleep signal or the sleep signal is input, the clock generator gradually steps down the CPU and the system bus in a phased manner. Operating frequency; and (5) after the operating frequency of the central processor and the system bus is reduced to a predetermined rating, the embedded controller is downgraded Central processor and a voltage level of the bus system. A frequency modulation method performed under an operating system is applied to an information processing device having an embedded controller, a clock generator, a central processing unit, and a system bus, wherein the frequency of execution under the operating system The modulation method includes the following steps: (1) causing the information processing device to receive the overclocking control input by the user (2) causing the embedded controller to raise the voltage level of the central processing unit and the bus bar of the system according to the overclocking control signal received by the information processing device; (3) causing the embedded controller to rely on the information The overclocking control signal received by the processing device causes the clock generator to increase the operating frequency of the central processing unit and the system bus; (4) when the information processing device receives the frequency down control signal, the sleep signal or the sleep signal When inputting, the embedded controller causes the clock generator to lower the operating frequency of the central processing unit and the system bus at the first speed reduction speed, and when the information processing device receives the shutdown signal, or restarts When the signal is input, the embedded controller causes the clock generator to lower the operating frequency of the central processing unit and the system bus at a second lowering speed; and (5) the central processing unit and the system After the operating frequency of the bus is reduced to a predetermined rating, the embedded controller is caused to lower the voltage level of the central processing unit and the system bus.