TWI421568B - Active array substrate, liquid crystal dislay panel and method for manufacturing the liquid crystal dislay panel - Google Patents

Description

Active array substrate, liquid crystal display panel and method of manufacturing liquid crystal display panel

The present invention relates to an active array substrate, a liquid crystal display panel, and a method of manufacturing the liquid crystal display panel. In particular, it relates to a test circuit applied to an active array substrate, which can improve test capability and reduce the probability of misjudgment during testing.

In recent years, flat-panel displays have been widely used because of their advantages of being light, thin, and short. Generally, the flat panel display has an active array substrate, and the active array substrate includes a plurality of active components presenting an array array, and the active component is electrically connected to the corresponding data lines, the scan lines, and the pixel electrodes.

When the image is to be displayed, the data signal is transmitted to each active component through the data line, and then the active signal is transmitted to the active component by the scan line to enable the active component to transmit a column of data signals to a column of pixel electrodes, and then the signal is turned off. After the active component is listed, the next active component of the active component is turned on, and the process is repeated until all the columns are addressed.

However, if some or a certain set of active components are not enabled due to the problem of line defects or unstable components, it will cause problems in signal transmission, resulting in failure to display properly. Therefore, in the manufacturing process of flat panel displays. Testing or repairing a line or component results in an increase in throughput and a reduction in overall process time.

In view of the foregoing, it is an object of the present invention to provide an active array substrate that can improve test capability and reduce the chance of misjudgment during testing.

The active array substrate provided by the invention can test short circuit and open circuit of the line in the display area of the active array substrate.

The liquid crystal display panel provided by the invention has the above active array substrate, and can test short circuit and open circuit of the line in the display area of the active array substrate.

A method for manufacturing a liquid crystal display panel provided by the present invention, the method comprising: providing an array of mother boards having test circuits independent of each other and an outer test circuit, which may be respectively before and after the step of forming a liquid crystal layer The second test procedure achieves an independent and complete test purpose to confirm whether the liquid crystal display panel has a short circuit and an open circuit in the display area.

The above and other objects, features and advantages of the present invention will become more <RTIgt;

Figure 1 is an array mother board of the present invention. 2A-2D is a method of manufacturing a liquid crystal display panel of the present invention.

As shown in FIG. 1, the array mother board 10 includes a substrate 100, a pixel array 101, a first test module T1, and a second test module T2. The pixel array 101 is disposed on the substrate 100, and the pixel array 101 includes a plurality of wires and a plurality of pixel units 11. The wires include a plurality of scan lines 12 and a plurality of data lines 13, and the pixel unit 11 includes an active element 15 and a pixel electrode. 14. Each active component 15 is electrically connected to the corresponding scan line 12, data line 13, and pixel electrode 14.

The first test module T1 is electrically connected to the scan lines 12, and the first test module T1 includes an inner test circuit 130 and an outer test circuit 140. It should be particularly noted that the outer test circuit 140 is an internal test circuit 130. Independently set and directly connected to the scan line 12 by the external test branch line 141. The substrate 100 has a dicing line L at a position between the inner test circuit 130 and the outer test circuit 140 for subsequent cutting of the active array substrate.

The second test module T2 is electrically connected to the data lines 13. The second test module T2 includes an inner test circuit 110 and an outer test circuit 120. It should be particularly noted that the outer test circuit 120 is followed by the test circuit 110. Independently set and directly connected to the data line 13 by the external test branch line 121. The substrate 100 has a dicing line L at a position between the inner test circuit 110 and the outer test circuit 120 for subsequent cutting of the active array substrate.

Please refer to FIGS. 2A to 2D for explaining the method of manufacturing a liquid crystal display panel of the present invention.

As shown in Fig. 2A, an array of mother boards 10 is provided, and the configuration of the array mother board 10 is as described above. At least one external test signal is transmitted to the pixel array 101 by the external test circuit 120 and/or the external test circuit 140 to execute a first test program, and the operation of the first test program will be described in detail later.

Next, as shown in Fig. 2B, the array mother substrate 10 is diced to detach at least a portion of the outer test circuits 120, 140 from the pixel array 101 to form the active array substrate 10'. The array mother board 10 has a cutting line L located in the inner test circuit 110 (130) and the outer test circuit. Between 120 (140), wherein the step of cutting the array mother board 10 to disengage at least a portion of the outer test circuit 120 (140) from the pixel array 101 includes cutting the array mother board 10 along the cutting line L. The active array substrate 10 includes a substrate 100, a pixel array 101, inner test circuits 130, 110, and outer test branch lines 141, 121. The pixel array 101 is disposed on the substrate 100, and the pixel array includes a plurality of wires and a plurality of pixel units 11. The wires include a plurality of scan lines 12 and a plurality of data lines 13. The pixel unit 11 includes an active element 15 and a pixel electrode 14, each active element 15 being electrically connected to a corresponding scan line 12, data line 13 and pixel electrode 14. Sexual connection. The inner test circuits 110 and 130 are electrically connected to the plurality of data lines 13 and the plurality of scan lines 12, respectively. The outer test branch lines 141, 121 are directly connected to the complex scan line 12 and the complex data line 13, respectively. It should be noted that the external test branch lines 141, 121 are separately provided with the inner test circuits 110, 130 and are respectively connected to the corresponding wires, so when the first test program or the second test program is executed, the inner test is performed. The circuits 110, 130 and the external test circuits 120, 140 do not interact with each other and operate independently, thereby reducing the probability of misjudgment during testing.

Then, as shown in Fig. 2C, a liquid crystal layer 30 is formed between the active array substrate 10' and the pair of substrates 20, wherein at least a portion of the inner test circuit 130 is exposed.

Finally, at least one internal test signal is transmitted to the pixel array 101 by the internal test circuit 130 to execute a second test program, and the operation of the second test program will be described in detail later. As a result, as shown in FIG. 2D, the liquid crystal display panel 1 is completed.

Figure 3A is a first embodiment of the first test module of the present invention. 3B and 3C are respectively a first example and a second example cross-sectional view of the first test module of the present invention taken along section line A-A'.

The first test module T1 includes an inner test circuit 130 and an outer test circuit 140.

The external test circuit 140 includes at least one external test signal line 142 and an external test signal module 1401. The external test signal line 142 is directly connected to the portion of the plurality of scan lines 12 by the external test branch line 141. The external test signal module 1401 is electrically connected to the at least one external test signal line 142. After the step of cutting the array mother substrate 10, the outer test branch line 141 remains in the active array substrate 10'.

When the first test procedure is performed, the external test signal is sequentially transmitted to the scan line 12 via the external test signal module 1401, the external test signal line 142, and the outer test branch line 141 to test whether each component in the pixel array 101 is working normally. Since the external test circuit 140 is independently provided from the inner test circuit 130, it is not affected by the inner test circuit 130 when the first test program is performed, that is, if the inner test circuit 130 has flaws or component failures. It will not affect the operation of the first test program.

The inner test circuit 130 includes an inner test gate line 131, an inner test gate signal module 1301, a plurality of test switches 135, a plurality of inner test signal lines 132, and an inner test signal module 1302. The inner test gate signal module 1301 is connected to the inner test gate line 131. The test switch 135 is exemplified by an N-type thin film transistor or a P-type thin film transistor. Test switch 135 has a brake The gate 135a of the test switch 135 is electrically connected to the inner test gate line 131, and the drains 135c of the test switches 135 are respectively connected to the scan line 12, The inner test signal line 132 is respectively connected to the source 135b of the test switches 135 by the inner test branch line 133. The inner test gate signal module 1301 includes a gate signal pad 1301a and a turn-off signal pad 1301b. The inner test signal line 132 is connected to the inner test signal module 1302. However, the internal test signal module 1302 and the external test signal module 1401 can be integrated into a single signal source according to the designer's needs, that is, the inner test signal line 132 and the outer test signal line 142 are connected to the same signal. The source, in other words, the inner test circuit 130 is connected in parallel with the outer test branch line 141.

During the second test procedure, the gate signal pad 1301a transmits an enable signal to the test switches 135. The voltage of the turn-on signal is about 20 volts to 30 volts, and then or simultaneously by the internal test signal mode. The group 1302, the inner test signal line 132, the inner test branch line 133, and the test switch 135 transmit the inner test signal to the scan line 12 to test whether the components in the pixel array 101 are functioning properly. Then, the shutdown signal pad 1301b transmits a shutdown signal to the test switches 135, and the voltage of the shutdown signal is about -5 volts to -10 volts.

By the first and second test procedures before and after the step of forming the liquid crystal layer, it is possible to further ensure whether the operation of each element and the line in the pixel array 101 is normal.

Please refer to FIG. 3B. FIG. 3B is a first example of the first test module T1 of the present invention taken along the section line A-A' of FIG. 3A. External test signal The line 142 and the inner test gate line 131 can be simultaneously formed on the substrate 100 with the same conductive material. The insulating layer 151 is formed on the outer test signal line 142, the inner test gate line 131, and the substrate 100. The inner test signal line 132 and the outer test branch line 141 are formed on the insulating layer 151 with the same conductive material, and then the protective layer 152 is completely formed. Next, the partial protective layer 152 and the partial insulating layer 151 are removed to form the contact hole h1. The outer test signal line 142 and the outer test branch line 141 are respectively exposed, and finally, the conductive layer 150 is formed on the protective layer 152 and the contact holes h1 and h2 for electrically connecting the outer test signal line 142 and the outer test branch line 141. . The material of the conductive layer 150 is exemplified by a transparent conductive material such as indium oxide or zinc oxide, but is not limited.

Please refer to FIG. 3C. FIG. 3C is a second example of the first test module T1 of the present invention taken along the section line A-A' of FIG. 3A. The outer test signal line 142 and the inner test gate line 131 can be simultaneously formed on the substrate 100 with the same conductive material. The insulating layer 151 is formed on the outer test signal line 142, the inner test gate line 131, and the substrate 100, and then removed. The portion of the insulating layer 151 is exposed to form a contact hole h3 to expose a portion of the outer test signal line 142. Then, the inner test signal line 132 and the outer test branch line 141 are selectively formed on the insulating layer 151, wherein the outer test branch line 141 is The inner test signal line 132 is not connected to the outer test branch line 141 and the outer test signal line 142 by the contact hole h3. Finally, the protective layer 152 is completely formed.

Figure 4 is a second embodiment of the first test module of the present invention. Different from the first embodiment of the first test module, the inner test signal line and the outer The test signal lines are divided into two groups of parity.

The outer test circuit 140 includes an outer test odd signal line 143, an outer test even signal line 144, and an outer test odd signal pad 1402 and an outer test even signal pad 1403.

When the first test procedure is performed, the external test signal includes an external test odd signal and an external test even signal. The external test odd signal is sequentially transmitted to the scan line 12a via the external test odd signal pad 1402, the outer test odd signal line 143, and the outer test odd branch line 141a to test whether the components in the pixel array 101 are operating normally. The external test even signal is sequentially transmitted to the scan line 12b via the external test even signal pad 1403, the outer test even signal line 144, and the outer test even branch line 141b to test whether the components in the pixel array 101 are operating normally.

Since the external test circuit 140 is independently provided from the inner test circuit 130, it is not affected by the inner test circuit 130 when the first test program is performed, that is, if the inner test circuit 130 has flaws or component failures. It will not affect the operation of the first test program.

The inner test circuit 130 includes an inner test gate line 131, an inner test gate signal module 1301, a plurality of test switches 135, a plurality of inner test signal lines, and an inner test signal module. The inner test gate signal module 1301 is connected to the inner test gate line 131. The test switch 135 has a gate 135a, a source 135b and a drain 135c. The gate 135a of the test switch 135 is connected to the inner test gate line 131. Electrically connected, the drains 135c of the test switches 135 are respectively connected to the scan lines 12a, 12b. The internal test signal line includes an internal test odd signal line 134 and an inner test even signal line 136, respectively The test odd branch line 133a and the inner test even branch line 133b are connected to the source 135b of the test switches 135. The inner test gate signal module 1301 includes a gate signal pad 1301a and a turn-off signal pad 1301b. The inner test signal line 132 is connected to the inner test signal module. The inner test signal module includes an inner test odd signal pad 1303 and an inner test even signal pad 1304. The inner test odd signal pad 1303 is connected to the inner test odd signal line 134, and the inner test even signal pad 1304 is connected to the inner test even signal line 136, wherein the inner test odd branch line 133a and the inner test even branch line 133b are interlaced. arrangement.

During the second test procedure, the gate signal pad 1301a transmits an enable signal to the test switches 135. The voltage of the turn-on signal is about 20 volts to 30 volts, and then the internal signal is tested by the internal signal. The pad 1303, the inner test odd signal line 134, the inner test odd branch line 133a, and the test switch 135 transmit the inner test odd signal to the scan line 12a to test whether the components of the corresponding odd columns in the pixel array 101 are functioning normally. Then, the shutdown signal pad 1301b transmits a shutdown signal to the test switches 135, and the voltage of the shutdown signal is about -5 volts to -10 volts. Next, the gate signal pad 1301a transmits an enable signal to the test switches 135. The voltage of the turn-on signal is about 20 volts to 30 volts, and then the inner test pad 1304 is tested by the inner test. The even signal line 136, the inner test even branch line 133b, and the test switch 135 transmit the inner test even signal to the scan line 12b to test whether the components of the corresponding even columns in the pixel array 101 are operating normally. Then, the shutdown signal pad 1301b transmits a shutdown signal to the test switches 135, and the voltage of the shutdown signal is about -5 volts to -10 volts.

By the first and second test procedures before and after the step of forming the liquid crystal layer, it is possible to further ensure whether the operation of each element and the line in the pixel array 101 is normal.

The second test module of the present invention is constructed in accordance with the first embodiment of the first test module of the present invention. The difference is that only the second test module is connected to the data line 13, and the remaining operating principles and test methods are The first embodiment of the first test module of the present invention is similar and will not be described herein.

Figure 5 is another example of the second test module of the present invention. As shown in FIG. 5, the second test module T2 includes an inner test circuit 110 and an outer test circuit 120.

The external test circuit 120 includes an external test red signal line 124, an external test green signal line 126, an external test blue signal line 128, an external test signal module, an external test red branch line 122R, an external test green branch line 122G, and an external test blue. Color branch line 122B. The external test signal module includes an external test red signal pad 1201R, an external test green signal pad 1201G, and an external test blue signal pad 1201B. The external test red signal pad 1201R is connected to the external test red signal line 124, and the external test green signal pad 1201G Connected to the external test green signal line 126, the external test blue signal pad 1201B is connected to the external test blue signal line 128, wherein the external test red signal line 124, the external test green signal line 126 and the external The data lines 13R, 13G, and 13B connected to the test blue signal line 128 are sequentially arranged.

When performing another first test procedure, the external test signal includes an external test red signal, an external test green signal, and an external test blue signal. The external test red signal is sequentially tested by external test red signal pad 1201R, external test The red signal line 124 and the outer test red branch line 122R are transmitted to the data line 13R to test whether the components of the corresponding red line in the pixel array 101 are operating normally. The external test green signal is sequentially transmitted to the data line 13G via the external test green signal pad 1201G, the outer test green signal line 126, and the outer test green branch line 122G to test whether the components of the corresponding green line in the pixel array 101 are normal. Operation. The external test blue signal is sequentially transmitted to the data line 13B via the external test blue signal pad 1201B, the outer test blue signal line 128, and the outer test blue branch line 122B to test the corresponding green line in the pixel array 101. Whether each component is working properly.

Since the external test circuit 120 is independently disposed from the inner test circuit 110, it is not affected by the inner test circuit 110 when performing the other first test procedure, that is, if the inner test circuit 110 has flaws or When the component is faulty, it will not affect the operation of this other first test program.

The inner test circuit 110 includes an inner test gate line 112, an inner test gate signal module 1101, a plurality of test switches 111, a plurality of inner test signal lines, and an inner test signal module. The inner test gate signal module 1101 is connected to the inner test gate line 112. The test switch 111 has a gate 111a, a source 111b and a drain 111c. The gate 111a of the test switch 111 is connected to the inner test gate 112. Electrically connected, the drains 111c of the test switches 111 are respectively connected to the data lines 13R, 13G and 13B. The inner test signal line includes an inner test red signal line 114, an inner test green signal line 116, and an inner test blue signal line 118, respectively, by internally testing the red branch line 133R, the inner test green branch line 133G, and the inner test blue branch line. 133B is connected to the source 111b of the test switches 111. Internal test The structure and operation principle of the gate signal module 1101 are similar to those of the test gate signal module 1301 in the first test module T1, and will not be described here. The internal test signal module includes an inner test red signal pad 1102R, an inner test green signal pad 1102G, and an inner test blue signal pad 1102B. The inner test red signal pad 1102R is connected to the inner test red signal line 114, the inner test green signal pad 1102G is connected to the inner test green signal line 116, and the inner test blue signal pad 1102B is connected to the inner test blue signal line 118. The inner test red branch line 133R, the inner test green branch line 133G, and the inner test blue branch line 133B are sequentially staggered.

During the second test procedure, the internal test gate signal module 1101 transmits an enable signal to the test switches 111. The voltage of the turn-on signal is about 20 volts to 30 volts, and then simultaneously The inner test red signal pad 1102R, the inner test red signal line 114, the inner test red branch line 133R, and the test switch 111 transmit the inner test red signal to the data line 13R to test each of the corresponding red lines in the pixel array 101. Whether the component is working properly. Then, the internal test gate signal module 1101 transmits a shutdown signal to the test switches 111, and the voltage of the shutdown signal is about -5 volts to -10 volts. Next, the internal test gate signal module 1101 transmits an enable signal to the test switches 111. The voltage of the turn-on signal is about 20 volts to 30 volts, and then the green signal pad 1102G is simultaneously tested by the inner test. The inner test green signal line 116, the inner test green branch line 133G, and the test switch 111 transmit the inner test green signal to the data line 13G to test whether the components of the corresponding green lines in the pixel array 101 are operating normally. Then, the internal test gate signal module 1101 transmits A turn-off signal is applied to the test switches 111, and the voltage of the turn-off signal is about -5 volts to -10 volts. Then, the internal test gate signal module 1101 transmits an open signal to the test switches 111. The voltage of the turn-on signal is about 20 volts to 30 volts, and then the blue test is simultaneously performed. The signal pad 1102B, the inner test blue signal line 118, the inner test blue branch line 133B, and the test switch 111 transmit the inner test blue signal to the data line 13B to test each of the corresponding blue lines in the pixel array 101. Whether the component is working properly. Then, the internal test gate signal module 1101 transmits a shutdown signal to the test switches 111, and the voltage of the shutdown signal is about -5 volts to -10 volts.

By means of the other first and second test procedures before and after the step of forming the liquid crystal layer, it is possible to further ensure whether the operations of the respective elements of the corresponding red, green and blue lines and the lines in the pixel array 101 are normal.

The switching element is exemplified by a thin film transistor, and the material of each of the wires is exemplified by a metal conductive material, and the opposite substrate is exemplified by a color filter substrate, which is familiar to those skilled in the art.

Because the internal and external test circuits of the present invention are separately set, the test capability can be improved, the probability of misjudgment during test can be reduced, and the short circuit or open circuit in the display area can be tested, and part of the test traces are pulled out to the cutting line L to complete the test. After the program, the external test circuit and some of its traces will be cut off.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of protection of the present invention is defined by the scope of the appended patent application. quasi.

1‧‧‧LCD panel

10‧‧‧Array Motherboard

10'‧‧‧Active array substrate

100‧‧‧Base

101‧‧‧ pixel array

11‧‧‧ pixel unit

110‧‧‧Intest circuit

Test red signal pad in 1102R‧‧

Test green signal pad in 1102G‧‧

Test blue signal pad in 1102B‧‧

111‧‧‧Test switch

111a‧‧‧ gate

111b‧‧‧ source

111c‧‧‧Bungee

Test gate line in 112‧‧

Test the red signal line in 114‧‧

Test the green signal line in 116‧‧

Test the blue signal line in 118‧‧

12, 12a, 12b‧‧‧ scan lines

120‧‧‧External test circuit

1201R‧‧‧External test red signal pad

1201G‧‧‧External test green signal pad

1201B‧‧‧External test blue signal pad

121‧‧‧External test branch line

122R‧‧‧ outside test red branch line

122G‧‧‧ outside test green branch line

122B‧‧‧External test blue branch line

124‧‧‧External test red signal line

126‧‧‧External test green signal line

128‧‧‧External test blue signal line

13, 13R, 13G, 13B‧‧‧ data lines

130‧‧‧Test circuit

Test gate signal module in 1301‧‧

1301a‧‧‧Gate signal pad

1301b‧‧‧Close signal pad

1302‧‧‧Test signal module

Test gate line in 131‧‧

132‧‧‧Test signal line

Test branch line within 133‧‧

Test the odd branch line in 133a‧‧

Test even branch line in 133b‧‧

Test the odd line in 134‧‧

135‧‧‧Test switch

135a‧‧‧ gate

135b‧‧‧ source

135c‧‧‧汲

Testing the signal line in 136‧‧

14‧‧‧ pixel electrodes

140‧‧‧External test circuit

1401‧‧‧External test signal module

1402‧‧‧External test odd signal pad

1403‧‧‧External test even signal pad

141‧‧‧External test branch line

141a‧‧‧External test odd branch line

141b‧‧‧External test even branch line

142‧‧‧External test signal line

143‧‧‧External test odd signal line

144‧‧‧External test even signal line

15‧‧‧Active components

150‧‧‧ Conductive layer

151‧‧‧Insulation

152‧‧‧Protective layer

20‧‧‧ opposite substrate

30‧‧‧Liquid layer

1 is an array mother board of the present invention; 2A-2D is a method for manufacturing a liquid crystal display panel of the present invention; FIG. 3A is a first embodiment of the first test module of the present invention; 3C is a first example and a second example cross-sectional view of the first test module of the present invention taken along a section line A-A'; FIG. 4 is a second embodiment of the first test module of the present invention. And Figure 5 is another example of the second test module of the present invention.

10‧‧‧Array Motherboard

100‧‧‧Base

101‧‧‧ pixel array

11‧‧‧ pixel unit

110‧‧‧Intest circuit

12‧‧‧ scan line

120‧‧‧External test circuit

121‧‧‧External test branch line

13‧‧‧Information line

130‧‧‧Test circuit

14‧‧‧ pixel electrodes

140‧‧‧External test circuit

141‧‧‧External test branch line

Claims (16)

An active array substrate includes: a substrate; a pixel array disposed on the substrate, the pixel array includes a plurality of wires; and an inner test circuit electrically connected to a portion of the plurality of wires, the inner test circuit The method includes: an inner test gate line; an inner test gate signal module connected to the inner test gate line; a plurality of test switches electrically connected to the inner test gate line, and the test switches are Correspondingly connected to one of the plurality of wires; at least one inner test signal line connected to the test switches; and an inner test signal module electrically connected to the inner test signal line; and a plurality of external test branch lines Directly connected to the drains of the test switches respectively; wherein the inner test circuit is connected in parallel with the outer test branch line, wherein the number of the plurality of test switches of the inner test circuit is equal to the number of the plurality of test branch lines, One of the plurality of test switches of the inner test circuit and one of the plurality of test branch lines are connected to the same wire. The active array substrate according to claim 1, wherein the wires comprise a plurality of scan lines and a plurality of data lines, and the inner test circuit is electrically connected to the scan lines. The active array substrate of claim 2, wherein the inner test signal line comprises an inner test odd signal line and an inner test even signal line, and the inner test signal module comprises: an inner test odd signal pad, Connected to the inner test odd signal line; and an inner test even signal pad connected to the inner test even signal line. The active array substrate according to claim 1, wherein the wires comprise a plurality of scan lines and a plurality of data lines, and the inner test circuit is electrically connected to the data lines. The active array substrate of claim 4, wherein the internal test signal lines comprise an inner test red signal line, an inner test green signal line, and an inner test blue signal line, the inner test signal module Including: one test red signal pad, connected with the inner test red signal line; one inner test green signal pad, connected with the inner test green signal line And an inner test blue signal pad connected to the inner test blue signal line, wherein the inner test red signal line, the inner test green signal line, and the inner test blue signal line are respectively connected The test open relationship is arranged in order. The active array substrate of claim 1, further comprising: another inner test circuit disposed on the substrate and electrically connected to another portion of the plurality of wires; and an external test branch a wire directly connected to the other portion of the plurality of wires. The active array substrate of claim 6, wherein the other inner test circuit is in parallel with the other outer test branch line. A liquid crystal display panel comprising: the active array substrate according to any one of claims 1 to 7; a pair of substrates; and a liquid crystal layer disposed on the active array substrate and the opposite substrate between. A method of manufacturing a liquid crystal display panel, comprising: Providing an array of mother boards, the array mother board includes: a substrate; a pixel array disposed on the substrate, the pixel array includes a plurality of wires; and a first test module disposed on the substrate, and the The first test module includes: an inner test circuit electrically connected to one of the plurality of wires, the inner test circuit comprising: an inner test gate line; and an inner test gate signal a module connected to the inner test gate line; a plurality of test switches electrically connected to the inner test gate line, wherein the drains of the test open relationships are respectively connected with one of the plurality of wires of the plurality of wires; The signal lines are respectively connected to the test switches; and an inner test signal module is electrically connected to the inner test signal lines; and the inner test gate signal module transmits at least one off signal to the tests And an external test circuit comprising a plurality of external test branch lines directly connected to the drains of the test switches; wherein the inner test circuit is connected in parallel with the outer test branch line, wherein The number of the plurality of test switch circuit within the test And corresponding to the number of the plurality of test branch lines, one of the plurality of test switches of the inner test circuit and one of the plurality of test branch lines are connected to the same wire; and the outer test circuit transmits at least one external test signal to the a pixel array to perform a first test procedure; cutting the array mother board to remove at least a portion of the external test circuit from the pixel array to form an active array substrate; forming a liquid crystal layer on the active array substrate and a pair of directions Between the substrates; and transmitting at least one internal test signal to the pixel array by the internal test circuit to perform a second test procedure. The method of claim 9, wherein the array mother board has a cutting line between the inner test circuit and the outer test circuit, wherein the array mother board is cut to at least a portion of the outer test circuit The step of disengaging the pixel array includes cutting the array master along the cutting line. The method of claim 9, wherein the inner test gate signal module comprises a gate signal pad and a turn signal pad, and the at least one off signal is transmitted to the test by the off signal pad. The switch, the voltage of the off signal is about -5 volts to -10 volts. The method of claim 9, wherein the internal test The test gate signal module includes a gate signal pad. The method further includes transmitting an open signal to the test switches via the gate signal pad. The voltage of the turn-on signal is about 20 volts to 30 volts. The method of claim 9, wherein the wires comprise a plurality of scan lines and a plurality of data lines, wherein the inner test circuit is electrically connected to the scan lines, and the inner test signal lines comprise an inner test chip. The signal line and the inner test signal line, the inner test signal module includes: an inner test odd signal pad connected to the inner test odd signal line; and an even test odd signal pad connected to the inner test even signal line The at least one internal test signal includes at least one inner test odd signal and at least one inner test even signal, and the at least one inner test odd signal is transmitted to the pixel array by the inner test odd signal line, the at least one inner The test even signal is transmitted to the pixel array by the internal test even signal line. The method of claim 9, wherein the wires comprise a plurality of scan lines and a plurality of data lines, wherein the inner test circuit is electrically connected to the data lines, wherein the inner test signal lines comprise an internal test The red signal line, the inner test green signal line and the inner test blue signal line, the inner test signal module includes: an inner test red signal pad, connected with the inner test red signal line a green signal pad is connected to the inner test green signal line; and an inner blue signal pad is connected to the inner test blue signal line; wherein the at least one inner test signal includes at least one inner test red a signal, at least one internal test green signal, and at least one internal test blue signal, wherein the at least one internal test red signal is transmitted to the pixel array by the internal test red signal line, wherein the at least one internal test green signal is The inner test green signal line is transmitted to the pixel array, and the at least one inner test blue signal is transmitted to the pixel array by the inner test blue signal line. The method of claim 9, wherein the external test circuit comprises: at least one external test signal line directly connected to the portion of the plurality of wires; and an external test signal module, and the at least one outer circuit The test signal line is electrically connected; wherein the wires comprise a plurality of scan lines and a plurality of data lines, the external test circuit is electrically connected to the scan lines, and the at least one external test signal line includes an external test odd signal line and a Externally testing the even signal line, the external test signal module includes: an external test odd signal pad, connected to the external test odd signal line; And an external test even signal pad connected to the external test even signal line, wherein the at least one external test signal includes at least one external test odd signal and at least one external test even signal, wherein the at least one external test odd signal is by the The external test odd signal line is transmitted to the pixel array, and the at least one external test even signal is transmitted to the pixel array by the external test even signal line. The method of claim 9, wherein the external test circuit comprises: at least one external test signal line connected to the test switches; and an external test signal module, and the at least one external test signal line And the plurality of scan lines and the plurality of data lines, wherein the external test circuit is electrically connected to the data lines, wherein the outer test signal lines comprise an external test red signal line and an external test green signal And an external test blue signal line, the external test signal module includes: an external test red signal pad connected to the external test red signal line; an external test green signal pad connected to the external test green signal line; And an external test blue signal pad, connected to the external test blue signal line The at least one external test signal includes at least one external test red signal, at least one external test green signal, and at least one external test blue signal, and the at least one external test red signal is transmitted to the external test red signal line to In the pixel array, the at least one external test green signal is transmitted to the pixel array by the external test green signal line, and the at least one external test blue signal is transmitted to the picture by the external test blue signal line. Prime array.