TWI420643B - Chip having tsv's, its forming method and a chip stack utilizing the chip - Google Patents

Description

Wafer structure with germanium perforation, method of forming, and stacked structure using the same

The present invention relates to semiconductor devices, and more particularly to a wafer structure having germanium perforations, a method of forming the same, and a stacked structure using the wafer structure.

In the semiconductor industry, the production of semiconductor package structures is mainly divided into three stages: wafer fabrication, wafer structure formation, and wafer structure packaging. The formation of the wafer structure is completed by a blank wafer through steps of circuit design, circuit fabrication, and wafer dicing. The electrical connection between the wafer structure and other components is usually done by wire bonding or bump bonding. The development of electronic products towards thin and light and high-density integrated circuits has become a trend today. In order to increase or expand the functionality or memory capacity of a product, multiple wafer structures are typically stacked within a package configuration. In order to electrically connect two or more stacked wafer structures, a wafer structure having bumps is typically used for flip chip bonding such that the height between the stacked wafer structures can be lower than the height between stacked wafer structures in a wire bonding manner. Generally, the bumps are formed on the active surface of the wafer structure and are made of solder, which will form a spherical shape during reflow, but the solder bumps may be diffused or thermally circulated during soldering or high temperature environments. The stress is accumulated and the fracture occurs, causing the electrical signal transmission to fail. In addition, since the bond between the wafer structure and the wafer structure is made of spherical solder bumps, it is difficult to achieve a fine pitch bump configuration, and it is also impossible to stack more wafer structures in a limited package thickness.

In order to solve the above problems, the main object of the present invention is to provide a wafer structure having a ruthenium perforation, thereby increasing the fixing strength of the columnar bumps and the characteristics of better solder nip to avoid the detachment or breakage of the bumps.

A second object of the present invention is to provide a wafer structure having a ruthenium perforation, which can prevent diffusion of solder on the active surface of the wafer, thereby achieving a solder joint fine pitch bump arrangement in the wafer stack gap to reduce manufacturing. cost.

Another object of the present invention is to provide a wafer structure having a ruthenium perforation that maintains the level of stacking of a plurality of wafer structures in a flip chip bond to achieve high quality and high density wafer stacking.

The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. The invention discloses a wafer structure having a crucible perforation, which mainly comprises a wafer body, two or more through holes and two or more columnar bumps. The wafer system has a first surface and a second surface. The through holes extend through the first surface to the second surface of the wafer body, each through hole having a first opening at the first surface, a second opening at the second surface, and a second opening a constriction between the first opening and the second opening, wherein the constriction is smaller than the first opening and smaller than the second opening. The columnar bumps are coupled to the wafer body in such a manner as to be aligned with the through holes, each of the columnar bumps having a first end surface and a second end surface, wherein the columnar bumps protrude from The first surface is configured to move the first end faces away from the corresponding first openings, and the columnar bumps extend through the corresponding recesses such that the second end faces are adjacent but not exceeding Corresponding to the second opening. The present invention also discloses the aforementioned method of forming a wafer structure.

The object of the present invention and solving the technical problems thereof can be further achieved by the following technical measures.

In the above-mentioned wafer structure, the through holes may be inclined from the first opening and the second opening to the side wall of the constriction, so that the through holes are hourglass-shaped.

In the foregoing wafer structure, a plurality of solders may be further included to be bonded to the first end faces.

In the aforementioned wafer structure, the second end face may be interposed between the constriction and the second opening.

In the foregoing wafer structure, the second end face can be aligned with the second opening.

In the foregoing wafer structure, the material of the columnar bumps may be metal formed by electroplating.

In the foregoing wafer structure, the first surface system can be an active surface.

The present invention also discloses a stacked structure using the foregoing wafer structure, which mainly includes a plurality of the foregoing wafer structures and a substrate, and the wafer structures are stacked on one of the substrates by means of the vertical alignment of the through holes. surface.

It can be seen from the above technical solutions that the wafer structure, the forming method and the stacked structure using the same have the following advantages and effects:

1. A special design of the through-wafer through hole and a specific snap-fit combination between the through-hole and the stud bump can be used as one of the technical means, so that the stud bump can be stuck to the wafer body, and the stud bump is added. The bond strength is better than the better solder bite to avoid the bumps from being detached or broken by the wafer body.

2. The formation position of the end faces of the columnar bumps on the wafer body can be used as one of the technical means to avoid diffusion and contamination of the solder on the active surface of the wafer, thereby achieving the use of solder-bonded micro-pitch in the wafer stack gap. Bump configuration to reduce manufacturing costs.

Third, the protruding portion of the stud bump can be used to define the gap between the stacked wafer structures as one of the technical means, so that the level of the wafer structure during stacking can be controlled, and the high-density wafer stack can be achieved and the better Package quality.

Fourth, a specific combination of a plurality of stacked wafer structures can be used as one of the technical means to form a uniform stress blocking interface between the plurality of wafer structures, thereby solving the difference in thermal expansion coefficient between the wafer structure and the packaging material. The problem of stress concentration generated.

The embodiments of the present invention will be described in detail below with reference to the accompanying drawings in which FIG. The components and combinations related to this case, the components shown in the figure are not drawn in proportion to the actual number, shape and size of the actual implementation. Some size ratios are proportional to other related sizes or have been exaggerated or simplified to provide clearer description of. The actual number, shape and size ratio of the implementation is an optional design, and the detailed component layout may be more complicated.

In accordance with a first embodiment of the present invention, a wafer structure having a crucible is illustrated in a cross-sectional view of FIG. The wafer structure 100 mainly includes a wafer body 110, two or more through holes 120, and two or more columnar bumps 130. The wafer body 110 has a first surface 111 and a second surface 112. Generally, the wafer body 110 is divided into a wafer (not shown), and the shape is a rectangular block or a square block, and the material is a semiconductor. In this embodiment, the first surface 111 can be an active surface, and the second surface 112 is a back surface. The term "active surface" as used herein refers to the surface used to form the desired integrated circuit components in a wafer process. Preferably, the second surface 112 is not thinned to maintain the thickness of the wafer body 110 at a wafer thickness after a general wafer dicing, about a centimeter level, for example, 0.1 to 10 centimeters (mm), and a common thickness. It is 1 cm.

Referring to FIG. 1 , the through holes 120 extend through the first surface 111 to the second surface 112 of the wafer body 110 . The formation of the through holes 120 can be accomplished by special mechanical drilling, laser or etching techniques with adjustable apertures. Each of the through holes 120 has a first opening 121 on the first surface 111 , a second opening 122 on the second surface 112 , and a constriction between the first opening 121 and the second opening 122 . 123, wherein the constriction 123 is smaller than the first opening 121 and smaller than the second opening 122 to form a latch structure for fixing the bump. The aperture size of the first opening 121 is equivalent to the area of the through hole 120 occupying the first surface 111. The aperture size of the second opening 122 corresponds to the through holes 120 occupying the second surface 112. The area. The first opening 121 can have the same aperture as the second opening 122. In this embodiment, the through holes 120 may be inclined by the first opening 121 and the second opening 122 to the sidewall of the cutout 123 such that the through holes 120 are hourglass-shaped. The sidewalls described above can be achieved by laser drilling with adjustable focal length or by an anisotropic etching.

Referring to FIG. 1 , the columnar bumps 130 are latched to the wafer body 110 by aligning the through holes 120 . The stud bumps 130 serve as electrodes for the wafer structure 100 to be externally stacked. Each of the stud bumps 130 has a first end surface 131 and a second end surface 132. The first end surface 131 and the second end surface 132 of each of the stud bumps 130 may be parallel to each other. The columnar bumps 130 protrude from the first surface 111 such that the first end faces 131 are away from the corresponding first openings 121. That is, the distance from the first end faces 131 of the stud bumps 130 to the first surface 111 of the wafer body 110 is the protruding height of the stud bumps 130. The columnar bumps 130 extend through the corresponding constrictions 123 such that the second end faces 132 are adjacent to each other but do not exceed the corresponding second openings 122. That is, the distance from the second end faces 132 of the stud bumps 130 to the first surface 111 of the wafer body 110 is the embedding depth of the stud bumps 130. In this embodiment, the second end surface 132 is interposed between the constricted portion 123 and the second opening 122, that is, formed as a concave electrode, and has the effect of accommodating solder to prevent diffusion contamination. The material of the columnar bumps 130 may be metal formed by electroplating. In this embodiment, the material of the columnar bumps 130 may be copper to play the role of gap maintenance and have a low cost advantage. Preferably, a sidewall of each of the through holes 120 is formed with a metal layer 124 which can be deposited to increase the adhesion to the pillar bumps 130 and serve as a plating seed layer. The metal layer 124 is optionally used for one of copper, nickel gold, tin, nickel palladium gold, tin lead, silver, and tin antimony.

As shown in FIG. 1 , in the embodiment, the wafer structure 100 may further include a plurality of solders 140 bonded to the first end faces 131 , so that there is a height difference from the first surface 111, which is not directly The wafer body 110 is contaminated. The wafer structure 100 can be externally electrically connected to a substrate 20 or another wafer structure 100 by the solders 140 (as shown in FIG. 3).

As can be seen from the above, the design of the recesses 123 can form a change in the aperture convergence in each of the through holes 120, so that the columnar bumps 130 formed in the through holes 120 can be engaged with the wafer body. 110. Further, in combination with the partial embedding of the columnar bumps 130, the bonding strength of the columnar bumps 130 is increased to provide better solder bite characteristics to prevent the bumps from falling off or breaking. Then, by forming the positions of the end faces 131 and 132 of the columnar bumps 130 on the wafer body 110, the diffusion of the solder 140 on the active surface of the wafer can be avoided, thereby achieving the use in the wafer stack gap. Solder-bonded micro pitch bumps are configured to reduce manufacturing costs. In addition, since the protruding portions of the columnar bumps 130 can maintain the level of the wafer structure 100 at the time of stacking, high quality and high density wafer stacking can be achieved.

The present invention further illustrates a method of forming the wafer structure 100 as exemplified in a cross-sectional view of the element in the method of FIGS. 2A to 2G.

First, as shown in FIG. 2A, the above-described wafer body 110 is provided. The wafer body 110 has a first surface 111 and a second surface 112. The wafer body 110 can be formed in a wafer.

Next, as shown in FIG. 2B , two or more through holes 120 are drilled for each of the wafer bodies 110 , and the through holes 120 extend through the first surface 111 to the second of the wafer body 110 . Surface 112. Each of the through holes 120 has a first opening 121 on the first surface 111 , a second opening 122 on the second surface 112 , and a constriction between the first opening 121 and the second opening 122 . 123, wherein the constriction 123 is smaller than the first opening 121 and smaller than the second opening 122. In this embodiment, the through holes 120 may be inclined by the first opening 121 and the second opening 122 to the sidewall of the narrowing 123, and the forming method may be selected from the cutting and scattering of the rotating laser light. Focusing on one of the cutting and etching deficiencies of laser light adjustment. After the through holes 120 are drilled, a metal layer 124 is formed on the sidewalls of the through holes 120 by electroless plating or vapor deposition, and a plating seed layer is formed on the first surface 111 of the wafer body 110. 125, in order to facilitate the subsequent electroplating process.

Thereafter, two or more columnar bumps 130 are disposed to be engaged with the wafer body 110 in such a manner as to be aligned with the through holes 120. For the details of the formation of the stud bumps 130, please refer to Figures 2C to 2F. In this embodiment, the step of disposing the columnar bumps 130 may include a double-sided plating step (as shown in FIG. 2D), and the second end faces 132 are formed in the double-sided plating step. Referring to FIGS. 2C and 2D, in the double-sided plating step, a first dry film 11 is covered and patterned, so that a second dry film 12 covers the second surface 112 and is Patterned. Specifically, as shown in FIG. 2C , the first dry film 11 is attached to the first surface 111 of the wafer body 110 after the through holes 120 are formed and before the second end faces 132 are formed. And covering the plating seed layer 125 and attaching the second dry film 12 to the second surface 112 of the wafer body 110. The first dry film 11 and the second dry film 12 are patterned by exposure development techniques. The patterned first dry film 11 has a plurality of holes 13 for exposing the first openings 121. The patterned second dry film 12 has a plurality of holes 14 for revealing the second openings 122. Double-sided plating is performed. Referring to FIG. 2D again, in the double-sided plating process, a plurality of plating metals 133 (that is, a portion constituting the columnar bumps 130) are formed in the through holes 120. In this embodiment, the plating metal 133 half fills the through holes 120, and particularly blocks the cutouts 123. The second end surfaces 132 formed are interposed between the cutouts 123 and Between the second openings 122.

In this embodiment, the step of disposing the columnar bumps 130 may include a single-sided plating step (as shown in FIG. 2E), and the first end faces 131 are formed in the single-sided plating step. This single-sided plating step is performed after the double-sided plating step. Referring to FIG. 2E, the first dry film 11 and the second dry film 12 are used in the single-sided plating step, and the photoresist 15 is pre-filled in the single-sided plating step. The holes 14 of the second dry film 12 are formed to cover the exposed second end faces 132. Referring to FIGS. 2D and 2E , electroplating is continuously performed on the electroplated metal 133 to form the stud bumps 130 and the first end faces 131 are formed. Therefore, the stud bumps 130 can protrude from The first surface 111. Thereafter, the first dry film 11 and the second dry film 12 are removed. As shown in FIG. 2F, after the removal, the pillar bumps 130 are protruded from the sidewalls of the first surface 111 and the second end surfaces 132 to complete the step of disposing the pillar bumps 130. In addition, after the step of disposing the columnar bumps 130, an etching step is further included to remove the plating seed layer 125 on the first surface 111 to obtain a structure as shown in FIG. 2G. In this embodiment, the method may further include a step of forming a plurality of solders 140 on the first end faces 131 (as shown in FIG. 1) as a medium for external electrical bonding.

The present invention also discloses a schematic cross-sectional view of the third embodiment using the stacked structure of the wafer structure 100 described above. The stacked structure mainly comprises a plurality of the aforementioned wafer structures 100 and a substrate 20. The substrate 20 has an upper surface 21 and an opposite lower surface 22, wherein the upper surface 21 is provided with a plurality of pads 23. The plurality of wafer structures 100 are stacked on the upper surface 21 of the substrate 20 by the vertical alignment of the through holes 120. Specifically, the lowermost wafer structure 100 is surface-bonded to the substrate 20 such that the first end faces 131 of the stud bumps 130 face the upper surface 21 of the substrate 20, using the solder. The pillar bumps 130 and the pads 23 are connected to electrically interconnect the underlying wafer structure 100 and the substrate 20 . The remaining wafer structures 100 stacked on the lower wafer structure 100 can be stacked in the same direction, and the solder 140 can reach the electrical interconnection between the wafer structures 100, wherein the solders 140 can be further filled with recesses. The second end faces 132. In this embodiment, the stacked structure may further include a glue body 30 formed on the upper surface 21 of the substrate 20 to seal the wafer structures 100. Preferably, the encapsulant 30 further fills the gap between the wafer structures 100 and is supported as a gap with the protrusions of the columnar bumps 130 to form a contour between the wafer structures 100. One of the technical means of the stress-blocking interface can solve the problem of stress concentration caused by the difference in thermal expansion coefficient between the wafer structure 100 and the encapsulating material (the encapsulant 30). In addition, the stacked configuration may further include a plurality of external terminals 40 bonded to the lower surface 22 of the substrate 20 for bonding the stacked structure to an external printed circuit board (not shown).

It can be seen from the above that the design of the columnar bumps 130 of the wafer structures 100 and the solders 140 of the wafer structure 100 located above during the stacking can be embedded in the through holes of the underlying wafer structure 100. Within 120, the upper and lower wafer structures 100 can be effectively joined and the degree of occlusion can be increased. Further, the protruding portions of the columnar bumps 130 can be used to define the gap between the stacked wafer structures 100, and the gap between the stacked wafer structures 100 can be maintained even when the wafers are bonded, so that the wafer can be controlled. The level of structure 100 is at the time of stacking and achieves high density wafer stacking with better package quality.

In accordance with a second embodiment of the present invention, another wafer structure having a crucible is illustrated in cross-section in FIG. The main components included in the wafer structure 200 are substantially the same as those of the wafer body 110, the through holes 120, and the stud bumps 130 of the first embodiment, and are denoted by the same reference numerals. Each of the through holes 120 has a first opening 121 at the first surface 111, a second opening 122 at the second surface 112, and a constriction 123. The constrictions 123 are located between the first openings 121 and the second openings 122 , wherein the constrictions 123 are smaller than the first openings 121 and the second openings 122 . The stud bumps 130 are latched to the wafer body 110 in such a manner as to be aligned with the through holes 120 . Each of the columnar bumps 130 has a first end surface 131 and a second end surface 132. The columnar bumps 130 protrude from the first surface 111, and the columnar bumps 130 extend through the corresponding portions. The shrinkage 123. In this embodiment, the second end surface 132 can be aligned with the second opening 122. Referring to FIG. 4 , the first end faces 131 of the columnar bumps 130 may be formed with a plurality of solders 140 for external electrical connection to a substrate 20 or another wafer structure 200 (eg, Figure 6 shows). Therefore, the fixing strength of the columnar bumps 130 and the better solder bite characteristics can be increased, and the diffusion contamination of the solder on the active surface of the wafer can be avoided, thereby achieving the use of solder bonding in the wafer stack gap. Pitch bump configuration.

The present invention further illustrates a method of forming the wafer structure 200 as exemplified in a cross-sectional view of the elements in the method of FIGS. 5A to 5G. The main steps involved in the method of forming the wafer structure 200 are substantially the same as the main steps of the first embodiment, such as providing a wafer body, drilling through holes, and providing stud bumps and the like.

First, referring to FIG. 5A, the wafer body 110 is provided. Next, referring to FIG. 5B, the through holes 120 are drilled. After the through holes 120 are drilled, a metal layer 124 and a plating seed layer 225 are formed. The metal layer 124 is formed in the through holes 120. In this embodiment, the plating seed layer 225 can be formed on the second surface 112 of the wafer body 110.

Thereafter, two or more columnar bumps 130 are disposed to be engaged with the wafer body 110 in such a manner as to be aligned with the through holes 120. For the manner in which the columnar bumps 130 are formed, please refer to FIGS. 5C to 5F. In this embodiment, the step of disposing the columnar bumps 130 may include a double-sided plating step (as shown in FIGS. 5C and 5D) and a single-sided plating step (as shown in FIG. 5E).

Referring to FIG. 5C, before forming the plating metal 133, a first dry film 11 may be covered in the double-sided plating step to be patterned and patterned to obtain a second dry film. 12 covers the second surface 112 and is patterned. In this embodiment, the second dry film 12 can cover the plating seed layer 225.

A plurality of plating metals 133 and the second end faces 132 are formed in the double-sided plating step. In this embodiment, the plating metal 133 fills the through holes 120 such that the second end surfaces 132 are aligned with the second opening 122. The first end faces 131 are formed in the single-sided plating step.

Next, referring to FIG. 5E, the single-sided electroplating step is performed, and the first dry film 11 and the second dry film 12 can be used in the single-sided electroplating step, and the single-sided electroplating step can be preceded. A photoresist 15 is packed in the holes 14 of the patterned second dry film 12. Next, referring to FIG. 5F, the first dry film 11 and the second dry film 12 remaining in the wafer body 110 are removed to complete the setting steps of the columnar bumps 130.

Next, referring to FIG. 5G, after the step of disposing the columnar bumps 130, an etching step is performed to remove the plating seed layer 225 on the second surface 112. Due to the change in position of the plating seed layer 225, the protruding height of the columnar bumps 130 is not affected in the etching step.

The present invention also discloses a cross-sectional view of the stacked structure of the wafer structure 200 as described above, which is illustrated in FIG. The stack structure mainly includes a plurality of wafer structures 200 and a substrate 20, and the wafer structures 200 are stacked on one of the upper surfaces 21 of the substrate 20 by the vertical alignment of the through holes 120. In the present embodiment, the wafer structures 200 are stacked in the same direction in such a manner that the second end faces 132 of the columnar bumps 130 face the upper surface 21 of the substrate 20. Specifically, the second end faces 132 of the wafer structure 200 located at the bottom are bonded to the plurality of pads 23 of the substrate 20 . Between the wafer structures 200, the pillar bumps 130 are connected by the solder 140 to achieve electrical connection. The upper surface 21 of the substrate 20 can be formed with a glue 30 for sealing the wafer structures 200. One of the lower surfaces 22 of the substrate 20 is engageable with a plurality of external terminals 40 for external engagement.

The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention. Any simple modifications, equivalent changes and modifications made without departing from the technical scope of the present invention are still within the technical scope of the present invention.

11. . . First dry film

12. . . Second dry film

13. . . Hole

14. . . Hole

15. . . Photoresist

20. . . Substrate

twenty one. . . Upper surface

twenty two. . . lower surface

twenty three. . . Pad

30. . . Sealant

40. . . External terminal

100. . . Wafer structure

110. . . Chip body

111. . . First surface

112. . . Second surface

120. . . Through hole

121. . . First opening

122. . . Second opening

123. . . Shrink

124. . . Metal layer

125. . . Electroplated seed layer

130. . . Columnar bump

131. . . First end face

132. . . Second end face

133. . . Plating metal

140. . . solder

200. . . Wafer structure

225. . . Electroplated seed layer

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic cross-sectional view showing a wafer structure having a crucible perforation according to a first embodiment of the present invention.

2A to 2G are views showing a cross-sectional view of an element in a method of forming a wafer structure according to a first embodiment of the present invention.

Figure 3 is a cross-sectional view showing the application of the wafer structure in accordance with the first embodiment of the present invention to a stacked structure.

Figure 4 is a cross-sectional view showing another wafer structure having a perforated hole in accordance with a second embodiment of the present invention.

5A to 5G are cross-sectional views showing the elements of the wafer structure in the forming method according to the second embodiment of the present invention.

Figure 6 is a cross-sectional view showing the application of the wafer structure in accordance with the second embodiment of the present invention to a stacked structure.

100. . . Wafer structure

110. . . Chip body

111. . . First surface

112. . . Second surface

120. . . Through hole

121. . . First opening

122. . . Second opening

123. . . Shrink

124. . . Metal layer

125. . . Electroplated seed layer

130. . . Columnar bump

131. . . First end face

132. . . Second end face

133. . . Plating metal

140. . . solder

Claims (16)

A wafer structure having a crucible, comprising: a wafer body having a first surface and a second surface; and two or more through holes extending through the first surface to the second of the wafer body a through hole having a first opening on the first surface, a second opening on the second surface, and a constriction between the first opening and the second opening, wherein the cutout The first opening is smaller than the second opening; the two or more columnar bumps are coupled to the wafer body in such a manner as to align the through holes, and each of the columnar bumps has a first An end surface and a second end surface, wherein the columnar protrusions protrude from the first surface in a convex shape so that the first end surfaces are away from the corresponding first opening, and the columnar protrusions And the plurality of solders are formed on the first end faces; wherein the second portions are adjacent to the corresponding second openings; and the plurality of solders are formed on the first end faces; The end face is corresponding to the corresponding shrinkage and the first Between the openings, such that the second end faces in the through holes are larger than the apertures of the constrictions, and the center points of the first end faces and the second end faces are longitudinally aligned with the constrictions The center point. The wafer structure having a perforated hole according to claim 1, wherein the through holes are formed by the first opening and the second opening The side walls to the neck are inclined so that the through holes are hourglass-shaped. The wafer structure having a perforated hole according to claim 1, wherein the material of the columnar bumps is a metal that can be plated. The wafer structure having a perforated hole according to claim 1, wherein the first surface is an active surface. A method for forming a wafer structure having a crucible, comprising the steps of: providing a wafer body having a first surface and a second surface; and drilling two or more through holes through the wafer body The first surface to the second surface, each through hole having a first opening at the first surface, a second opening at the second surface, and a first opening and the second opening The necking is smaller than the first opening and smaller than the second opening; two or more columnar bumps are disposed to be engaged with the wafer body in such a manner as to align the through holes, each a columnar bump has a first end surface and a second end surface, wherein the columnar bumps protrude from the first surface in a convex shape so that the first end faces are away from the corresponding first An opening, and the columnar bumps extend through the corresponding recesses such that the second end faces are adjacent but not exceeding the corresponding second openings; and a plurality of solders are formed on the first end faces on; The second end faces are disposed between the corresponding cutouts and the second openings, such that the second end faces in the through holes are larger than the apertures of the cutouts, and the An end surface and a center point of the second end faces are longitudinally aligned with a center point of the constrictions. The method for forming a wafer structure having a perforated hole according to claim 5, wherein the through holes are inclined by the first opening and the second opening to the side wall of the constriction to make the through holes The hole is hourglass shaped. The method for forming a wafer structure having a ruthenium perforation according to claim 6, wherein the method for forming the slanted sidewall is selected from the group consisting of cutting of a rotating laser light, cutting of a scattered-focus laser light, and etching. One. The method for forming a wafer structure having a ruthenium perforation according to claim 6, wherein the material of the columnar bumps is a metal that can be plated. The method for forming a wafer structure having a ruthenium perforation according to claim 8 , wherein the step of arranging the pillar bumps comprises a double-side plating step and a single-side plating step in the double-side plating step Forming the second end faces, the first end faces are formed in the single-sided plating step. The method for forming a wafer structure having a ruthenium perforation according to claim 9 wherein a first dry film covers the first surface and is patterned in the double-side plating step to make a second The dry film covers the second surface and is patterned, and the first dry film and the second dry film are used in the single-sided plating step, and the photoresist is filled in the single-sided plating step. A plurality of holes of the second dry film are exposed to expose the second end faces. A method of forming a wafer structure having a tantalum perforation according to claim 6 wherein the first surface is an active surface. The method for forming a wafer structure having a tantalum perforation according to claim 6 or 11, wherein after the step of disposing the pillar bumps, an etching step is further included to remove one of the first surfaces Electroplating seed layer. A stacked structure comprising a plurality of wafer structures having a crucible perforation as described in claim 1 and a substrate, wherein the plurality of through-holes are vertically aligned, the wafer structures are stacked on the substrate An upper surface. The stacked structure according to claim 13 further comprising a gel formed on the upper surface of the substrate to seal the wafer structures. The stacked structure of claim 14, wherein the encapsulant further fills a gap between the wafer structures. The stacked structure according to claim 13 further comprising a plurality of external terminals bonded to a lower surface of the substrate.