TWI420598B - 在功率半導體晶片上形成帶有圖案的厚金屬的方法 - Google Patents

在功率半導體晶片上形成帶有圖案的厚金屬的方法 Download PDF

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TWI420598B
TWI420598B TW99101228A TW99101228A TWI420598B TW I420598 B TWI420598 B TW I420598B TW 99101228 A TW99101228 A TW 99101228A TW 99101228 A TW99101228 A TW 99101228A TW I420598 B TWI420598 B TW I420598B
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metal
thickness
layer
forming
copper
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TW99101228A
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TW201030852A (en
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Il Kwan Lee
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Alpha & Omega Semiconductor
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Description

在功率半導體晶片上形成帶有圖案的厚金屬的方法
本發明涉及一種功率半導體晶片的製備方法。更確切地說，本發明是關於一種在一個功率半導體晶片上製備厚金屬的工藝。
半導體功率器件是當今電子行業中最重要的支柱產業之一。如今半導體功率器件不斷朝著用低功率消耗以及低成本，來獲得更高的晶片集成密度、更高的功率承載能力的方向發展，因此以往在引線接合法中用金線和鋁線的方法，已經被銅線所取代，這是因為在相同接線損毀的情況下，銅線是最節省成本的方法。但主要的技術難題在於銅線的硬度，為了能夠焊接銅線，需要不斷增加在功率半導體晶片上的金屬厚度，一般要求金屬厚度在3-6微米之間(1微米=10-6米)。
用傳統焊線方法製備的半導體功率器件，用一個1-3微米的單一的熱金屬層，作為接觸和焊接區。當冷金屬鋁在接觸孔中形成空洞導致可靠性失效時，用熱金屬鋁覆蓋階梯，以便在接觸孔內獲得可靠的接觸。這對於通過縮小器件尺寸，來提升半導體有效區域工作效率的情況來說，顯得尤為重要。例如，現在使用的一些功率金屬氧化物半導體場效應管的壁-壁節距尺寸都在微米量級上，這就要求接觸孔的尺寸更小，掩膜校準公差也要小。但是由於熱金屬良好的階梯覆蓋率會降低以後掩膜過程中的校準標記的銳度，所以在增加金屬層厚度時，公差也要適當增大，這樣一來，半導體的有效區域效率也將降低。因此，有必要找到一種既能提供可靠接觸，又能提供有效校準標記，在3-6微米範圍內沉積厚金屬層的新方法。
本方法用於在一個半導體功率晶片的表面絕緣層上形成帶圖案的厚金屬。其中半導體功率晶片頂部帶有多個預設圖案的接觸區。本方法包括以下步驟：
a)製備一個帶有內置校準標記、近乎完整的半導體晶片，準備用於塗敷金屬。
b)在晶片上方，用熱金屬工藝，沉積一層子厚度為TK1的底部金屬層。
c)在底部金屬層上方，用冷金屬工藝，沉積一層子厚度為TK2的頂部金屬層，形成總厚度為TK=TK1+TK2的複合厚金屬。
d)使用內置的校準標記作參照，在複合厚金屬上形成圖案。
按照這種方法製備的帶圖案的厚金屬具備以下優點：更好的金屬階梯覆蓋率，原因是熱金屬工藝比冷金屬工藝具有更好的金屬階梯覆蓋率。
更低的校準誤差率，原因是冷金屬工藝的校準信號雜訊比熱金屬工藝的更低。
在一個典型實施例中，如果複合厚金屬產生過度校準信號雜訊的話，會導致不可接受的校準誤差率，因此本方法還對子厚度TK1和TK2做出了進一步限制，使總厚度TK不超過預設的最大厚度TKmax。
在一個典型實施例中，如果TK1厚度不足的話，會導致不可接受的金屬階梯覆蓋率，因此本方法還規定TK1和TK2子厚度的比值R=TK2/TK1不超過預設的最大比值Rmax。
在一個典型實施例中，如果TK1厚度過大的話，會導致不可接受的校準誤差率，因此本方法還規定TK1和TK2子厚度的比值R=TK2/TK1不小於預設的最小比值Rmin。
在一個典型實施例中，使用熱金屬工藝沉積底部金屬層還包括在400攝氏度以上時，真空沉積一種(鋁、矽、銅)的混合物。按照重量百分比，這種混合物含有98%~99%的鋁、0.5%~1.5%的矽以及0.1%~1.0%的銅。
在一個典型實施例中，使用冷金屬工藝沉積頂部金屬層還包括，在大約300±50攝氏度時，真空沉積一種(鋁、銅)的混合物。按照重 量百分比，這種混合物含有99.0%~99.9%的鋁和0.1%~1.0%的銅。
在一個典型實施例中，TKmax為6.0微米，Rmax約為7：1，Rmin約為3：1。
對於本領域的技術人員，本說明書還將進一步討論本發明的上述情況以及多個實施例。
10‧‧‧半導體晶片
11‧‧‧校準標記群
20、20”‧‧‧金屬氧化物半導體場效應管晶片
105‧‧‧襯底層
110‧‧‧外延層
115‧‧‧絕緣區
120‧‧‧柵極絕緣層
125‧‧‧溝道
125-R‧‧‧柵極流道溝道
130‧‧‧絕緣柵極材料
135‧‧‧本體區
140‧‧‧源極區
145‧‧‧介質層
150-G‧‧‧柵極接觸開口
150-S‧‧‧源極/本體接觸開口
155‧‧‧本體接觸植入區
1a‧‧‧溝道盒
160‧‧‧金屬層
160-G‧‧‧分離柵極金屬
160-S‧‧‧源極金屬層
161‧‧‧I-型(熱)金屬
162‧‧‧Ⅱ-型(冷)金屬
1a”‧‧‧校準標記
200‧‧‧引線框
210‧‧‧壓料墊
220‧‧‧漏極引線
230‧‧‧源極引線
240、260‧‧‧柵極引線
250‧‧‧銅線
第1A圖表示一個帶有內置校準標記的功率金屬氧化物半導體場效應管的俯視圖；第1B圖表示一個金屬氧化物半導體場效應管晶片的一部分，在金屬化之前的橫截面視圖；第1C圖為第1A圖的內置校準標記的俯視圖；第1D圖為第1C圖的內置校準標記的橫截面視圖；第2A圖表示一個金屬氧化物半導體場效應管晶片的一部分，在實現銅線焊接的厚金屬工藝的一個實施例後的橫截面視圖；第2B圖表示第1C圖所示的內置校準標記的一部分，在實現銅線焊接的厚金屬工藝的一個實施例後的橫截面視圖；第3A圖表示一個金屬氧化物半導體場效應管晶片的一部分，在實現銅線焊接的厚金屬工藝的另一個實施例後的橫截面視圖；第3B圖表示第1C圖所示的內置校準標記的一部分，在實現銅線焊接的厚金屬工藝的另一個實施例後的橫截面視圖；第4圖表示金屬氧化物半導體場效應管封裝的俯視圖。
本說明書及附圖僅對本發明現有的一個或多個較佳實施例作解釋說明，並對許多任選功能和/或可選實施例作了介紹。本說明書及附圖僅用作解釋說明，並不能以此局限本發明的範圍。因此，本領域的技術人員應該可以輕鬆掌握各種變化、修正和可選方案。這些變化、修正和可選方案也應屬於本發明的保護範圍內。
第1A圖表示半導體晶片10的典型結構，晶片上面含有多個帶溝道的金屬氧化物半導體場效應管晶片20，每個晶片都具有如第1B圖所示的橫截面視圖，為以後的金屬化做準備。在晶片10的四個角上，帶有校準標記群11，用於在製備過程中校準晶片。每個校準標記群11都含有多個列，每一列都有多個如第1C圖所示的3×4微米溝道盒。第1D圖表示一個溝道盒1a的橫截面。溝道盒1a的深度約為1.0-1.5微米。也可選擇另一種幾何形狀的校準標記，比如交叉型。參照第1B圖，金屬氧化物半導體場效應管晶片20含有一個有源區，有源區中帶有多個溝道125，並且絕緣柵極材料130延伸至外延層110中，覆蓋在襯底層105上，襯底層105起漏極的作用。在一個實施例中，絕緣柵極在溝道125底部，擁有一個較厚的絕緣區115。在另一個實施例中，柵極絕緣層120位於溝道125的側壁上，絕緣區115同柵極絕緣層120的厚度一樣。金屬氧化物半導體場效應管晶片20還包括本體區135，在溝道和源極區140之間延伸，沉積在溝道附近的本體區中。本體接觸植入區155沉積在源極區140之間。介質層145覆蓋在半導體表面，帶有源極/本體接觸開口150-S，通過介質層145，為源極/本體區提供金屬接觸。一般來說，介質層145的厚度約為0.3-1.0微米，接觸開口的寬度為0.15-0.5微米。在一個實施例中，介質層145的厚度約為0.5微米，源極/本體接觸開口的寬度約為0.25微米。
金屬氧化物半導體場效應管晶片20還包括一個終止區，帶有一個柵極接觸開口150-G，通過介質層145，在柵極流道溝道125-R頂部，為柵極130提供金屬接觸。在一個實施例中，柵極流道溝道125-R要比柵極溝道125更寬、更深。在另一個實施例中，柵極接觸開口150-G的寬度要比源極/本體接觸開口150-S的寬度更窄。柵極溝道125和柵極流道溝道125-R在第三個維度上相互連接(圖中沒有給出)。
如第2A圖所示，在半導體晶片10上方沉積一個金屬層160。在此過程中，金屬也覆蓋了校準標記1a。被金屬覆蓋的校準標記用於，在形成帶圖案的金屬層160時，對齊掩膜，以便從源極金屬160-S上分離柵極金屬160-G。為了使用于銅引線接合的結合片足夠厚，金屬層160的厚度應在3-6微米之間，最好是4-5微米之間。可以將I-型金屬化和Ⅱ-型金 屬化配合使用。之所以使用“I-型金屬化”和“Ⅱ-型金屬化”技術，是為了在半導體晶片的處理過程中，使多種類型的材料混合物都可用於金屬化。而且，對於每種材料混合物，一般都有一個首選的晶片處理參數集，用於相關的沉積過程。典型實施例需要以下條件：
I-型金屬化：含有鋁、矽、銅的熱金屬，在等於或大於400攝氏度的情況下真空沉積。在一個實施例中，按照重量百分比，這種混合物(鋁、矽、銅)含有98%~99%的鋁、0.5%~1.5%的矽以及0.1%~1.0%的銅。一個較佳的典型實施例是(按照重量百分比)含有98.5%的鋁、1.0%的矽以及0.5%的銅。在處理過程中，要注意在熱金屬中添加Si的摻雜物的時間，以防止鋁在矽晶片中向下形成尖峰。
Ⅱ-型金屬化：含有鋁和銅的冷金屬，在等於或小於350攝氏度的情況下真空沉積。在一個實施例中，按照重量百分比，這種混合物(鋁、銅)含有99.0%~99.9%的鋁、0.1%~1.0%的銅。一個較佳的典型實施例是(按照重量百分比)含有99.5%的鋁和0.5%的銅。
在一個實施例中，當溫度超過400攝氏度時，使用超導薄膜沉積一層4微米厚的I-型熱金屬鋁層。第2B圖表示4微米厚的I-型金屬沉積後，校準標記1a的橫截面視圖。如圖所示，金屬層160提供良好的階梯覆蓋率。但是，厚金屬層160會使下面校準標記的階梯結構變得平整。每一個變形的標記都會在校準掩膜的過程中，因對比度下降而產生干擾校準信號。另外，I-型金屬的晶粒邊界結構，使得來自一個校準標記探測器的光，通過I-型金屬後，不能清晰看到校準標記1a’；Ⅱ-型金屬的晶粒邊界結構更適宜完成此項任務。在接下來的接觸金屬掩膜刻蝕工藝中，如果使用單程讀取演算法，由於校準標記的微弱對比度造成的干擾校準信號，會導致45.8%的誤差率，這將削減多達20%的成品產量。為了保證充足的產量，這種高校準誤差率要求掩膜校準公差也要更大，因此先進技術製造的小器件尺寸帶來的優勢被大幅削弱。
在另一個實施例中，如第3A-3B圖所示，使用I-型和Ⅱ-型金屬的混合物沉積。最好是在一個較厚的Ⅱ-型(冷)金屬162層之後，沉積一個較薄的I-型(熱)金屬161層。例如，I-型金屬161(熱 金屬)薄層的厚度可以在0.5-1微米之間選擇，Ⅱ-型金屬162(冷金屬)厚層的厚度可以在3-4微米之間選擇。第3A圖和第3B圖分別表示沉積I-型金屬薄層和Ⅱ-型金屬厚層之後，金屬氧化物半導體場效應管晶片20”校準標記1a”的橫截面視圖。第2A圖和第2B圖，以及第3A圖和第3B圖表示複合金屬層，在與半導體區域保持良好接觸的同時，提供了一個與下方橫截面一致的頂面。校準標記的階梯結構投影在頂面上，合適的對比度，以便準確地校準掩膜。另外，頂部金屬表面上的階梯結構，在引線接合時起襯墊的作用，以減弱引線接合時產生的碰撞。
正如上面所提到的，由於熱金屬比較不容易在金屬/半導體介面附近的金屬中形成不可接受的空洞，因此熱金屬比冷金屬的金屬階梯覆蓋率更好。底部I-型金屬層必須足夠厚，以便提供充足的熱金屬，形成不含空洞的金屬/半導體介面。但是隨著I-型金屬層厚度的增加，校準標記的對比度將降低。實驗結果表明，I-型金屬的厚度最好是在0.5-1微米之間，才能使對比度保持在可接受水準之上時，與半導體區域形成良好的接觸。另外，為了維持適當的金屬校準通過率，複合I-型和Ⅱ-型金屬層的總厚度不應超過6微米，最好也不要超過5微米。一個相關的經驗實驗進一步表明，比值R=TK2/TK1不應超過最大比值Rmax(約為7：1)，一旦超出此值，熱金屬厚度TK1過小，不足以獲得可接受的金屬階梯覆蓋率，而且比值R也不應小於Rmin(約為3：1)，一旦小於此值，熱金屬厚度TK1過大，會導致不可接受的校準誤差率。例如，同樣是4微米的複合厚度，0.5微米的I-型金屬和3.5微米的Ⅱ-型金屬複合，或1微米的I-型金屬和3微米的Ⅱ-型金屬複合，都會獲得良好的接觸和校準通過率。
將半導體晶片10切成獨立的晶片20”，以便在背部減薄並金屬化之後，封裝成獨立組件。如第4圖所示，晶片20”沉積在一個引線框200上，金屬氧化物半導體場效應管漏極連接在引線框200的壓料墊210上。引線框200含有一個連接在引線框200一側的壓料墊210上的漏極引線220，在引線框200的另一側有一個源極引線230和一個柵極引線240。可以使用銅線將晶片20”的源極和柵極，通過引線接合到引線框200的源極引線230和柵極引線240上。銅線250用作源極引線，一端連接到源極金 屬層160-S上，另一端連接到源極引線230上。在一個典型實施例中，柵極引線260也是由銅構成，引線的一端連接到柵極金屬層160-G上，另一端連接到柵極引線240上。在另一個典型實施例中，柵極引線260中含有金，以便將柵極引線的直徑減至最小，柵極金屬160-G也達到最小，這樣才能進一步提升半導體區域的工作效率。
本文提出了一種在半導體晶片上，形成帶圖案的堆積厚金屬的方法。此方法包括以下步驟：
a)製備一個近乎完整的功率半導體晶片，準備用於塗敷金屬。
b)在晶片上方，用熱金屬工藝，沉積一層帶有內置校準標記的、厚度為TK1的底部金屬層。
c)在底部金屬層上方，用冷金屬工藝，沉積一層厚度為TK2的頂部金屬層，形成總厚度為TK=TK1+TK2的複合厚金屬。
d)使用內置的校準標記作參照，在複合厚金屬上形成圖案。
按照這種方法製備的帶圖案的厚金屬具備以下優點：更好的金屬階梯覆蓋率，原因是熱金屬工藝比冷金屬工藝具有更好的金屬階梯覆蓋率。
更低的校準誤差率，原因是冷金屬工藝的校準信號雜訊比熱金屬工藝的更低。
上述說明包含許多特殊情況，這些特殊情況僅對本發明現有的較佳實施例作解釋說明用，不能以此局限本發明的保護範圍。通過說明和附圖，對這些特殊結構的多個典型實施例作了說明。本領域的技術人員應當清楚，本發明還可以通過其他特殊方法實現，無需過多的實驗，本領域的技術人員就能實現這些實施例。例如，本發明使用堆積金屬結構，以便同時改變各種金屬子層的不同優勢，我們預計此方法也可用於各種其他金屬混合物的多層堆積，以及相關的沉積階梯等。本專利文件旨在說明，本發明的範圍不應局限於上述說明中的典型實施例，而應由以下的權利要求書來界定。任何和所有來自於權利要求書中內容或同等範圍中的修正，都將被認為屬於本發明的保護範圍之內。
20”‧‧‧金屬氧化物半導體場效應管晶片
105‧‧‧襯底層
110‧‧‧外延層
120‧‧‧柵極絕緣層
125‧‧‧溝道
125-R‧‧‧柵極流道溝道
130‧‧‧絕緣柵極材料
135‧‧‧本體區
140‧‧‧源極區
145‧‧‧介質層
155‧‧‧本體接觸植入區
160-G‧‧‧分離柵極金屬
160-S‧‧‧源極金屬層
161‧‧‧I-型(熱)金屬
162‧‧‧Ⅱ-型(冷)金屬

Claims (24)

  1. 一種用於在一個帶有多個預設圖案的接觸區的功率半導體晶片的表面絕緣層上製備帶圖案的厚金屬的方法，其特徵在於，這種方法包括：a)製備一個帶有內置校準標記、近乎完整的半導體晶片，準備用於塗敷金屬；b)在晶片上方，用熱金屬工藝，沉積一層子厚度為TK1的底部金屬層；c)在底部金屬層上方，用冷金屬工藝，沉積一層子厚度為TK2的頂部金屬層，形成總厚度為TK=TK1+TK2的複合厚金屬；d)使用內置的校準標記作參照，在複合厚金屬上形成圖案；按照這種方法製備的帶圖案的厚金屬具備以下優點：1)更好的金屬階梯覆蓋率，原因是熱金屬工藝比冷金屬工藝具有更好的金屬階梯覆蓋率；2)更低的校準誤差率，原因是冷金屬工藝的校準信號雜訊比熱金屬工藝的更低。
  2. 如申請專利範圍第1項所述的用於形成帶圖案的厚金屬的方法，其特徵在於，還包括選擇所述的子厚度TK1和所述的子厚度TK2，使總厚度TK不超過預設的總厚度最大值TKmax，一旦超過最大值，無論TK1和TK2取何值，複合厚金屬的額外校準信號雜訊，都會導致不可接受的校準誤差率。
  3. 如申請專利範圍第2項所述的用於形成帶圖案的厚金屬的方法，其特徵在於，還包括選擇所述的子厚度TK1和所述的子厚度TK2，使它們的比值R=TK2/TK1不超過預設的最大比值Rmax，一旦超過最大比值，子厚度TK1厚度不足，會導致不可接受的金屬階梯覆蓋率。
  4. 如申請專利範圍第2項所述的用於形成帶圖案的厚金屬的方法，其特徵在於，還包括選擇所述的子厚度TK1和所述的子厚度TK2，使它們的比值R=TK2/TK1不小於預設的最小比值Rmin，一旦小於最小比值，子厚度TK1厚度過大，會導致不可接受的校準誤差率。
  5. 如申請專利範圍第1項所述的用於形成帶圖案的厚金屬的方法，其特徵在於，使用熱金屬工藝沉積底部金屬層還包括，在溫度超過400攝氏度時，真空沉積(鋁、矽、銅)的混合物。
  6. 如申請專利範圍第5項所述的用於形成帶圖案的厚金屬的方法，其特徵在於，(鋁、矽、銅)的混合物還包括(按照重量百分比)98%~99%的鋁、0.5%~1.5%的矽以及0.1%~1.0%的銅。
  7. 如申請專利範圍第6項所述的用於形成帶圖案的厚金屬的方法，其特徵在於，(鋁、矽、銅)的混合物還包括(按照重量百分比)98.5%的鋁、1.0%的矽以及0.5%的銅。
  8. 如申請專利範圍第1項所述的用於形成帶圖案的厚金屬的方法，其特徵在於，使用冷金屬工藝沉積頂部金屬層還包括，在溫度大致300±50攝氏度時，真空沉積(鋁、銅)的混合物。
  9. 如申請專利範圍第8項所述的用於形成帶圖案的厚金屬的方法，其特徵在於，(鋁、銅)的混合物還包括(按照重量百分比)99.0%~99.9%的鋁和0.1%~1.0%的銅。
  10. 如申請專利範圍第9項所述的用於形成帶圖案的厚金屬的方法，其特徵在於，(鋁、銅)的混合物還包括(按照重量百分比)99.5%的鋁和0.5%的銅。
  11. 如申請專利範圍第2項所述的用於形成帶圖案的厚金屬的方法，其特徵在於，所述的TKmax約為4.0-5.0微米。
  12. 如申請專利範圍第3項所述的用於形成帶圖案的厚金屬的方法，其特徵在於，所述的Rmax約為7：1。
  13. 如申請專利範圍第4項所述的用於形成帶圖案的厚金屬的方法，其特徵在於，所述的Rmin約為3：1。
  14. 如申請專利範圍第1項所述的用於形成帶圖案的厚金屬的方法，其特徵在於，還包括選擇所述的子厚度TK1和所述的子厚度TK2，使TK1約為1.0微米，TK2約為3.0微米。
  15. 如申請專利範圍第1項所述的用於形成帶圖案的厚金屬的方法，其特徵在於，還包括選擇所述的子厚度TK1和所述的子厚度TK2，使TK1約為0.5微米，TK2約為3.5微米。
  16. 一種功率半導體晶片，其特徵在於，包括：一個帶有多個溝道的有源區，並且絕緣柵極材料延伸至覆蓋在襯底層上的外延層中，襯底層起漏極的作用； 在溝道之間延伸的本體區；沉積在溝道附近的本體區中的源極區；一個覆蓋在半導體表面，帶有接觸開口的介質層；一個覆蓋在介質層上的金屬層，通過接觸開口連接源極區，但所述的金屬層包括一個位於底部的I-型熱金屬薄層和一個位於頂部的Ⅱ-型冷金屬厚層；以及一個帶有柵極接觸開口的終止區，穿過介質層，在柵極流道溝道頂部，為絕緣柵極提供金屬接觸。
  17. 如申請專利範圍第16項所述的功率半導體晶片，其特徵在於，所述的熱金屬層的厚度在0.5-1微米之間。
  18. 如申請專利範圍第16項所述的功率半導體晶片，其特徵在於，所述的金屬層的複合厚度在4-5微米之間，以便銅引線接合。
  19. 如申請專利範圍第16項所述的功率半導體晶片，其特徵在於，Ⅱ-型金屬厚度與I-型金屬厚度的比值在3：1至7：1之間。
  20. 如申請專利範圍第16項所述的功率半導體晶片，其特徵在於，所述的金屬層有一階梯結構的頂面形態與它下面的介質層的形態基本一致。
  21. 如申請專利範圍第16項所述的功率半導體晶片，其特徵在於，還包括：一個覆蓋在介質層上的金屬層，通過接觸開口連接絕緣柵極，所述的金屬層還包括一個位於底部的I-型金屬層和一個位於頂部的Ⅱ-型金屬層。
  22. 一種功率半導體器件，其特徵在於，包括：一個帶有多個接觸區的功率半導體晶片；在晶片上方，用熱金屬工藝，沉積有一層子厚度為TK1的底部金屬層，在底部金屬層上方，用冷金屬工藝，沉積有一層子厚度為TK2的頂部金屬層，形成總厚度為TK=TK1+TK2的複合厚金屬；一個覆蓋在半導體表面的介質層，在所述的多個接觸區上方延伸，介質層上還帶有多個接觸開口；一個厚度在4微米以上的第一金屬層，覆蓋在介質層上，通過多個接觸開口，連接介質層下方的多個源極區和本體區；以及銅接合引線將金屬層連接到一個引線框的多個源極引線上。
  23. 如申請專利範圍第22項所述的功率半導體器件，其特徵在於，還包括： 一個通過柵極流道溝道頂部的介質層開口的柵極接頭；一個覆蓋在介質層上的第二金屬層，通過接觸開口連接一個柵極流道；以及一個銅接合引線，將第二金屬層連接到引線框上的一個柵極引線上。
  24. 如申請專利範圍第22項所述的功率半導體器件，其特徵在於，還包括：一個通過柵極流道溝道頂部的介質層開口的柵極接頭；一個覆蓋在介質層上的第二金屬層，通過接觸開口連接一個柵極流道；以及一個金接合引線，將第二金屬層連接到引線框上的一個柵極引線上，以便進一步提升半導體區域的工作效率。
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