TWI420499B - Liquid crystal display device and method for driving the same - Google Patents

Description

Liquid crystal display device and driving method thereof

The present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device capable of avoiding frame flicker caused by frame rate switching and a driving method thereof.

The Seamless Dynamic Refresh Rate Switching (SDRRS) function is a power saving technology proposed by Intel Corporation for a liquid crystal display device for a notebook computer. When the liquid crystal display device of the notebook computer is in a standby state, the figure is The frame rate can be switched from 60 Hz (Hertz, Hz) to 40 Hz for power saving purposes. However, when the liquid crystal display device is switched to a different frame rate, the charging time of the liquid crystal capacitor is different, which may cause a problem of flickering of the screen.

Please refer to FIG. 1A , which is a timing diagram of a control signal of a frame rate of 60 Hz when the conventional liquid crystal display device implements the SDRRS function. The liquid crystal display device controls a gate driver integrated circuit and a source driver integrated circuit by a Timing Controller (T-Con), and is driven by a gate. The integrated circuit controls the conduction of the gate line, and the source drives the integrated circuit to write the data to the source line. In the figure, N, N+1, and N+2 respectively represent control signals related to the Nth gate line, the N+1th gate line, and the N+2th gate line. The preparation signal STH and the write signal LP are transmitted from the timing controller to the source drive integrated circuit, and the gate control signal OE is transmitted from the timing controller to the gate drive integrated circuit. When the preparation signal STH is at the high level, it indicates that the timing controller is ready to transmit data to the source drive integrated circuit. When the write signal LP is at the high level, the timing controller transmits the data to the source drive integrated circuit, and when the write signal LP is at the low level, the source drive integrated circuit writes the data to the source line. When the gate control signal OE is at a high level, the gate line is not turned on, and the problem of rewriting is prevented when the adjacent two gate lines are overlapped. When the gate control signal OE is at a low level, the gate line is turned on.

First, when the timing controller transmits the high-level preparation signal STH to the source driving integrated circuit, it indicates that the source driving integrated circuit prepares to prepare the source line electrically coupled to the Nth gate line. The data is transmitted to the source driving integrated circuit, and then when the write signal LP is at the high level, the timing controller transmits the data of the source line electrically coupled to the Nth gate line to the source driving integrated circuit. The timing controller simultaneously transmits the high level gate control signal OE to the gate drive integrated circuit to prevent rewriting. After the data transfer is completed, the timing controller transmits the low level gate control signal OE to the gate drive integrated circuit to turn on the Nth gate line, and simultaneously transmits the low level write signal LP to the source drive integrated body. The circuit, the source driving integrated circuit writes the data into the source line electrically coupled to the Nth gate line and starts charging to maintain the data, that is, the charging time of the Nth gate line is the gate The period during which the control signal OE is at a low level is represented by T1.

When the timing controller transmits the high-level preparation signal STH to the source driving integrated circuit again, it indicates that the source driving integrated circuit is ready to electrically connect the source line with the (N+1)th gate line. The data is transmitted to the source driving integrated circuit, and then when the write signal LP is at the high level, the timing controller transmits the data of the source line electrically coupled to the (N+1)th gate line to the source driver. The integrated circuit simultaneously transmits the high-level gate control signal OE to the gate drive integrated circuit to prevent re-writing. After the data transfer is completed, the timing controller transmits the low level gate control signal OE to the gate drive integrated circuit to turn on the N+1th gate line, and simultaneously transmits the low level write signal LP to the source drive. In the integrated circuit, the source driving integrated circuit writes the data into the source line electrically coupled to the N+1th gate line and starts charging to maintain the data, that is, the N+1th gate line The charging time is the period during which the gate control signal OE becomes a low level, which is also T1. As for the subsequent control timing and so on, this will not be described again.

Please refer to FIG. 1B , which is a timing diagram of a control signal of a frame rate of 40 Hz when the conventional liquid crystal display device implements the SDRRS function. The control timing of the preparation signal STH, the write signal LP, and the gate control signal OE is the same as that of FIG. 1A. The difference between FIG. 1B and FIG. 1A is that the frame rate of FIG. 1B is reduced to 40 Hz, so the period of the gate control signal OE is increased, and the gate control signal OE is high during the period of the high level, which represents the gate control. The signal OE is increased during the low level period, that is, the charging time representing the frame rate of 40 Hz is increased, and the charging time of the frame rate of 40 Hz is represented by T2. Since the charging time T2 of the 40 Hz frame rate is different from the charging time T1 of the 60 Hz frame rate, different brightnesses are generated, causing a problem that the picture flickers when the frame rate is switched.

The existing solution is based on the charging time T1 of the frame rate of 60 Hz, and reduces the period during which the gate control signal OE is at a low level by increasing the period of the gate control signal OE in the first FIG. The charging time T2 of the frame rate is shortened to T1, so the same charging time (ie, T1) is maintained regardless of the frame rate of 60 Hz or 40 Hz, and the problem of flickering of the screen when the frame rate is switched is avoided. This solution must be adjusted in a time during which the gate control signal OE is at a high level. However, it is actually difficult to complete the adjustment in an instant, so that there is still a possibility of flickering of the screen.

An object of the present invention is to provide a liquid crystal display device and a driving method thereof that can avoid flickering of a picture caused by instantaneous switching of a frame rate.

In order to achieve the above object, according to a feature of the present invention, a liquid crystal display device includes a liquid crystal panel, a timing controller, a modulation unit, a detecting unit, and a driving unit. The timing controller receives a first frame rate and provides a clock signal corresponding to one of the first frequencies of the first frame rate. When the first frame rate is required to switch to a second frame rate, the modulation unit gradually modulates the clock signal from the first frequency to a second frequency corresponding to one of the second frame rates. So that the first frame rate is gradually changed to the second frame rate. The detecting unit selects the clock signal of the first frequency or the clock signal of the second frequency. The driving unit controls the liquid crystal panel to display an image according to the clock signal of the first frequency selected by the detecting unit or the clock signal of the second frequency.

According to another feature of the present invention, a liquid crystal display device includes a liquid crystal panel, a timing controller, a modulation unit, a detecting unit, and a driving unit. The driving method includes: The timing controller receives a first frame rate and provides a first frequency corresponding to one of the first frame rates; when the first frame rate is required to switch to a second frame rate, the modulation unit will The clock signal is gradually modulated from the first frequency to a second frequency corresponding to one of the second frame rates, so that the first frame rate is gradually changed to a second frame rate; the detecting unit Selecting the clock signal of the first frequency or the clock signal of the second frequency; and the clock signal of the first frequency selected by the driving unit according to the detecting unit or the clock of the second frequency Signal to control the LCD panel to display images.

The liquid crystal display device and the driving method thereof of the present invention modulate the clock signal in a gradual manner when the first frame rate is required to be switched to the second frame rate, so that the human eye cannot detect the change of the luminance, thereby avoiding the human eye. Feel the problem of flickering the picture.

The technical solution of the present invention will be described in detail below with reference to the accompanying drawings.

Referring to Figure 2, there is shown a liquid crystal display device in accordance with the present invention. The liquid crystal display device includes a liquid crystal panel 200, a timing controller 202, a modulation unit 204, a detecting unit 206, and a driving unit 208. The liquid crystal panel 200 includes a plurality of gate lines GL and a plurality of source lines SL arranged in a staggered manner with each other. The driving unit 208 includes a gate driving unit 210 and a source driving unit 212. The gate driving unit 210 is configured to turn on the gate lines GL. The source driving unit 212 is configured to write data into the source lines SL. In this embodiment, the detecting unit 206 and the modulating unit 204 are separately provided by the timing controller 202. In another embodiment, at least one of the detecting unit 206 and the modulating unit 204 can be disposed in the timing controller 202.

Due to the high-performance data transmission and low-voltage requirements of the liquid crystal display device, a system input signal SI needs to be connected to a low voltage differential signal (LVDS) in accordance with the low voltage differential signal (LVDS) meeting the above requirements. The 214 is passed to the timing controller 202. The system input signal SI includes information on the frame rate.

The clock signal frequency provided by the timing controller 202 can be set by:

F=H _TOTAL ×V _TOTAL ×FR (1)

Where F is the clock signal frequency, H _TOTAL is the horizontal total pixel, V _TOTAL is the vertical total pixel, and FR is the frame rate. It can be seen from the formula (1) that when the SDRRS function is executed, the frame rate FR is required to be switched from 60 Hz (first frame rate) to 40 Hz (second frame rate) due to the horizontal total pixels H _TOTAL and the vertical total The pixel V _{TOTAL is} unchanged, and the present invention gradually changes (down) the clock signal frequency F, so that the frame rate FR can be changed from 60 Hz to 40 Hz as the clock signal frequency F is lowered, although The control signal generated by the timing controller 202 changes with the change of the clock signal frequency F, but it can be made undetectable by the human eye by using the gradual modulation method instead of changing the frame rate FR from 60 Hz to 40 Hz. The brightness of the picture changes. Conversely, when the frame rate FR is required to be switched from 40 Hz to 60 Hz, the gradual modulation (up) of the clock signal frequency F can also be utilized, so that the frame rate FR is raised from the 40 Hz as the clock signal frequency F is raised. Change to 60Hz.

The operation of the liquid crystal display device of the present invention will be explained below. The timing controller 202 receives a first frame rate of the system input signal SI and provides a clock signal corresponding to a first frequency of the first frame rate. The timing controller 202 generates a control signal according to the clock signal to control the liquid crystal panel 200 to display an image. The control signal is, for example, the signal shown in FIG. 1A, which is not described in detail.

Then, when the first frame rate is required to be switched to a second frame rate, the modulation unit 204 gradually modulates the clock signal from the first frequency to a corresponding one of the second frame rates. The second frequency is such that the first frame rate is gradually changed to the second frame rate. The detecting unit 206 selects the clock signal of the first frequency or the clock signal of the second frequency. The driving unit 208 controls the liquid crystal panel 200 to display an image according to the clock signal of the first frequency or the clock signal of the second frequency selected by the detecting unit 206. Further, the gate driving unit 210 turns on the gate lines GL of the liquid crystal panel according to the clock signal of the first frequency selected by the detecting unit 206 or the clock signal of the second frequency. . The source driving unit 212 writes data to each source line SL according to the clock signal of the first frequency selected by the detecting unit 206 or the clock signal of the second frequency.

It should be noted that the modulation unit 204 can adopt a conventional pulse width modulation circuit, which is not described in detail.

Referring to FIG. 3, a schematic diagram of the clock signal DCLK being modulated from the first frequency to the second frequency when the SDRRS function is implemented according to the present invention (ie, changing from the first frame rate) To the second frame rate). When the system input signal SI requires a frame rate switch, the timing controller 202 must recognize the request during the T1 period and change the first frame rate to the second frame rate during the T2 period. It should be noted that the T1 period and the T2 period are calculated according to the SDRRS specification established by Intel Corporation.

Please refer to Figure 4 for a graph of frame rate versus time. It can be seen from the formula (1) that when the clock signal DCLK is modulated from the first frequency to the second frequency, it means that the first frame rate corresponding to the first frequency is changed to the second frame corresponding to the second frequency. The method for modulating the clock signal DCLK of the present invention includes: linearly changing from the first frequency to the second frequency (ie, linearly changing from the first frame rate to the second frame rate), such as Line A, or from the first frequency to the second frequency according to curve B or C (ie, changing from the first frame rate to the second frame rate according to curve B or C).

Please refer to FIG. 5, which illustrates an embodiment of the detecting unit 206 of FIG. 2 and its detection and selection principle. The detecting unit 206 includes a comparator 2060 and a multiplexer 2062. The comparator 2060 compares the first frame rate A and the second frame rate B to determine whether the first frame rate A is required to switch to the second frame rate B. The multiplexer selects the clock signal of the first frequency or the clock signal of the second frequency according to whether the first frame rate A is required to be switched to the second frame rate B. The first frame rate A is determined according to the system input signal SI, and the second frame rate B is used as a comparison reference. In this embodiment, the second frame rate B is 40 Hz. After the timing controller 202 receives the 60 Hz information required by the system input signal SI, the timing controller 202 generates the first frame rate (60 Hz) A and the second frame rate (40 Hz) B to the comparator. 2060, the comparison result C of the comparator 2020 is 0, and the multiplexer 2062 selects a clock signal and a control signal that meet the frame rate of 60 Hz to the driving unit 208. If the system input signal SI is required to be switched from 60 Hz to 40 Hz, the first frame rate A generated by the timing controller 202 to the comparator 2060 is changed from 60 Hz to 40 Hz, and the second frame rate B as a comparison reference is still At 40 Hz, the comparison result C of one of the comparators 2060 is 1. The modulation unit 204 gradually changes the clock signal from 60 Hz to 40 Hz, and the multiplexer 2062 selects the time when the frame rate is 40 Hz. The pulse signal and the control signal are sent to the driving unit 208.

Please refer to FIG. 6 , which is a schematic diagram showing the control signal being modulated from the first frequency to the second frequency as the clock signal DCLK is changed. The control signal in the figure is taken as an example of the write signal LP of FIG. 1A. The present invention can be further configured to adjust the first frequency to the second frequency in the Nth frame, that is, the frame rate from the first The frame rate is changed to the second frame rate. When the frequency of the clock signal DCLK is gradually lowered, the frequency of the write signal LP also decreases.

Please refer to FIG. 7, which is a flow chart showing a driving method of a liquid crystal display device according to the present invention. The liquid crystal display device comprises a liquid crystal panel, a timing controller, a modulation unit, a detecting unit and a driving unit, and the driving method comprises the following steps.

In step S700, the timing controller receives a first frame rate and provides a clock signal corresponding to one of the first frequencies of the first frame rate.

In step S710, when the first frame rate is required to be switched to a second frame rate, the modulation unit gradually modulates the clock signal from the first frequency to a corresponding second frame rate. a second frequency such that the first frame rate is gradually changed to the second frame rate. In one embodiment, the clock signal is linearly modulated from the first frequency to the second frequency. In another embodiment, the clock signal is modulated from the first frequency to the second frequency according to a curve relationship.

In step S720, the detecting unit selects the clock signal of the first frequency or the clock signal of the second frequency.

In step S730, the driving unit controls the liquid crystal panel to display an image according to the clock signal of the first frequency selected by the detecting unit or the clock signal of the second frequency.

In step S720, it is determined whether the first frame rate is required to be switched to the second frame rate, and selecting the first frequency according to whether the first frame rate is required to switch to the second frame rate. The clock signal or the clock signal of the second frequency.

In view of the above, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the invention, and the present invention may be made without departing from the spirit and scope of the invention. Various modifications and refinements are made, and the scope of the present invention is defined by the scope of the appended claims.

200. . . LCD panel

202. . . Timing controller

204. . . Modulation unit

206. . . Detection unit

208. . . Drive unit

210. . . Gate drive unit

212. . . Source drive unit

214. . . Low voltage differential signal connector

2060. . . Comparators

2062. . . Multiplexer

A. . . First frame rate

B. . . Second frame rate

C. . . Comparing results

DCLK. . . Clock signal

GL. . . Gate line

LP. . . Write signal

OE. . . Gate control signal

S700-S730. . . step

SI. . . System input signal

SL. . . Source line

STH. . . Prepare the signal

FIG. 1A is a timing diagram of a control signal of a frame rate of 60 Hz when a conventional liquid crystal display device implements the SDRRS function;

FIG. 1B is a timing diagram of a control signal of a frame rate of 40 Hz when the conventional liquid crystal display device implements the SDRRS function;

Figure 2 is a view showing a liquid crystal display device according to the present invention;

3 is a schematic diagram showing the modulation of the clock signal DCLK from the first frequency to the second frequency when the liquid crystal display device according to the present invention implements the SDRRS function;

Figure 4 is a diagram showing the frame rate-time relationship;

Figure 5 is a diagram showing an embodiment of the detecting unit of Figure 2 and its detection and selection principle;

Figure 6 is a schematic diagram showing the control signal as the clock signal is modulated from the first frequency to the second frequency;

Figure 7 is a flow chart showing a driving method of a liquid crystal display device according to the present invention.

200. . . LCD panel

202. . . Timing controller

204. . . Modulation unit

206. . . Detection unit

208. . . Drive unit

210. . . Gate drive unit

212. . . Source drive unit

214. . . Low voltage differential signal connector

GL. . . Gate line

SI. . . System input signal

SL. . . Source line

Claims (10)

A liquid crystal display device comprising: a liquid crystal panel; a timing controller, receiving a first frame rate and providing a pulse signal corresponding to one of the first frequencies of the first frame rate; a modulation unit, when the When a frame rate is required to switch to a second frame rate, the modulation unit gradually modulates the clock signal from the first frequency to a second frequency corresponding to one of the second frame rates, so that The first frame rate is gradually changed to the second frame rate; a detecting unit selects the clock signal of the first frequency or the clock signal of the second frequency; and a driving unit, according to the The detecting unit selects the clock signal of the first frequency or the clock signal of the second frequency to control the liquid crystal panel to display an image. The liquid crystal display device of claim 1, wherein the modulation unit is disposed in the timing controller. The liquid crystal display device of claim 1, wherein the detecting unit is disposed in the timing controller. The liquid crystal display device of claim 1, wherein the detecting unit comprises: a comparator that determines whether the first frame rate is required to be switched to the second frame rate; and a multiplexer, And selecting the clock signal of the first frequency or the clock signal of the second frequency according to whether the first frame rate is required to switch to the second frame rate. The liquid crystal display device of claim 1, wherein the clock signal is linearly modulated from the first frequency to the second frequency. The liquid crystal display device of claim 1, wherein the clock signal is modulated from the first frequency to the second frequency according to a curve relationship. A driving method of a liquid crystal display device, comprising: a liquid crystal panel, a timing controller, a modulation unit, a detecting unit and a driving unit, the driving method comprising: the timing controller receiving a first image Block rate and providing a clock signal corresponding to one of the first frequencies of the first frame rate; when the first frame rate is required to switch to a second frame rate, the modulation unit signals the clock signal from The first frequency is gradually modulated to a second frequency corresponding to one of the second frame rates, so that the first frame rate is gradually changed to the second frame rate; the detecting unit selects the first frequency The clock signal or the clock signal of the second frequency; and the driving unit controls the liquid crystal according to the clock signal of the first frequency selected by the detecting unit or the clock signal of the second frequency The panel displays the image. The method for driving a liquid crystal display device according to claim 7, wherein the step of the detecting unit selecting the clock signal of the first frequency or the clock signal of the second frequency comprises: determining the Whether the first frame rate is required to switch to the second frame rate; and selecting the clock signal of the first frequency or the second according to whether the first frame rate is required to switch to the second frame rate The clock signal of the frequency. The method of driving a liquid crystal display device according to claim 7, wherein the clock signal is linearly modulated from the first frequency to the second frequency. The method of driving a liquid crystal display device according to claim 7, wherein the clock signal is modulated from the first frequency to the second frequency according to a curve relationship.