TWI419323B - Semiconductor pn junction structure and manufacturing method thereof - Google Patents

Description

Semiconductor PN junction structure and manufacturing method thereof

The present invention relates to a semiconductor PN junction structure and a method of fabricating the same, and more particularly to a semiconductor PN junction structure for enhancing a breakdown protection voltage and a method of fabricating the same.

1A and 1B are respectively a top view and a cross-sectional view showing a prior art semiconductor PN junction structure. As shown in the upper view of FIG. 1A and the cross-sectional view of FIG. 1B, the semiconductor P-type region 11 is in contact with the N-type region 12 to form a PN junction structure 13. Viewed from the top view, the PN junction structure 13 is substantially linear. When the P-type region 11 and the N-type region 12 are unbiased or subjected to a reverse bias (that is, a positive voltage and a negative voltage are respectively applied to the N-type region 12 and the P-type region 11), as shown in FIG. 1C As shown, a depletion region 14 is formed adjacent the PN junction structure 13. The width and electric field strength of the depletion region 14 are related to the type and concentration distribution of the P-type impurity and the N-type impurity in the P-type region 11 and the N-type region 12, in addition to the magnitude of the applied bias voltage. When no bias is applied to the PN junction structure 13, the electric field strength and distribution are as shown in Fig. 1D; the width of the depletion region 14 is indicated by d1 in Fig. 1C. In Fig. 1D, the horizontal axis of the coordinate axis represents the position x , the vertical axis represents the electric field E , and the thick black line segment 15 represents the intensity and distribution of the electric field.

The above-mentioned PN junction is widely used in various semiconductor elements, and its PN junction breakdown protection voltage has its limitations, which is well known to those skilled in the art and will not be described herein. Due to the development of technology, the operating voltage is getting lower and lower, the thermal budget in the semiconductor process is reduced, the concentration of the P and N well regions is increased, and the PN junction collapse protection voltage is lowered. Therefore, when it is necessary to enhance the PN junction collapse protection voltage and not change the impurity doping concentration, a new PN junction structure must be added to enhance the PN junction breakdown protection voltage and increase the application range of the component.

In view of the above, the present invention is directed to the deficiencies of the prior art described above, and provides a semiconductor PN junction structure and a manufacturing method thereof, which can improve the breakdown protection voltage of the component operation and increase the application range of the component.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor PN junction structure and a method of fabricating a semiconductor PN junction structure.

In order to achieve the above object, the present invention provides a semiconductor PN junction structure comprising: a semiconductor substrate; and a PN junction formed by a P-type region and an N-type region being connected to each other in the semiconductor substrate; Wherein, the PN junction has a staggered comb structure as viewed from above.

The interlaced comb structure may be any regular or irregular interlaced shape, which may be viewed from a top view, for example, may include a rectangular, wavy, zigzag, or arcuate structure. Further, an island-shaped impurity region of an opposite conductivity type may be present in the P-type region or the N-type region.

In one embodiment, the PN junction is under the surface of the semiconductor substrate and may comprise a plurality of layers of comb structures.

When the PN junction is subjected to a reverse bias, the formed depletion regions are preferably connected in series.

In another aspect, the present invention also provides a method of fabricating a semiconductor PN junction structure, comprising: providing a semiconductor substrate; and implanting impurities to form a PN junction, the PN junction being a P-type region and a N The pattern regions are formed by being connected to each other in the semiconductor substrate; wherein the PN junction surface has a staggered comb structure as viewed from above.

The purpose, technical content, features and effects achieved by the present invention will be more readily understood by the detailed description of the embodiments.

The drawings in the present invention are schematic and are mainly intended to represent the process steps and the relationship between the layers, and the shapes, thicknesses, and widths are not drawn to scale.

Referring to Figures 2A-2C, there is shown a first embodiment of the present invention, and Figure 2A shows a top view of a semiconductor PN junction formed by implanting impurities in a semiconductor substrate. As shown in FIG. 2A, the semiconductor P-type region 21 is in contact with the N-type region 22 to form a PN junction structure 23. Viewed from the top view, the PN junction structure 23 has an interdigitated comb structure. FIG. 2B shows an electric field simulation diagram of the PN junction structure 23. Since the PN junction structure 23 has an interlaced comb structure, when the PN junction depletion region begins to form, the depletion region will turn with the PN junction to form The strip-shaped depletion zone of the comb-tooth shape; if the distance between the comb teeth is not excessive, the adjacent depletion zones may be connected to each other to form an integrally connected depletion zone, as shown in the hollow depletion zone 24 of FIG. 2B. When the PN junction structure 23 is unbiased or subjected to a reverse bias, the resulting depletion region 24 has a width d2 .

Fig. 2C shows a comparison of the present invention with the prior art, in which the thick black line segment 25 represents the electric field intensity distribution of the present embodiment, and the broken line segment 15 represents the prior art electric field intensity distribution. From Fig. 2C, it can be seen that the present invention is superior to the prior art in that when a fixed reverse bias is applied to the PN junction structure 23, the withstand voltage region, that is, the depletion region 24 is elongated into d2 , The width d1 of the prior art depletion region 14 is wider than that of the prior art, and the electric field is lower than that of the prior art depletion region 14. That is to say, when the same reverse bias is applied, the electric field strength of the embodiment is lower, and the depletion region is wider, which means that the reverse bias voltage that can be withstood by the present invention is higher than that of the prior art, and the range of action is higher. wide.

Next, FIGS. 3 to 6 exemplify that the present invention can be implemented in different shapes and distributions, and FIGS. 3 to 6 show top views of semiconductor PN junctions of four further embodiments of the present invention. The semiconductor PN junction of the present invention may be, in addition to the rectangular comb structure shown in FIG. 2A, for example, but not limited to, a wavy, zigzag, circular arc, etc., as shown in FIGS. 3 to 5. The tooth structure, and the impurity regions of the opposite conduction type are respectively implanted in the P-type region 21 and the N-shaped region 22 as shown in Fig. 6, to form a staggered island-shaped comb-tooth structure. In fact, the so-called "interlaced comb structure" can be any regular or irregular interlaced shape, and it is only necessary to widen the depletion region and reduce the electric field strength by the non-linear PN junction.

7A and 7B illustrate another embodiment of the present invention. As shown in FIG. 7A, the interlaced comb structure of the PN junction may not be limited to a single layer, and may also include a plurality of layers under the surface of the semiconductor substrate. The interdigitated comb structure and the comb-tooth structure which are staggered up and down may not need to be completely aligned or may be staggered. FIG. 7B is a cross-sectional view showing the PN junction of the embodiment. As shown in the figure, the PN junctions of the upper and lower layers are also formed with upper and lower PN junctions when staggered, and the oblique line region indicates the range of the depletion region. It is of course also possible to use the present invention to connect longitudinally adjacent depletion regions to reduce the electric field distribution of the reverse bias and to enhance the collapse protection voltage.

The present invention has been described with reference to the preferred embodiments thereof, and the present invention is not intended to limit the scope of the present invention. In the same spirit of the invention, various equivalent changes can be conceived by those skilled in the art. For example, other process steps or structures, such as deep wells, may be added without affecting the main characteristics of the components. For example, if the semiconductor substrate itself may be P-type or N-type, it is not absolutely necessary to implant two types at this time. Impurities form the PN junction, and in some cases only impurities of the opposite type to the semiconductor substrate need to be implanted. The above and other equivalent variations are intended to be covered by the scope of the invention.

11,21‧‧‧P type area

12,22‧‧‧N-zone

13,23‧‧‧Semiconductor PN junction

14,24‧‧ vacant area

15,25‧‧‧ electric field strength distribution line

D1, d2 ‧ ‧ vacant zone width

x ‧‧‧ position

E ‧‧‧ electric field

Figure 1A shows a top view of a prior art semiconductor PN junction structure.

Fig. 1B is a cross-sectional view showing the structure of a prior art semiconductor PN junction.

Figure 1C shows the depletion region formed by the prior art semiconductor PN junction structure.

Figure 1D shows the electric field strength distribution of a prior art semiconductor PN junction structure.

Fig. 2A is a top view showing the semiconductor PN junction of the first embodiment of the present invention.

Fig. 2B is a view showing an electric field simulation of the PN junction structure of the first embodiment of the present invention.

Figure 2C shows a comparison of the electric field strength and the depletion zone width of the first embodiment of the present invention with the prior art.

Figure 3 shows a top view of a semiconductor PN junction of another embodiment of the present invention.

Figure 4 is a top plan view showing a semiconductor PN junction of another embodiment of the present invention.

Fig. 5 is a top plan view showing a semiconductor PN junction of another embodiment of the present invention.

Figure 6 is a top plan view showing a semiconductor PN junction of another embodiment of the present invention.

Figures 7A and 7B show another embodiment of the present invention.

twenty one. . . P-type zone

twenty two. . . N-type zone

twenty three. . . Semiconductor PN junction

twenty four. . . Vacant area

D2. . . Depletion zone width

Claims (8)

A semiconductor PN junction structure comprising: a semiconductor substrate; and a PN junction formed by a P-type region and an N-type region being connected to each other in the semiconductor substrate; wherein the PN junction is viewed from above Having a staggered comb structure and having a plurality of comb-tooth structures under the surface of the semiconductor substrate. The semiconductor PN junction structure according to claim 1, wherein the comb structure comprises a rectangular, wavy, zigzag, or circular arc structure as viewed from above. The semiconductor PN junction structure according to claim 1, wherein the island-shaped impurity region of the opposite conductivity type is present in the P-type region or the N-type region. The semiconductor PN junction structure of claim 1, wherein the comb structure comprises a plurality of comb teeth, and when the PN junction is subjected to a reverse bias, the formed depletion regions are integrally connected. A semiconductor PN junction structure manufacturing method comprising: providing a semiconductor substrate; and implanting impurities to form a PN junction, wherein the PN junction is connected to the semiconductor substrate by a P-type region and an N-type region Formed; wherein the PN junction, viewed from a top view, has an interlaced comb structure and includes a plurality of comb structures under the surface of the semiconductor substrate. The method for fabricating a semiconductor PN junction structure according to claim 5, wherein the comb structure comprises a rectangular, wavy, zigzag, or circular arc structure as viewed from above. The method for fabricating a semiconductor PN junction structure according to claim 5, wherein the island-shaped impurity having an opposite conductivity type in the P-type region or the N-type region is used. Area. The method of fabricating a semiconductor PN junction structure according to claim 5, wherein the comb structure comprises a plurality of comb teeth, and when the PN junction is subjected to a reverse bias, the formed depletion regions are integrally connected.