TWI417004B - Interposer having through hole - Google Patents

Abstract

Disclosed is an interposer formed with a conductive through hole, the walls of the through holes having a first insulating layer, a second insulating layer formed on the first insulating layer, and a metallic material formed on the second insulating layer, wherein the material made of the first and second insulating layers are different, thereby enhancing the characteristics of anti-leakage and anti-surge as endurable to high voltage.

Description

Perforated interposer

The present invention relates to an interposer, and more particularly to an interposer having perforations.

Since IBM introduced the Flip Chip Package technology in the early 1960s, flip chip technology is characterized by the electrical connection between the semiconductor wafer and the substrate through the solder bumps compared to Wire Bond technology. Not a general gold line. The advantage of this flip chip technology is that the technology can increase the package density to reduce the size of the package component. At the same time, the flip chip technology does not need to use a long length of gold wire, thereby improving electrical performance. In view of this, the industry has used high-temperature solder on ceramic substrates, that is, Control-Collapse Chip Connection (C4), which has been used for many years. In recent years, due to the increasing demand for high-density, high-speed, and low-cost semiconductor components, and in response to the trend of shrinking the size of electronic products, flip-chip devices have been placed on low-cost organic circuit boards (for example, printed circuit boards or substrates). It has been explosively grown by filling the underside of the wafer with an underfill resin to reduce the thermal stress caused by the difference in thermal expansion between the structure of the germanium wafer and the organic circuit board.

In the current flip chip technology, an electronic pad is disposed on a surface of a semiconductor integrated circuit (IC) wafer, and the package substrate also has a corresponding flip chip, and the chip and the package substrate may be appropriately disposed. Solder bumps or other conductive solder materials are disposed on the package substrate in a face-down mode, wherein the solder bumps or conductive adhesive materials provide electrical input between the wafer and the package substrate /Output (I/O) and mechanical connections. When the package substrate and the semiconductor wafer are subsequently packaged, in order to provide electrical connection between the package substrate and an external electronic device (such as a circuit board), it is generally necessary to implant a plurality of solder balls on the bottom surface of the package substrate.

As electronic products become lighter, thinner, and more functionally demanding, the wiring density of the semiconductor wafer is becoming higher and higher, and the pitch of each of the flip-chip pads of the package substrate is smaller. .

At present, the distance between the flip-chip pads of the package substrate is in micrometer size, and cannot be effectively reduced to the size of the distance between the electrode pads of the corresponding wafer, resulting in a semiconductor wafer having a high line density, but it is not compatible. The substrate is packaged so that the electronic product cannot be efficiently produced.

In order to overcome the above problems, a splicing interposer 1 is further disposed between the package substrate 9 and the semiconductor wafer 8. As shown in FIG. 1, the cymbal interposer 1 has a cymbal body 10 and is disposed therethrough. A through-silicon via (TSV) 14 and a redistribution layer (RDL) 13 disposed on the top end of the crucible body 10 and the crucible hole 14 are disposed at the bottom end of the crucible. The conductive pad 92 is electrically coupled to the flip chip 90 of the package substrate 9 having a large pitch, and the uppermost layer of the circuit redistribution layer 13 has an electrical connection pad for electrically bonding by the solder bump 81. The electrode pads 80 of the semiconductor wafer 8 having a small pitch are formed into an encapsulant 7.

Thereby, the package substrate 9 can be bonded to the semiconductor wafer 8 having the high wiring density electrode pad 80 to achieve the purpose of integrating the semiconductor wafer 8 having a high wiring density. Therefore, the interposer 1 can solve the problem of lack of a package substrate that can be matched, and does not change the original supply chain and infrastructure of the IC industry.

At present, in the fabrication of the ruthenium perforation 14, an isolation layer 11 is formed on the wall of the perforation 14 of the crucible. As shown in FIG. 1B, the material is generally SiN _X , polymer, high temperature furnace or chemical gas. Phase deposition (CVD) produces SiO ₂ .

However, in the process of fabricating the insulating layer 11, there are some defects, for example, the process of chemical vapor deposition has the problem of leakage, the polymer has dielectric problems, the temperature of the high temperature furnace is too high, and the SiO is generated. _{2 The} material is too hard, or the insulating layer 11 has only a single material, which has problems of reliability and insulation.

Therefore, how to overcome the various problems in the above-mentioned prior art has become a problem that is currently being solved.

In view of the above-mentioned various deficiencies of the prior art, the present invention provides a perforated interposer having a first insulating layer, a second insulating layer formed on the first insulating layer, and a hole formed thereon. a metal material on the second insulating layer, and the materials of the first and second insulating layers are different.

In the aforementioned perforated interposer, the first and second insulating layers may extend onto the substrate of the perforated interposer. Alternatively, a first electrically isolating layer may be formed on the substrate.

As can be seen from the above, the perforated interposer of the present invention is formed on the wall of the conductive perforation to form an insulating layer of two materials, which has better anti-leakage and high voltage resistance than the single-material insulating layer of the prior art. And can improve the insulation and improve the reliability of electrical conduction.

The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. In the meantime, the terms "upper" and "one" as used in the specification are merely for convenience of description, and are not intended to limit the scope of the invention, and the relative relationship is changed or adjusted. Substantially changing the technical content is also considered to be within the scope of the invention.

Please refer to FIGS. 2A to 2H, which are cross-sectional views showing a first embodiment of the manufacturing method of the perforated interposer 2 of the present invention.

As shown in Figures 2A and 2A', a substrate 20 having opposing first and second surfaces 20a, 20b is provided. Next, an annular hole 200 is formed on the first surface 20a of the substrate 20, the annular hole 200 having a bottom portion 200a.

In this embodiment, the material of the substrate 20 may be glass, germanium wafer, metal, or polymer. Furthermore, the outline of the annular hole 200 may be circular or polygonal, and is not particularly limited.

As shown in FIG. 2B, a first insulating layer 21 is formed on the first surface 20a of the substrate 20 and the hole wall of the annular hole 200. Next, a first insulating layer 22 is formed on the first insulating layer 21 on the first surface 20a of the substrate 20, and the second insulating layer 22 is filled with the annular hole 200.

In this embodiment, the materials of the first and second insulating layers 21, 22 are different, and the first insulating layer 21 is a hard material, and the second insulating layer 22 is opposite to the first insulating layer 21. It is a soft material. Further, the material of the first and second insulating layers 21, 22 may be an organic material or an inorganic material such as an epoxy resin, SiN _X , SiO ₂ or the like.

As shown in FIG. 2C, an opening 220 corresponding to the annular hole 200 is formed on the second insulating layer 22, and the first insulating layer 21 in the opening 220 is removed to be exposed in the ring of the annular hole 200. The substrate 20 has a first surface 20a.

As shown in FIGS. 2D and 2D', the material of the substrate 20 in the opening 220 is removed, so that the annular hole 200 forms a through hole 201 that communicates with the first surface 20a of the substrate 20. The through hole 201 has a bottom portion 201a, and the hole 201 has a bottom portion 201a. The first and second insulating layers 21, 22 serve as the hole walls of the perforations 201.

As shown in FIG. 2E, a first wiring layer 23a is formed on the second insulating layer 22 on the first surface 20a of the substrate 20, and a metal material 240 is formed in the through hole 201 to form the conductive via 24. Next, a first protective layer 25a is formed on the second insulating layer 22 and the first wiring layer 23a.

In this embodiment, the first circuit layer 23a and the conductive via 24 are formed by electroplating, that is, the second insulating layer 22 on the first surface 20a of the substrate 20 and the second hole in the hole 201. A seed layer (not shown) is formed on the insulating layer 22, and the seed layer is used as a path for conducting current, and the metal material 240 is formed on the seed layer to form the first circuit layer 23a and Conductive perforations 24.

Furthermore, the conductive via 24 has a first end surface 24a corresponding to the first surface 20a and a second end surface 24b corresponding to the second surface 20b, and the first end surface 24a of the conductive via 24 is electrically connected to the first circuit layer. 23a, and the metal material 240 is attached to the bottom 201a of the through hole 201.

Moreover, the material of the conductive via 24 includes the metal material 240, the first and second insulating layers 21, 22. In addition, the conductive via 24 is hollow, and the first protective layer 25a is filled in the conductive via 24 .

As shown in FIG. 2F, a portion of the second surface 20b of the substrate 20 and the metal material 240 of the bottom portion 201a of the through hole 201 are removed to make the second surface 20b' of the substrate 20 and the second conductive via 24 The end face 24b is flush and the second end face 24b of the conductive via 24 is exposed.

As shown in FIG. 2G, an electrical isolation layer 26 is formed on the second surface 20b' of the substrate 20 to cover the first and second insulating layers 21, 22 of the conductive vias 24 to electrically isolate the electrical isolation layer. Layer 26 exposes a portion of second end face 24b of conductive via 24.

As shown in FIG. 2H, a second wiring layer 23b is formed on the electrical isolation layer 26, and the second wiring layer 23b is electrically connected to the second end surface 24b of the conductive via 24. Finally, a second protective layer 25b is formed on the electrical isolation layer 26 and the second wiring layer 23b, and a plurality of first and second openings 250a are formed on the first and second protective layers 25a, 25b. 250b, so that a part of the surfaces of the first and second circuit layers 23a, 23b are exposed to the first and second openings 250a, 250b.

Referring to Figures 3A through 3C, there is shown a cross-sectional view of a second embodiment of the method of making the perforated interposer 2' of the present invention. The difference between this embodiment and the first embodiment is only that the metal material 240 of the bottom portion 201a of the through hole 201 is retained, and other related processes are the same, so the same portions will not be described herein.

As shown in FIG. 3A, in the process of FIG. 2E, a first circuit layer 23a is formed on the second insulating layer 22 on the first surface 20a of the substrate 20, and a hollow conductive via 24' is formed. The bottom portion 201a of the through hole 201 has the metal material 240. Next, a first protective layer 25a is formed on the second insulating layer 22 and the first wiring layer 23a, and the first protective layer 25a is filled in the conductive via 24'.

As shown in FIG. 3B, part of the second surface 20b of the substrate 20 is removed from the first insulating layer 21 of the bottom 201a of the through hole 201, and the metal material 240 of the bottom 201a of the through hole 201 is left to make the conductive via 24 The second end face 24b' is exposed such that the metal material 240 covers the hollow of the second end face 24b' of the conductive via 24'.

As shown in FIG. 3C, an electrical isolation layer 26 is formed on the second surface 20b' of the substrate 20, and a second end surface 24b electrically connected to the conductive via 24' is formed on the electrical isolation layer 26. 'The second circuit layer 23b. Finally, a second protective layer 25b is formed on the electrical isolation layer 26 and the second wiring layer 23b.

4A to 4C are schematic cross-sectional views showing a third embodiment of the method for manufacturing the perforated interposer 2" of the present invention. The difference between the present embodiment and the first embodiment is only the structure of the conductive perforations 24", and the like. The related processes are the same, so the same part will not be described here.

As shown in FIG. 4A, in the process of FIG. 2E, a first circuit layer 23a is formed on the second insulating layer 22, and the metal material 240 is filled in the through hole 201 to form a conductive via 24" The first insulating layer 21, the second insulating layer 22, and the metal material 240 fill the conductive vias 24".

As shown in FIG. 4B, part of the material of the second surface 20b of the substrate 20 is removed such that the second end surface 24b" of the conductive via 24" is flush with the second surface 20b' of the substrate 20.

As shown in FIG. 4C, an electrical isolation layer 26 is formed on the second surface 20b' of the substrate 20, and a second end surface 24b electrically connected to the conductive via 24" is formed on the electrical isolation layer 26. The second circuit layer 23b. Finally, a second protective layer 25b is formed on the electrical isolation layer 26 and the second wiring layer 23b.

Accordingly, the present invention provides a perforated interposer 2, 2', 2" comprising: a substrate 20 having a first surface 20a and a second surface 20b' opposite thereto, and conductive vias 24, 24' disposed in the substrate 20. a first circuit layer 23a disposed on the first surface 20a of the substrate 20, a first protective layer 25a disposed on the first surface 20a of the substrate 20 and the first circuit layer 23a, An electrical isolation layer 26 on the second surface 20b' of the substrate 20, a second wiring layer 23b disposed on the electrical isolation layer 26, and a second wiring layer 23b disposed on the electrical isolation layer 26 and the second wiring layer 23b. Two protective layers 25b.

The substrate 20 is a ruthenium substrate having a perforated structure formed by the annular hole 200 and the through hole 201, and the first surface 20a has a first insulating layer 21 and is formed on the first insulating layer 21. A second insulating layer 22, wherein the materials of the first and second insulating layers 21, 22 are different, such as the first insulating layer 21 is a hard material, and the second insulating layer 22 is a soft material.

The conductive vias 24, 24', 24" are formed in the through-hole structure and communicate with the first and second surfaces 20a, 20b' of the substrate 20, and have a first end surface 24a corresponding to the first surface 20a, 24a" and a second end surface 24b, 24b', 24b" corresponding to the second surface 20b', and the first and second insulating layers 21, 22 are further extended into the perforated structure as the conductive via 24, 24' The 24" hole wall structure is such that a metal material 240 is disposed on the second insulating layer 22 in the perforated structure.

The first circuit layer 23a is disposed on the second insulating layer 22 on the first surface 20a of the substrate 20, and is electrically connected to the first end faces 24a, 24a of the conductive vias 24, 24', 24" .

The first protective layer 25a is disposed on the second insulating layer 22 on the first surface 20a of the substrate 20.

The electrical isolation layer 26 covers the first and second insulating layers 21, 22 of the conductive vias 24, 24', 24" to expose a portion of the second end of the conductive vias 24, 24', 24" 24b, 24b', 24b".

The second circuit layer 23b is electrically connected to the second end faces 24b, 24b', 24b" of the conductive vias 24, 24', 24".

Furthermore, in the first and second embodiments, the conductive vias 24, 24' are hollow, such that the first protective layer 25a is filled in the conductive vias 24, 24'. For example, in the first embodiment, the first protective layer 25a communicates with the first end surface 24a and the second end surface 24b of the conductive via 24, and in the second embodiment, the metal material 240 covers the conductive via 24' The hollow of the second end face 24b'.

In addition, in the third embodiment, the first insulating layer 21, the second insulating layer 22, and the metal material 240 fill the conductive vias 24".

Please refer to FIGS. 5A to 5H, which are cross-sectional views showing a fourth embodiment of the manufacturing method of the perforated interposer 3 of the present invention. The difference between this embodiment and the first embodiment is only in the structure on the first surface 30a of the substrate 30, and other related processes are the same, so the same portions will not be described herein.

As shown in FIG. 5A, a structure as shown in FIG. 2B is provided, that is, an annular hole 300 is formed on a substrate 30 having a first surface 30a and a second surface 30b opposite to each other, the annular hole 300 having a bottom portion 300a, and A first insulating layer 31 is formed on the first surface 30a of the substrate 30 and the hole wall of the annular hole 300, and a second insulating layer 32 is formed on the first insulating layer 31 and the annular hole 300.

As shown in FIGS. 5B and 5B', the first insulating layer 31 and the second insulating layer 32 on the first surface 30a of the substrate 30 are removed, and only the first insulating layer 31 and the second of the annular holes 300 are retained. Insulation layer 32.

As shown in FIG. 5C, a first electrical isolation layer 36a is formed on the first surface 30a of the substrate 30, and the first electrical isolation layer 36a has an opening 360 corresponding to the annular hole 300 to expose the The first surface 30a of the substrate 30 within the ring of the annular aperture 300.

As shown in FIG. 5D, the material of the substrate 30 in the opening 360 is removed, so that the annular hole 300 forms a through hole 301 communicating with the first surface 30a of the substrate 30. The through hole 301 has a bottom portion 301a, and the first The second insulating layer 31, 32 serves as a hole wall of the through hole 301.

As shown in FIG. 5E, a first wiring layer 33a is formed on the first electrical isolation layer 36a, and a metal material 340 is plated in the via 301 to form conductive vias 34. Next, a first protective layer 35a is formed on the first electrical isolation layer 36a and the first wiring layer 33a.

In this embodiment, the conductive via 34 has a first end surface 34a corresponding to the first surface 30a and a second end surface 34b corresponding to the second surface 30b, and the first end surface 34a of the conductive via 34 is electrically connected to the first end surface 34a. A wiring layer 33a, and the bottom 301a of the through hole 301 has the metal material 340.

Furthermore, the conductive vias 34 include the metal material 340, the first and second insulating layers 31, 32, and the conductive vias 34 are hollow, so that the first protective layer 35a is filled in the conductive vias 34.

As shown in FIG. 5F, a portion of the second surface 30b of the substrate 30 and the metal material 340 of the bottom portion 301a of the through hole 301 are removed, and the second surface 30b' of the substrate 30 and the second end surface of the conductive via 34 are removed. 34b is flush to expose the second end face 34b of the conductive via 34.

As shown in FIG. 5G, a second electrical isolation layer 36b is formed on the second surface 30b' of the substrate 30, and the first and second insulating layers 31, 32 of the conductive vias 34 are covered to make the second The electrical isolation layer 36b exposes a portion of the second end face 34b of the conductive via 34.

As shown in FIG. 5H, a second wiring layer 33b is formed on the second electrical isolation layer 36b, and the second wiring layer 33b is electrically connected to the second end surface 34b of the conductive via 34. Finally, a second protective layer 35b is formed on the second electrical isolation layer 36b and the second wiring layer 33b, and a plurality of first and second openings are formed on the first and second protective layers 35a, 35b. 350a, 350b, such that portions of the first and second circuit layers 33a, 33b are exposed to the first and second openings 350a, 350b.

Referring to Figures 6A through 6C, there is shown a cross-sectional view of a fifth embodiment of the method of making the perforated interposer 3' of the present invention. The difference between this embodiment and the fourth embodiment is only that the metal material 340 of the bottom portion 301a of the through hole 301 is retained, and other related processes are the same, so the same portions will not be described herein.

As shown in FIG. 6A, in the process of FIG. 5E, a first circuit layer 33a is formed on the first electrical isolation layer 36a, and the hollow conductive via 34' is formed, and the bottom 301a of the via 301 is formed. The upper layer has the metal material 340. Next, a first protective layer 35a is formed on the first electrical isolation layer 36a and the first wiring layer 33a, and the first protective layer 35a is filled in the conductive vias 34'.

As shown in FIG. 6B, a portion of the second surface 30b of the substrate 30 is removed from the first insulating layer 31 of the bottom portion 301a of the through hole 301, and the metal material 340 of the bottom portion 301a of the through hole 301 is left to make the conductive via 34. The second end face 34b' is exposed such that the metal material 340 covers the hollow of the second end face 34b' of the conductive via 34'.

As shown in FIG. 6C, a second electrical isolation layer 36b is formed on the second surface 30b' of the substrate 30, and a conductive via 34' is electrically connected to the second electrical isolation layer 36b. The second wiring layer 33b of the second end face 34b'. Finally, a second protective layer 35b is formed on the second electrical isolation layer 36b and the second wiring layer 33b.

7A to 7C are schematic cross-sectional views showing a sixth embodiment of the method for manufacturing the perforated interposer 3" of the present invention. The difference between this embodiment and the fourth embodiment lies only in the structure of the conductive perforations 34", and other The related processes are the same, so the same part will not be described here.

As shown in FIG. 7A, in the process of FIG. 5E, a first circuit layer 33a is formed on the first electrical isolation layer 36a, and the metal material 340 is filled in the via hole 301 to form a conductive via. 34", the first insulating layer 31, the second insulating layer 32 and the metal material 340 fill the conductive vias 34".

As shown in FIG. 7B, a portion of the second surface 30b of the substrate 30 is removed from the first insulating layer 31 of the bottom portion 301a of the through hole 301, so that the second end surface 34b" of the conductive via 34" and the substrate 30 are The second surface 30b' is flush.

As shown in FIG. 7C, a second electrical isolation layer 36b is formed on the second surface 30b' of the substrate 30, and a conductive via 34" is electrically connected to the second electrical isolation layer 36b. The second wiring layer 33b of the second end face 34b". Finally, a second protective layer 35b is formed on the second electrical isolation layer 36b and the second wiring layer 33b.

Therefore, the present invention provides another perforated interposer 3, 3', 3" comprising: a substrate 30 having a first surface 30a and a second surface 30b' opposite thereto, and conductive vias 34, 34 disposed in the substrate 30. a first electrical isolation layer 36a disposed on the first surface 30a of the substrate 30, a first wiring layer 33a disposed on the first electrical isolation layer 36a, and the first electrical layer The first protective layer 35a on the isolation layer 36a and the first circuit layer 33a, the second electrical isolation layer 36b disposed on the second surface 30b' of the substrate 30, and the second electrical isolation layer 36b are disposed on the second electrical isolation layer 36b. The second wiring layer 33b and the second protective layer 35b provided on the second electrical isolation layer 36b and the second wiring layer 33b.

The substrate 30 is a ruthenium substrate and has a perforated structure composed of the annular hole 300 and the through hole 301.

The conductive vias 34, 34', 34" are formed in the through-hole structure and communicate with the first and second surfaces 30a, 30b' of the substrate 30, and have a first end surface 34a corresponding to the first surface 30a, 34a" and a second end surface 34b, 34b', 34b" corresponding to the second surface 30b', and the hole wall of the perforated structure sequentially has a first insulating layer 31, a second insulating layer 32 and a metal The material of the first and second insulating layers 31, 32 is different, for example, the first insulating layer 31 is a hard material, and the second insulating layer 32 is a soft material.

The first electrical isolation layer 36a covers the first and second insulating layers 31, 32 of the conductive vias 34, 34', 34" to expose the first end of the conductive vias 34, 34', 34" 34a, 34a".

The first circuit layer 33a is electrically connected to the first end faces 34a, 34a" of the conductive vias 34, 34', 34".

The second electrical isolation layer 36b covers the first and second insulating layers 31, 32 of the conductive vias 34, 34', 34" to expose a portion of the conductive vias 34, 34', 34" End faces 34b, 34b', 34b".

The second circuit layer 33b is electrically connected to the second end faces 34b, 34b', 34b" of the conductive vias 34, 34', 34".

Furthermore, in the fourth and fifth embodiments, the conductive vias 34, 34' are hollow, such that the first protective layer 35a is filled in the conductive vias 34, 34'. For example, in the fourth embodiment, the first protective layer 35a communicates with the first end surface 34a and the second end surface 34b of the conductive via 34. In the fifth embodiment, the metal material 340 covers the conductive via 34'. The hollow of the second end face 34b'.

In addition, in the sixth embodiment, the first insulating layer 31, the second insulating layer 32, and the metal material 340 fill the conductive vias 34".

In summary, the perforated interposer of the present invention mainly has two kinds of insulating materials on the hole wall of the conductive perforation, so as to have better anti-leakage and high-voltage resistance characteristics, and improve insulation and enhance electrical conduction. Reliability.

Furthermore, the perforated interposer of the present invention is a low-cost manufacturing technique, which is advantageous for mass production.

The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

10‧‧‧ boards

12‧‧‧First connector

13‧‧‧Fixed holes

20‧‧‧Electronic component fixture

22‧‧‧ Subject

23‧‧‧Connecting Department

24‧‧‧Extension block

25‧‧‧Elastic block

251‧‧‧The top block

26‧‧‧Cantilever

28‧‧‧Flexible hook

282‧‧‧ Guide surface

30‧‧‧Electronic components

32‧‧‧Second connector

33‧‧‧Perforation

1A is a schematic cross-sectional view of a package of a conventional package substrate, a semiconductor wafer, and a germanium interposer;

1B is a partial enlarged cross-sectional view of a conventional 矽 interposer;

2A to 2H are schematic cross-sectional views showing a first embodiment of the method for manufacturing a perforated interposer according to the present invention; wherein the 2A' and 2D' are respectively a top view of the 2A and 2D views;

3A to 3C are schematic cross-sectional views showing a second embodiment of the method for manufacturing the perforated interposer of the present invention;

4A to 4C are schematic cross-sectional views showing a third embodiment of the method for manufacturing a perforated interposer of the present invention;

5A to 5H are schematic cross-sectional views showing a fourth embodiment of the method for manufacturing a perforated interposer according to the present invention; wherein, the fifth B' is a top view of the fifth panel;

6A to 6C are schematic cross-sectional views showing a fifth embodiment of the method for manufacturing the perforated interposer of the present invention;

7A to 7C are schematic cross-sectional views showing a sixth embodiment of the method of manufacturing the perforated interposer of the present invention.

2‧‧‧Perforation Intermediary Board

20‧‧‧Substrate

20a‧‧‧ first surface

20b’‧‧‧ second surface

21‧‧‧First insulation

22‧‧‧Second insulation

23a‧‧‧First circuit layer

23b‧‧‧Second circuit layer

24‧‧‧Electrical perforation

24a‧‧‧ first end

24b‧‧‧second end face

240‧‧‧Metal

25a‧‧‧First protective layer

25b‧‧‧Second protective layer

250a‧‧‧first opening

250b‧‧‧second opening

26‧‧‧Electrical isolation

Claims (16)

A perforation interposer includes:
The substrate has a first surface and a second surface opposite to each other, and a perforated structure connecting the first surface and the second surface, and the first surface of the substrate has a first insulating layer and is formed on the first insulating layer The second insulating layer is different from the materials of the first and second insulating layers;
Conductive perforations are formed in the perforated structure, and the first and second insulating layers extend into the perforated structure to serve as a hole wall structure of the conductive perforation, the conductive perforation having a first end surface corresponding to the first surface a metal material corresponding to the second end surface corresponding to the second surface and the second insulating layer disposed in the perforated structure;
The first circuit layer is disposed on the second insulating layer on the first surface of the substrate, and electrically connected to the first end surface of the conductive via;
a first protective layer is disposed on the first insulating layer on the first surface of the substrate and the first circuit layer;
An electrical isolation layer is disposed on the second surface of the substrate and exposing the second end surface of the conductive via;
The second circuit layer is disposed on the electrical isolation layer and electrically connected to the second end surface of the conductive via; and the second protective layer is disposed on the electrical isolation layer and the second circuit layer. The perforated interposer of claim 1, wherein the electrical isolation layer covers the first and second insulating layers on the second end surface of the conductive via. The perforated interposer of claim 1, wherein the conductive perforation is hollow. The perforated interposer of claim 3, wherein the first protective layer is refilled in the conductive via. The perforated interposer of claim 4, wherein the first protective layer communicates with the first end surface and the second end surface of the conductive perforation. The perforated interposer of claim 4, wherein the metal material covers the second end surface of the electrically conductive perforation. The perforated interposer of claim 1, wherein the metal material fills the conductive perforation, and the metal material is made of copper. The perforated interposer of claim 1, wherein the first insulating layer is a hard material, and the second insulating layer is a soft material relative to the first insulating layer. A perforation interposer includes:
The substrate has a first surface and a second surface opposite to each other, and a perforated structure connecting the first surface and the second surface;
Conductive perforations are formed in the perforated structure, the conductive perforations having a first end surface corresponding to the first surface and a second end surface corresponding to the second surface, and the perforated structure has a first insulating layer on the wall of the hole, a second insulating layer formed on the first insulating layer and a metal material formed on the second insulating layer, wherein the materials of the first and second insulating layers are different;
The first electrical isolation layer is disposed on the first surface of the substrate and exposes the first end surface of the conductive via;
The first circuit layer is disposed on the first electrical isolation layer and electrically connected to the first end surface of the conductive via;
a first protective layer is disposed on the first electrical isolation layer and the first circuit layer;
The second electrical isolation layer is disposed on the second surface of the substrate and exposes the second end surface of the conductive via;
a second circuit layer is disposed on the second electrical isolation layer and electrically connected to the second end surface of the conductive via; and a second protection layer is disposed on the second electrical isolation layer and the second line On the floor. The perforated interposer of claim 9, wherein the first and second electrically insulating layers respectively cover the first and second insulating layers on the first and second end faces of the conductive via. The perforated interposer of claim 9, wherein the conductive perforation is hollow. The perforated interposer of claim 11, wherein the first protective layer is refilled in the conductive via. The perforated interposer of claim 12, wherein the first protective layer communicates with the first end surface and the second end surface of the conductive via. The perforated interposer of claim 13, wherein the metal material covers the second end surface of the electrically conductive perforation. The perforated interposer of claim 9, wherein the metal material fills the conductive perforation, and the metal material is made of copper. The perforated interposer of claim 9, wherein the first insulating layer is a hard material, and the second insulating layer is a soft material relative to the first insulating layer.