TWI416889B - Hd physical layer of a wireless communication device - Google Patents

Abstract

A radio frequency (RF) transmitter is coupled to and controlled by a processor to transmit data. A physical layer circuit is coupled to the RF transmitter to encode and decode between a digital signal and a modulated analog signal. The physical layer circuit comprises a high ate physical layer circuit (HRP) and a low rate physical layer circuit (LRP). The low rate channels generated by the low rate physical layer circuit (LRP) share a same frequency band as a corresponding high rate channel generated by the high rate physical layer circuit (HRP).

Description

HD physical layer of wireless communication device

The present invention relates to the field of wireless communications; more specifically, the present invention relates to a wireless communication device using adaptive beamforming.

In 1998, the Digital Display Working Group (DDWG) was formed to replace the analog video graphics interface card (VGA) connection standard by establishing a common interface standard between the computer and the display. The resulting standard is the Digital Video Interface (DVI) specification issued in April 1999.

There are several content protection mechanisms available. For example, High Frequency Wide Digital Content Protection (HDCP) and Digital Transmission Content Protection (DTCP) are well known content protection mechanisms. It is recommended to use HDCP as a security component of DVI and design HDCP for the digital video monitor interface.

The High Definition Multimedia Audio Interface (HDMI) is a connectivity interface standard developed to meet the explosive demand for high definition audio and video. HDMI is capable of carrying video and audio and is compatible with DVI (which only carries video signals). The main advantage of DVI and HDMI is that both can transmit uncompressed high definition digital bit streams over a single cable.

HDCP is a system for protecting content transmitted on DVI and HDMI from being copied. See HDCP 1.0 for details. HDCP provides authentication, encryption and revocation. The dedicated circuitry in the playback device and display monitor encrypts the video data and sends it out. With HDCP, content is encrypted immediately before (or inside) the DVI or HDMI transmitter chip and decrypted immediately after (or inside) the DVI or HDMI receiver chip.

In addition to the encryption and decryption functions, the HDCP performs authentication to verify that the receiving device (eg, display, television, etc.) is authorized to receive the encrypted content. Re-authentication is performed approximately every two seconds to continuously confirm the security of the DVI or HDMI interface. At any one time, if re-authentication does not occur by, for example, disconnecting the device and/or connecting an illegal recording device, the source device (eg, a digital versatile disc (DVD) player, a video converter) Etc.) End the transfer of encrypted content.

While the discussion of HDMI and DVI is generally focused on wired communications, the use of wireless communications to transmit content has become increasingly popular. Although there is currently a lot of attention to cellular technology and wireless networks, there is an increasing interest in unlicensed spectrum near 60 GHz for wireless video transmission or very high speed network connections. More specifically, in the United States and Japan, the adjacent bandwidth of 7 GHz has been opened for unauthorized use at millimeter wave frequencies around 60 GHz.

A radio frequency (RF) transmitter is coupled to and controlled by the processor to transmit data. A physical layer circuit is coupled to the RF transmitter to encode and decode between a digital signal and a modulation analog signal. The physical layer circuit includes a high rate physical layer circuit (HRP) and a low rate physical layer circuit (LRP). The low rate channel generated by the low rate physical layer circuit (LRP) shares the same frequency band as the corresponding high rate channel generated by the high rate physical layer circuit (HRP).

An apparatus and method for wireless communication is disclosed. In one embodiment, wireless communication is performed using a wireless communication transceiver with an adaptive beamforming antenna. As is apparent to those skilled in the art, wireless communication can be performed using a wireless receiver or transmitter.

In an embodiment, the wireless communication includes an additional link or channel for transmitting information between the transmitter and the receiver. This link can be unidirectional or bidirectional. In one embodiment, the channel is used to transmit antenna information from the receiver back to the transmitter, thereby enabling the transmitter to adapt its antenna array to find the path in the other direction by manipulating the antenna elements. This approach avoids obstacles.

In an embodiment, the link is also used to transmit information corresponding to wirelessly transmitted content (eg, wireless video). This information can be content protection information. For example, in one embodiment, the link is used to transmit an encryption key and an encryption key confirmation when the transceiver transmits the HDMI material. Thus, in an embodiment, the link transmits control information and content protection information.

This extra link can be an independent channel in the 60 GHz band. In an alternate embodiment, the link can be a wireless channel in the 2.4 GHz or 5 GHz band.

In the following description, numerous details are set forth to provide a more comprehensive explanation of the invention. However, the invention may be practiced without these specific details, as will be apparent to those skilled in the art. In other instances, well-known structures and devices are shown in the form of block diagrams and are not shown in detail in order to avoid obscuring the invention.

Some portions of the detailed description that follows are presented in terms of calculations and symbolic representations of operations performed on data bits in computer memory. These calculus descriptions and representations are used by those skilled in the art to communicate the nature of their work most effectively to those skilled in the art. The algorithm is here and is generally envisaged as a self-consistent sequence of steps leading to the desired result. These steps are steps that require physical manipulation of physical quantities. Usually, though not necessarily, such quantities are in the form of an electrical or magnetic signal that can be stored, transferred, combined, compared and otherwise manipulated. In principle, it has proven convenient at times, principally, to refer to such signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

However, it should be borne in mind that all such and similar terms should be combined with the appropriate physical quantities and are merely the convenience of the application. Unless otherwise expressly stated (as will be apparent from the description below), it should be understood that throughout the description, such as "processing" or "computing" or "calculating" or "determining" or "displaying" or The discussion of the terms of the analogy refers to the behavior and process of a computer system or similar electronic computing device, which is expressed as a physical (electronic) amount of data in a computer system register and memory. The location is expressed as computer system memory or scratchpad or other such information to store, transmit or display other physical quantities of the device.

The invention also relates to an apparatus for performing the operations herein. The device may be specially constructed for the desired purpose, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. The computer program can be stored in a computer readable storage medium such as, but not limited to, any type of disc, including a floppy disk, a compact disc, a compact disc-read only memory (CD-ROM), and a magneto-optical disc. Memory (ROM), random access memory (RAM), erasable programmable read only memory (EPROM), electronically erasable programmable read only memory (EEPROM), magnetic or optical card or any type Suitable for storing media of electronic instructions, and each of the media is coupled to a computer system bus.

The algorithms and displays presented in this article are not intrinsically related to any particular computer or other device. Various general purpose systems may be utilized in conjunction with the programs taught herein, or more specialized apparatus may be conveniently constructed for performing the required method steps. The structures required for a variety of such systems will appear from the description below. Moreover, the invention is not described in reference to any particular programming language. It will be appreciated that the teachings of the present invention as described herein can be implemented using a variety of programming languages.

A machine-readable medium includes any mechanism for storing or transmitting information in a form readable by a machine (eg, a computer). By way of example, a machine-readable medium includes only memory ("ROM"); random access memory ("RAM"); disk storage media; optical storage media; flash memory devices; electrical, optical, acoustic Or other forms of propagating signals (eg, carrier waves, infrared signals, digital signals, etc.).

An example of a communication system

1 is a block diagram of one embodiment of a communication system. Referring to FIG. 1, the system includes a media receiver 100, a media receiver interface 102, a transmitting device 140, a receiving device 141, a media player interface 113, a media player 114, and a display 115.

Media receiver 100 receives content from a source (not shown). In an embodiment, the media receiver 100 includes a video converter. The content may include baseband digital video such as, but not limited to, content conforming to the HDMI or DVI standard. In this case, media receiver 100 can include a transmitter (eg, an HDMI transmitter) to forward the received content.

The media receiver 100 transmits the content 101 to the transmitter device 140 via the media receiver interface 102. In an embodiment, the media receiver interface 102 includes logic to convert the content 101 to HDMI content. In this case, the media receiver interface 102 can include an HDMI plug and the content 101 is transmitted via a wired connection; however, it can be transmitted via a wireless connection. In another embodiment, the content 101 contains DVI content.

In one embodiment, the transfer of content 101 between the media receiver interface 102 and the transmitter device 140 is performed over a wired connection; however, the transfer can occur via a wireless connection.

Transmitter device 140 wirelessly transmits information to receiver device 141 using two wireless connections. One of the wireless connections is via a phased array antenna with adaptive beamforming. Another wireless connection is via wireless communication channel 107, referred to herein as a back channel. In an embodiment, the wireless communication channel 107 is unidirectional. In an alternate embodiment, the wireless communication channel 107 is bidirectional.

The receiver device 141 transmits the content received from the transmitter device 140 to the media player 114 via the media player interface 113. In one embodiment, content transfer between the receiver device 141 and the media player interface 113 is via a wired connection; however, the transfer can occur via a wireless connection. In an embodiment, the media player interface 113 includes an HDMI plug. Similarly, content transfer between the media player interface 113 and the media player 114 is via a wired connection; however, the transfer can occur via a wireless connection.

The media player 114 causes the content to be played on the display 115. In one embodiment, the content is HDMI content, and the media player 114 transmits the media content to the display via a wired connection; however, the transfer can occur via a wireless connection. Display 115 can include a plasma display, a liquid crystal display (LCD), a cathode ray tube (CRT), and the like.

Note that the system of Figure 1 can be modified to include a DVD player/recorder instead of a DVD player/recorder for receiving and playing and/or recording the content.

In an embodiment, transmitter 140 and media receiver interface 102 are part of media receiver 100. Similarly, in one embodiment, receiver 140, media player interface 113, and media player 114 are all part of the same device. In an alternate embodiment, receiver 140, media player interface 113, media player 114, and display 115 are all part of the display. An example of such a device is shown in Figure 3.

In one embodiment, the transmitter device 140 includes a processor 103, an optional baseband processing component 104, a phased array antenna 105, and a wireless communication channel interface 106. Phased array antenna 105 includes a radio frequency (RF) transmitter having a digitally controlled phased array antenna coupled to processor 103 and controlled by processor 103 to transmit content to receive using adaptive beamforming Device 141.

In one embodiment, the receiver device 141 includes a processor 112, an optional baseband processing component 111, a phased array antenna 110, and a wireless communication channel interface 109. Phased array antenna 110 includes a radio frequency (RF) transmitter having a digitally controlled phased array antenna coupled to processor 112 and controlled by processor 112 for use with adaptive beamforming from the transmitter device 140 receives the content.

In one embodiment, processor 103 generates baseband signals that are processed by baseband signal processing 104 prior to wireless transmission by phased array antenna 105. In this case, the receiver device 141 includes baseband signal processing to convert the analog signal received by the phased array antenna 110 into a baseband signal processed by the processor 112. In an embodiment, the baseband signal is an orthogonal frequency division multiplexing (OFDM) signal. In one embodiment, the baseband signal is a single carrier phase, amplitude, or phase and amplitude modulated signal.

In an embodiment, transmitter device 140 and/or receiver device 141 are part of a separate transceiver.

Transmitter device 140 and receiver device 141 perform wireless communication using a phased array antenna with adaptive beamforming that allows beam steering. Beamforming is well known in the art. In one embodiment, the processor 103 sends digital control information to the phased array antenna 105 to indicate the amount used to offset one or more phase shifters in the phased array antenna 105, thereby manipulating the technique A beam formed by a method well known to the public. Processor 112 also uses digital control information to control phased array antenna 110. The digital control information is transmitted using the control channel 121 in the transmitter device 140 and the control channel 122 in the receiver device 141. In an embodiment, the digital control information includes a set of coefficients. In one embodiment, each of processors 103 and 112 includes a digital signal processor.

A wireless communication link interface 106 is coupled to the processor 103 and provides an interface between the wireless communication link 107 and the processor 103 to convey antenna information about the use of the phased array antenna and to convey information to facilitate Play content at one location. In an embodiment, the information transmitted between the transmitter device 140 and the receiver device 141 to facilitate playback of the content includes: an encryption key sent from the processor 103 to the processor 112 of the receiver device 141 and one or A plurality of acknowledgments from the processor 112 of the receiver device 141 are sent to the processor 103 of the transmitter device 140.

Wireless communication link 107 also transmits antenna information between transmitter device 140 and receiver device 141. During initialization of phased array antennas 105 and 110, wireless communication link 107 transmits information to enable processor 103 to select direction for phased array antenna 105. In one embodiment, the information includes, but is not limited to, antenna position information and performance information corresponding to the antenna position, such as one or more pairs of signals including the position of the phased array antenna 110 and the channel used for the antenna positioning. Strength data. In another embodiment, the information includes, but is not limited to, transmitted by processor 112 to processor 103 to enable processor 103 to determine which portions of phased array antenna 105 are used to convey information of the content.

The wireless communication link 107 transmits a pair of processors 112 from the receiver device 141 when the phased array antennas 105 and 110 are operating in a mode in which the antennas can transmit content (e.g., HDMI content) during operation in the mode. An indication of the status of the communication path. The indication of the communication status includes an indication from the processor 112 that causes the processor 103 to steer the beam in another direction (e.g., to another channel). This facilitates the response to interference with the transmission of portions of the content. This information may specify that one or more alternate channels may be used by processor 103.

In one embodiment, the antenna information includes information transmitted by the processor 112 to specify a location, and the receiver device 141 will direct the phased array antenna 110 to the location. This mode is available during initialization, when the transmitter device 140 informs the receiver device 141 where to locate its antenna for signal quality measurements to identify the best channel. The specified location may be an exact location or may be a relative location, for example, one of the predetermined location sequences followed by the transmitter device 140 and the receiver device.

In one embodiment, the wireless communication link 107 transmits information from the receiver device 141 to the transmitter device 140 to specify the antenna characteristics of the phased array antenna 110 or vice versa.

An example of a transceiver architecture

2 is a block diagram of one embodiment of an adaptive beamforming multi-antenna radio system including the transmitter device 140 and the receiver device 141 of FIG. Transceiver 200 includes a plurality of independent transmit and receive chains. Transceiver 200 performs phased array beamforming using a phased array of identical RF signals and offsets the phase of one or more antenna elements in the array to achieve beam steering.

Referring to Figure 2, a digital signal processor (DSP) 201 formats the content and produces an instantaneous baseband signal. The DSP 201 provides modulation, FEC coding, package matching, interleaving, and automatic gain control.

The DSP 201 then forwards the baseband signal to be modulated on the RF portion of the transmitter and transmitted out. In one embodiment, the content is modulated into an OFDM signal in a manner well known in the art.

A digital/analog converter (DAC) 202 receives the digital signal output from the DSP 201 and converts it to an analog signal. In one embodiment, the signal output from DAC 202 is a signal between 0 MHz and 256 MHz. In an alternate embodiment, the signal output from DAC 202 is a signal between 0 MHz and 750 MHz.

Mixer 203 receives the signal output from DAC 202 and combines it with the signal from local oscillator (LO) 204. The signal output from the mixer 203 is at an intermediate frequency. In an embodiment, the intermediate frequency is between 2 GHz and 15 GHz.

A plurality of phase shifters 205 _0-N receive the output from the mixer 203. A double downconverter is included to control which phase shifters receive signals. In an embodiment, the phase shifters are quantized phase shifters. In an alternate embodiment, the phase shifters can be replaced by a complex multiplier. In one embodiment, DSP 201 also controls the phase and magnitude of the current in each of the antenna elements in phased array antenna 220 via control channel 208, in a manner well known in the art. Produce the desired beam pattern. In other words, DSP 201 controls phase shifters 205 _0-N of phased array antenna 220 to produce the desired pattern.

Each of the phase shifters 205 _0-N produces an output that is sent to one of the power amplifiers 206 _0-N that amplifies the signal. The amplified signal is sent to an antenna array 207 having a plurality of antenna elements 207 _0-N . In one embodiment, the signal transmitted from antennas 207 _0-N is a radio frequency signal between 56 GHz and 64 GHz. Therefore, a plurality of beams are output from the phased array antenna 220.

For the receiver, antennas 210 _0-N receive wireless transmissions from antennas 207 _0-N and provide them to phase shifters 211 _0-N . As discussed above, in one embodiment, phase shifters 211 _0-N include quantized phase shifters. Alternatively, the phase shifters 211 _0-N may be replaced by a complex multiplier. Phase shifters 211 _0-N receive signals from antennas 210 _0-N that are combined to form a single feed line output. In one embodiment, a multiplexer is used to combine signals from different components and output the single feed. The output of phase shifter 211 _0-N is input to an intermediate frequency (IF) amplifier 212, which reduces the frequency of the signal to an intermediate frequency. In an embodiment, the intermediate frequency is between 2 GHz and 9 GHz.

Mixer 213 receives the output of IF amplifier 212 and combines it with the signal from LO 214 in a manner well known in the art. In one embodiment, the output of mixer 213 is a signal in the range of 0 MHz to about 250 MHz. In one embodiment, each channel has an I and Q signal. In an alternate embodiment, the output of mixer 213 is a signal in the range of 0 MHz to about 750 MHz.

An analog/digital converter (ADC) 215 receives the output of mixer 213 and converts it to digital form. The digital output from ADC 215 is received by DSP 216. The DSP 216 restores the amplitude and phase of the signal. The DSP 201 can provide demodulation, packet disassembly, deinterlacing, FEC decoding, and automatic gain control.

In one embodiment, each of the transceivers includes a control microprocessor that establishes control information for the DSP. The control microprocessor can be on the same die as the DSP.

DSP-controlled adaptive beamforming

In one embodiment, the DSP implements an adaptive algorithm that enables beamforming weighting to be implemented in hardware. That is, the transmitter and receiver work together to perform beamforming in the RF frequency using a digitally controlled analog phase shifter; however, in an alternate embodiment, beamforming is performed in the IF. Phase shifters 205 _0-N and 211 _0-N are controlled via control channel 208 and control channel 217 via their respective DSPs in a manner well known in the art. For example, DSP 201 controls phase shifters 205 _0-N to cause the transmitter to perform adaptive beamforming to steer the beam, while DSP 201 controls phase shifters 211 _0-N to direct the antenna elements to receive wireless transmissions from the antenna elements and Signals from different components are combined to form a single feeder output. In one embodiment, a multiplexer is used to combine signals from different components and output the single feed.

The DSP 201 performs beam steering by pulse or excitation, and a suitable phase shifter is connected to each antenna element. The pulse algorithm under DSP 201 controls the phase and gain of each component. Phased array beamforming to perform DSP control is well known in the art.

Adaptive beamforming antennas are used to avoid interference barriers. By adapting beamforming and steering the beam, communication can be avoided without hindering the wireless transmission between the transmitter and the receiver.

In an embodiment, with respect to an adaptive beamforming antenna, it has three phases of operation. The three operational phases are the training phase, the search phase, and the tracking phase. The training phase and the search phase are performed during the initialization period. The training phase determines the spatial field type with a predetermined sequence { }and{ } channel overview. Calculate candidate spatial patterns in the search phase { },{ a list of } and choose a preferred { , } for data transfer between a transmitter of one transceiver and a receiver of another transceiver. The tracking phase keeps track of the strength of the candidate list. When the first choice is blocked, select the next pair of spatial field types to use.

In an embodiment, during the training phase, the transmitter transmits a sequence of spatial patterns to the outside { }. For each spatial field type { }, the receiver projects the received signal to another sequence of scenes { }on. The result of the projection is: at { },{ On the opposite side, get the channel overview.

In an embodiment, thorough training is performed between the transmitter and the receiver, wherein the antenna of the receiver is positioned at all locations and the transmitter transmits a plurality of spatial patterns. Thorough training is well known in the art. In this case, the M transmission spatial patterns are transmitted by the transmitter and the N received spatial patterns are received by the receiver to form an N x M channel matrix. Thus, the transmitter traverses the field pattern of the transmission sector and the receiver searches for the strongest signal for the transmission. The transmitter then moves to the next sector. At the end of the thorough search process, the grading of all locations of the transmitter and receiver and the signal strength of the channels at their locations are obtained. The information remains paired with the location of the antenna and the signal strength of the channel. This list can be used to manipulate the antenna beam in the presence of interference.

In an alternate embodiment, two-segment training is used in which the transmitted orthogonal antenna pattern divides the space into successive narrow segments to obtain a channel profile.

It is assumed that the DSP 101 is in a steady state and the direction in which the antenna should be pointed has been determined. In the nominal state, the DSP will have a set of coefficients that it sends to the phase shifter. The coefficients are the phase quantities of the phase shifter offset signal for the corresponding antenna of the signal. For example, the DSP 101 sends a set of digital control information to the phase shifter, indicating that different phase shifters will be offset by different amounts, for example, offset by 30 degrees, offset by 45 degrees, offset by 90 degrees, offset by 180 degrees. Wait. Therefore, the phase of the signal sent to the antenna element will be offset by a certain number of degrees. The final result of shifting, for example, 16, 16, 32, 64 elements in the array by a different amount enables the antenna to be manipulated to provide the most sensitive receiving position for the receiving antenna. That is, the offset of the composite combination across the array of antennas provides the ability to change the position of the most sensitive point of the antenna on the hemisphere.

Note that in an embodiment, the appropriate connection between the transmitter and the receiver may not be a direct path from the transmitter to the receiver. For example, the most appropriate path can bounce back from the ceiling.

Return channel

In one embodiment, a wireless communication system includes a return channel or link for transmitting information between wireless communication devices (e.g., transmitters and receivers, a pair of transceivers, etc.). This information relates to beamforming antennas and this information enables one or both of the wireless communication devices to adapt the array of antenna elements to better direct the antenna elements of the transmitter to the antenna elements of the receiving device. The information also includes information that facilitates the use of content that is wirelessly transmitted between the transmitter and receiver antenna elements.

In FIG. 2, the return channel 220 is coupled between the DSP 216 and the DSP 201 to enable the DSP 216 to send tracking and control information to the DSP 201. In an embodiment, the return channel 220 acts as a high speed downlink and acknowledge channel.

In an embodiment, the return channel is also used to transmit information corresponding to the application, and the wireless communication is performed for the application (eg, wireless video). This information includes content protection information. For example, in one embodiment, the return channel is used to transmit encrypted information (eg, an encryption key and an encryption key confirmation) when the transceiver transmits the HDMI material. In this case, the return channel is used for content protection communication.

More specifically, in HDMI, encryption is used to verify that the data store is a licensed device (eg, a licensed display). When an HDMI stream is transmitted, a continuous stream of new encryption keys is transmitted to verify that the licensed device has not been altered. The blocks of the HD TV data frame are encrypted by different keys, and then the keys must be returned on the return channel 220 for verification to verify the player. The return channel 220 transmits the encryption key to the receiver in the forward direction and transmits an acknowledgement of the key reception from the receiver in the return direction. Therefore, the encrypted information is sent in both directions.

The use of a return channel for content protection communication is beneficial because it avoids having to complete a very long retraining process when the communication is sent with the content. For example, if the key from the transmitter is sent with the content flowing through the primary link and the primary link is disconnected, for a typical HDMI/HDCP system, it will impose a very long 2 seconds to 3 Retraining in seconds. In an embodiment, the separate bidirectional link has higher reliability than the main direction link that gives its omnidirectional orientation. By using this return channel for the HDCP key and the communication of the return confirmation from the receiving device, time-consuming retraining can be avoided even with the most impulsive obstacles.

During the action, when the beamforming antenna is transmitting content, the return channel is used to allow the receiver to inform the transmitter about the status of the channel. For example, when the channel between the beamformed antennas is of sufficient quality, the receiver sends a message on the return channel to indicate that the channel is acceptable. The receiver can also use the return channel to send transmitter measurable information indicating the quality of the channel being used. If some form of interference (eg, obstruction) occurs that degrades the quality of the channel below an acceptable level or prevents complete transmission between the beamforming antennas, the receiver may indicate that the channel is no longer acceptable and / Or you can request a change in the channel on the return channel. The receiver may request to change to the next channel in a predetermined group of channels, or may assign a particular channel to the transmitter for use.

In an embodiment, the return channel is bidirectional. In this case, in one embodiment, the transmitter uses the return channel to send information to the receiver. This information may include information that the command receiver positions its antenna elements at different fixed positions (the transmitter will scan for such positions during initialization). The transmitter may specify this by explicitly indicating the location, or by indicating that the receiver should continue to travel to a predetermined sequence or list (both transmitter and receiver travel through this sequence or The list indicates the next position.

In an embodiment, the return channel is used by either or both of the transmitter and the receiver to inform the other antenna characteristic information. For example, the antenna characteristic information can specify that the antenna can accept a radius resolution as low as 6 degrees and the antenna has a certain number of components (eg, 32 components, 64 components, etc.).

In an embodiment, wireless communication is performed on the return channel by using an interface unit. Any form of wireless communication can be used. In an embodiment, OFDM is used to transmit information on a return channel. In another embodiment, continuous phase modulation (CPM) with a low peak to average power ratio is used to communicate information on the return channel.

Physical layer (PHY) overview

The Wireless HD specification supports two basic types of PHYs: High Rate PHY (HRP) and Low Rate PHY (LRP).

According to an embodiment, the HRP supports data rates of multiple Gbps. HRP can operate in a directional mode (typically a beamforming mode). HRP can be used to transmit audio, video, data and control messages. The LRP can only be sent from the HTx/HTR device to the HRx/HTR device. In an embodiment, the HRP occupies a bandwidth of approximately 1.7 GHz.

According to an embodiment, the LRP supports multiple data rates of Mbps. The LRP can operate in a directional, omnidirectional or beamforming mode. In an embodiment, the LRP can be used to transmit control messages, beacons, and acknowledgments. In an alternate embodiment, the LRP can be further used to transmit audio or compress video. In yet another embodiment, the LRP can be further used to transmit low speed data. LRP can be sent between any device. The LRP occupies one of the three 91 MHz subchannels of the HRP channel discussed below.

Frequency plan

HRP and LRP can share the same frequency band. Figure 4 illustrates one embodiment of a frequency plan for HRP and LRP. The low rate channel 404 shares the same frequency band as the corresponding high rate channel 402. The three low rate channels 1A, 1B, 1C can be configured in each high rate channel bandwidth (channel 1) to avoid interference. According to another embodiment, the low rate and high rate channels can operate in a time division duplex mode. Figure 4 illustrates four examples of channels between 57 GHz and 66 GHz: channel 1 operates between 57.2 GHz and 59.2 GHz, channel 2 operates between 59.4 GHz and 61.4 GHz, and channel 3 operates at 61.6 GHz and 63.6 GHz. Operation between, channel 4 operates between 63.8 GHz and 65.8 GHz.

A single low cost crystal oscillator is capable of generating these frequencies. The baseband clock frequency can be close to 2.5 GHz (for example, 2.508 GHz). According to an embodiment, the frequency plan can support the design of an easily implemented RF synthesizer. The resulting center frequencies can be: 58.608 GHz, 60.720 GHz, 62.832 GHz, and 64.944 GHz. Possible crystal frequencies can include 44 MHz, 66 MHz, and 132 MHz.

High Rate PHY (HRP)

HRP supports data rates of 3.76 Gbps, 1.88 Gbps, and 0.94 Gbps. The data rate can be individually matched to the video resolution standards of 1080p, 1080i, and 480p for various sampling rates. Therefore, this range can be increased at lower data rates. A higher PHY rate can still allow multiple lower rate streams via the MAC.

HRP can utilize several types of coding and modulation: OFDM, 16QAM and QPSK modulation, internal convolutional codes (1/3, 2/3, 4/7, 4/5 rates) and Reed-Solomon (Reed) at a rate of 0.96 -Solomon) Outer code. In addition to the internal convolutional code, the use of the Reed-Solomon outer code reduces the SNR requirement by approximately 2 dB. An external interleaver can be used to achieve full gain of the outer code.

HRP can utilize four channels for the channel bandwidth of 1.7 GHz in the global 60 GHz band. According to an embodiment, there may be three channels per zone.

HRP can be extended to include parallelization of FEC streams for cost-effective implementation and support for the unequal error protection (UEP) concept.

Figure 5A illustrates an embodiment of a Tx PHY block diagram. The scrambler 502 receives the LMAC data and feeds it into the MSB/LSB separation block 504. For the MSB, an RS encoder 506 and an external interleaver 510 can be used. For the LSB, an RS encoder 508 and an external interleaver 512 can be used. The breakdown circuit 514 can be coupled to external interleavers 510 and 512. The following circuits are formed after the breakdown circuit 514: data multiplexer 516, bit interleaver 518, QAM mapper 520, carrier interleaver 522, pilot/DC/null insertion 524, and IFFT 526.

The HRP outer code interleaver 510, 512 can include a block interleaver and a convolutional interleaver. The function of the external interleaver is to ensure that the tuples of the outer code are mapped to consecutive bits of the inner codeword and that successive contigs of the outer code are mapped to different inner codewords. Block interleaver requires almost no memory in the transmitter and can improve efficiency without zero insertion. The tail element can be easily added by an external interleaver. The cyclotron interleaver requires several shift registers in the transmitter and may degrade efficiency with zero insertion. When a cyclotron interleaver is used, four OFDM symbols may be required to transmit the initial/final zero in the shift register. Efficiency can be degraded from about 0.5% to about 2%. The block outer interleaver 510, 512 minimizes the memory requirements between the Reed-Solomon outer code and the internal whirling code. In an embodiment, the block interleaver depth is 4 and there are M = 4 internal cyclotron encoders for each external interleaver. The external block interleaver will operate at four depths for HRP data. In an embodiment, the block interleaver can be implemented by a table of octets such that the number of rows is the same as the depth and the number of columns is the same as the length of the Reed-Solomon code: b(i, k), i=0,1,...,depth-1;k=0,1,...,N-1 b(i,K),b(i,K+1), ...,b(i,N The octet of -1) is the Reed-Solomon code co-bit of the octet of b(i,0), b(i,1),..., b(i,K-1) , Here RS(N, K) is the Reed-Solomon code. In an embodiment, the parameters of the external interleaver are depth = 4, K = 216, and N = 224. In another embodiment, the block interleaver operates on a group of bits (referred to as a byte). In another embodiment, each tuple has 8 bits or an octet. In another embodiment, each tuple has more than one bit.

Figure 5B illustrates an example of a block interleaver code. To reduce memory requirements, the mapping to the row and column of Figure 5B should use the following formula: i=fioor{[l mod(depth * M)]/M} k=M floor[l/(depth * M)+l mod M l = 0, 1, ..., depth * K-1 where l is the number of octets at the input of the external interleaver.

The external interleaver can output octets from the beginning i = 0, k = 0 to the last i = depth -1, k = N-1 . In the case where M is parallel with the cyclotron internal encoder of each RS codeword, the external interleaver assigns the octet of b(0,0),..., b(depth-1,0) to the first roundabout. Encoder, led by LSB. All octets of b(i,k * M + m) ( i =0,..., depth-1,k =0,1,..., N/M-1 ) will be output to the mth One rotary encoder. The tail element of the cyclotron encoder is inserted by an external interleaver. The i= depth-1 behavior of Figure 5B is a parity bit located at b(depth-1, K-M-9), b(depth-1, K-M-8),..., b(depth-1, The shortened RS (N-M, K-M, t=4) code at K-M-1) . The b- bits of b(depth-1, N-M), ..., b(depth-1, N-1) are complemented by zeros.

Figure 6 illustrates various parameters of the HRP in three different tables (602, 604, 606). Tables 602 and 604 illustrate different parameters of the HRP in accordance with the present invention. Table 606 illustrates the support rates in different modes of HRP.

One embodiment of an HRP internal code circuit is illustrated in Figures 7 and 8. Figure 7 illustrates a circuit diagram 700 of an HRP internal code. The inner code circuit can be described using a polynomial of (133, 171, 165). Figure 8 illustrates a table of the code rate, breakdown field type, and transmission sequence of the HRP internal code circuit. The "0" in the breakdown pattern means that the breakdown or deletion and the "1" in the breakdown type means no breakdown or deletion.

To support a data rate of 3.9 Gps, it may be necessary to parallelize the cyclotron encoder. In an embodiment, a base 4 accumulation-comparison-selection technique can be used at the receiver. The base 4 ACS processes 2 bits in each loop. The required clock frequency is equal to 3.9 Gps divided by the number of decoders and divided by two. For example, for 8 decoders, a clock of 244 MHz may be required.

The HRP data multiplexer 516 can combine data from eight cyclotron encoders. The mode can be determined by EEP or UEP. In the EEP mode, a loop mechanism is implemented to evenly allocate bits. In the UEP modulation mode, the MSB corresponds to the I branch of the QAM mapper, and the LSB corresponds to the Q branch of the QAM mapper. In the UEP coding mode, the strong MSB convolutional code causes the MSB bit at the input of the data multiplexer 516 to be more than the LSB bit. The block of 4 input bits (32 in total) of each of the 8 whirling encoders can represent one full cycle of the breakdown field type. The UEP coding mode can cause 28 MSB bits and 20 LSB bits at the output of the cyclotron encoder, which are mapped to 48 transmission bits scattered over I and Q.

The HRP bit interleaver 518 can spread the bits from the HRP data multiplexer 516 to the I/Q-branch of the QAM or QPSK cluster. The MSB and LSB of the QAM cluster do not provide the same encoded BER. The bit interleaver ensures that the BERs of the individual element streams from the same inner code encoder are the same. Each elementary stream is mapped to an equal number of MSBs and LSBs of the QAM cluster. The following is a suggested solution: P16:0,1,2,3,4,5,6,7,9,8,11,10,13,12,15,14, making i=M*floor(k/ M)+mod(2*floor(k/2)+mod(k+floor(k/M), 2), M), k=0,1,...,2M-1, where in the block of 2M=16 , i is the index of the output bit, and k is the index of the input bit.

P32: 0, 1, 2, 3, 4, 5, 6, 7, 11, 8, 9, 10, 15, 12, 13, 14, 18, 19, 16, 17, 22, 23, 20, 21, 25,26,27,24,29,30,31,28, such that i=M*floor(k/M)+mod(4*floor(k/4)+mod(k+floor(k/M),4),M ), k = 0, 1, ... 4M-1, where in the block of 4M = 32, i is the index of the output bit, and k is the index of the input bit.

The above solutions are illustrated graphically in Figures 9 and 10.

In an HRP channel with frequency selective fading, different subchannels of an OFDM symbol may have different channel responses and adjacent OFDM subchannels typically experience the same fading effect. To improve performance, the carrier interleaver maps adjacent data to distant OFDM subchannels. In an embodiment, the HRP spiral scan carrier interleaver may include the following solution: i=mod(floor(k/24)+3*mod(k,24), 14)*24+mod(k,24), k = 0, 0, ... , N _dsc(HR) -1 where i is the index of the output carrier frequency and k is the index of the input carrier frequency.

The above solution is illustrated graphically in Figure 11.

In an alternate embodiment, the carrier shift interleaver can be designed based on the bit reverse principle. In the actual implementation of IFFT, there is a one-bit inverse circuit before or after the IFFT calculation. In the bit reverse circuit, the index of the input data first appears as a binary digit, and the resulting binary representation indicates that the legal system bit is inverted, and the reverse binary digit of the bit becomes the index of the output data. When using a bit reverse carrier interleaver, the carrier interleaver and the IFFT calculation can be combined. The IFFT calculation circuit is embedded in a bit-inverse carrier-shift interleaver. The DC, null, and pilot carrier tones are placed in reverse orientation before the bit inserted into the carrier interleaver. In this way it is ensured that after the alignment, the DC, null and pilot carrier tones will appear in the pre-specified position. Using the traveling pilot as will be described later, the bit position reverse positioning for the pilot is sequentially changed in OFDM symbols. When used in a base 2 IFFT implementation (which uses multiple 2x2 basic architecture blocks), the bit reverse carrier interleaver can perform optimal operations. For example, for a base 8 IFFT implementation using multiple 8x8 architecture blocks, the index of the input data should first be represented as an octet, and the octet inverse number as the output data. In this particular example, the octet reverse carrier interleaver provides the simplest implementation for combining the carrier interleaver and IFFT.

HRP pilot 524 may include a rotating pilot mechanism to vary the pilot carrier per symbol, thereby allowing for better channel tracking of packets as necessary. This approach also avoids having to change the polarity of all pilots from one OFDM symbol to the next OFDM symbol according to the coverage sequence. The pilot value can be the same as the carrier frequency of the corresponding HRP preamble #5 (described later). The pilot carrier tone position can be defined by a symbol index starting with a preamble #5. For symbol=0: Nsymbol-1, k=(-177+mod(3*symbol,22):22:177), here k! ={-1,0,1}. According to an embodiment, the pilot rotational speed can be fixed to rotate each symbol by 3 bins. Conversely, if the pilot position is fixed, its value will need to change over time to avoid any spectral ripple effects.

The HRP preamble can include 8 symbols. Symbols #1-#4 can be based on a PN sequence. Six consecutive m-sequences can be used in 4 symbols. Symbols #1-#4 can be used for packet detection, frame synchronization based AGC training. Symbols #5-#8 may be based on OFDM symbols and may be used for frequency offset estimation and channel estimation. According to an embodiment, scaling factor correction can be used to maintain the power of the eight preamble symbols the same as the remaining OFDM symbols for data transmission. In one of these embodiments, the power of symbols #1-#4 can be 3 dB greater than the symbols #5-#8.

Figure 12 illustrates one embodiment of an external FEC for an HRP header. The HRP header external FEC is somewhat similar to the external FEC for HRP data because it provides the same or better error protection as the data. It uses the same Reed-Solomon generator. It uses the same method to provide a tail part element to terminate the convolutional codeword. It uses the same Reed-Solomon decoder in the receiver. Four OFDM symbols can be used for the HRP header with 112 coded bytes at 1/4 rate. The HRP header FEC can use the same RS code generator polynomial as the data. The HRP header FEC may include 92 or more 92 uncoded bytes. A coded branch may include four cyclotron encoders having four tail position tuples 1202. The depth of the HRP header FEC can be 2 bytes 1204 and 1206. The byte 1204 can include 44 data bytes, 8 parity bits, and tail location 1202. The byte 1206 can include 48 data bytes and 8 parity bits. The depth of the two block interleavers provides sufficient performance.

Figure 13 illustrates one embodiment of an HRP data scrambler. A 15th degree polynomial (x ^I5 + x ¹⁴ +1) can be used to improve the randomness of the transmitted data for HRP. Figure 13 illustrates an initialization sequence with four bits at locations D12 through D15 (where D15 is first).

Low rate PHY (LRP)

LRP can be used for MAC frame transmission (eg, ACK, beacon, discovery, etc.), for low rate (less than 40 Mbps) streams from A/V sources, for antenna manipulation and for tracking the transmission of data used. The LRP can be designed with a BPSK modulation based on OFDM of 128-point FFT and a gyro code of 1/3, 1/2 and 2/3 rates. The Reed-Solomon code is not required because of the short message and high BER tolerance. LRP can operate in three modes: LRP omnidirectional (long) mode, LRP beamforming mode, and LRP oriented (short) mode. These different modes are discussed further below.

Figure 14 illustrates one embodiment of LRP Tx processing. The LRP circuit can include a scrambler 1402, an FEC 1404, an interleaver 1406, a map 1408, an IFFT 1416, a loop first code 1414, a symbol shaping 1412, and an up-conversion 1410.

Figure 15 illustrates a table of LRP data rates. As shown, different LRP modes produce different LRP data rates.

The LRP pilot and data carrier frequency can be defined as follows: 128-point FFT, 30 data carrier frequency modulation and 4 pilot carrier frequency adjustments, and three unused carrier frequency adjustments at DC (carrier frequency adjustment number -1 , 0 and 1), the pilot carrier frequency adjustment position can be modified, and the fixed pilot carrier frequency adjustment position at the carrier frequency adjustment numbers -14, -6, 6 and 14 is at all other positions from -18 to +18. Data carrier frequency adjustment.

The LRP scrambler 1402 can use a 6th degree polynomial. The scrambler initialization field can be 4 bits. To initialize this polynomial, the 4-bit initialization field can be concatenated with the 01 bit.

In LRP omni mode, the resulting signal is omnidirectional, has a range that is at least as large as any of the forward channel modes, and allows for a much stronger path than the forward channel. The line rate in LRP omni mode can be from about 5 Mbps to about 10 Mbps with a target BER of less than 10 ^-6 . In LRP omni mode, each signal is transmitted multiple times using different antenna patterns. In one embodiment, each signal is repeated 8 times using 8 different antenna patterns. In an embodiment, different antenna patterns are orthogonal to one another. Therefore, each copy uses a different TX phased array setting (exchanged during the cycle first code). The receiver can use MRC or similar technology to combine the copies. Spatial diversification helps maintain omnidirectional coverage.

16 illustrates an LRP omnidirectional data packet format including: a preamble 1602, a header 1604, and a valid bearer 1606. Header 1604 can include mode 1608, reserved 1610, length 1612, scrambler Init 1614, and CRC-8. Header 1604 is a long format having 30 bits encoded as 2 OFDM symbols having a 1/2 rate tail portion elementary convolutional code. When the tail element is used, the initial and final states of the whirling code are the same. In one embodiment, the last six information bits of the header can be used to initialize the state of the cyclotron encoder. The LRP full forward term 1602 can include two types: a long full forward term and a short full forward term.

The long full forward term can be about 56.67 microseconds. This type of preamble can be used for beacons and other LRP data packets that require blind timing synchronization.

Figure 17 illustrates an embodiment of a long full forward term 1700 having six segments (with 17766 samples): automatic gain control (AGC) and signal detection segment 1702, coarse frequency offset estimation (FOE) and Timing recovery section 1704, fine FOE and timing recovery section 1706, RX beamforming section 1708, AGC section 1710, and channel estimation section 1710. The first three preamble segments 1702, 1704, 1706 consist of a sequence of offset-QPSK modulated chips (chip rate 156.75 MHz (one-half of the sampling rate)), the chips Filtered to meet the 91 MHz LRP transmission mask.

The domain of the AGC and signal detection section 1702 contains 78 symbols, each of which is defined by Barker-13 for the I and Q components ([-1 -1 -1 -1 -1 1 1 -1 -1 1 -1 1 -1]) 1 or -1 of the chip sequence. Symbol sequence {Sk} (Sk= 1) is constructed by differential encoding of 26 repetitions of the three-symbol sequence {b _k } = [-1, 1, -1], specifically, S _k = S _k-1 × b _k , where S _{0 =} 1.

The domain of the coarse FOE (Frequency Offset Estimation) section 1704 contains 81 symbols, where each symbol is defined as 1 or -1 dispersed by the Buck-13 chip sequence for the I and Q components. Symbol sequence {S _k } ( S _k = 1) is constructed by the differential coding of 9 repetitions of the nine-symbol sequence {b _k } =[-1 -1 -1 -1 1 1 -1 1 -1], specifically, S _9i+k = S _9i+k-1 × b _k , where S ₀ is the last symbol of the previous field.

The fields of the fine FOE and timing recovery section 1706 consist of a 1440 PN chip sequence for the I and Q components generated by using the polynomial x ¹² + x ¹¹ + x ⁸ + x ⁶ +1 under the initial conditions of 0xB95. .

The domain of the RX beamforming section 1708 consists of a 2560 PN chip sequence for the I and Q components, which is generated under the initial conditions of 101001 using a polynomial x ⁶ + x ⁵ + 1 .

The AGC section 1710 is 20 repetitions of an OFDM training symbol of 32 samples long, which is equal to the IFFT of the following BPSK 32-point sequence: subcarriers -4 to 4 are equal to {1 1 1 -1 0 -1 -1 1 -1} And all others are equal to zero.

The channel estimation section 1712 is composed of 32 128 sample OFDM training symbols, where each is equal to the following 128 points BPSK sequence (previously 28 sample cycle first code) IFFT: subcarrier 2-18 is equal to {1 -1 1 -1 -1 1 -1 1 1 1 1 1 1 -1 -1 1 1 }, subcarrier -18 to -2 is equal to {-1 1 1 1 1 1 -1 -1 1 -1 1 -1 -1 - 1 1 -1 1}, and all others are equal to zero. The TX antenna phased array pattern can be changed at regular time intervals for each of the five of the LRP full forward terms 1602. Therefore, for 8 TX antennas, the TX phased array is changed for every 78, 234, 160, 640, 64, and 156 samples for each of the above five domains.

The short full forward term can be about 42.72 microseconds. This type of preamble can be used in the contention period (for slotted CSMA) and other LRP data packets that require only limited (+/- 135 nanoseconds) timing synchronization.

Figure 18 illustrates an embodiment of a short full forward term 1800 having six segments (13392 samples): AGC segment 1802, AGC segment 1804, signal detection and time synchronization segment 1806, RX beamforming Section 1808, AGC section 1810, and channel estimation section 1812. The first four preamble fields 1802, 1804, 1806, 1808 consist of a sequence of BPSK chips (chip rate 156.75 MHz (each chip equals 2 samples)), which are filtered to match 91. The LRP transmission mask of MHz. The chip sequence is generated by repeating the 63-tap M-sequence to be specified. The first two fields 1802 and 1804 are AGC fields with lengths of 336 and 264 chips, respectively. The third field 1806 is 720 chips in length and is used to detect LRP packets and synchronize their timing in a window of -/+ 135 nanoseconds. The fourth field 1808 is 2560 chips in length and is used for RX beamforming. The second AGC field 1804 is 20 repetitions of an OFDM training symbol of 32 samples long, which is equal to the following IFFT of the BPSK 32-point sequence: subcarriers -4 to 4 are equal to {1 1 1 -1 0 -1 -1 1 -1 }, and all others are equal to zero. Channel estimation field 1812 is composed of 32 128 sample OFDM training symbols, each of which is equal to the following 128 points BPSK sequence (previously 28 sample cycle first code) IFFT: subcarrier 2-18 equals {1 -1 1 -1 -1 1 -1 1 1 1 1 1 1 -1 -1 1 1}, subcarrier -18 to -2 is equal to {-1 1 1 1 1 1 -1 -1 1 -1 1 -1 -1 -1 1 -1 1}, and all others are equal to zero. The TX antenna phased array pattern can be changed at regular time intervals for each of the five of the short full forward terms. Therefore, for 8 TX antennas, the TX phased array is changed for every 32, 48, 160, 640, 64, and 156 samples for each of the above 6 domains.

In the LRP beamforming mode, the same technique as HRP beamforming can be used. This mode is the highest data rate but is oriented and requires beam update. 19 illustrates an example of a data packetization format 1900 for LRP beamforming that includes a short preamble 1902, a header 1904, and a valid bearer 1906. Header 1904 can be 30 bits that are encoded as 3 symbols, with the 1/3 rate tail portion element convolutional code.

The LRP beamforming preamble 1902 allows for blind timing synchronization and has a similar structure to the HRPPDU preamble. Figure 20 illustrates one embodiment of an LRP beamforming preamble 2000. The LRP beamforming preamble 2000 packet length is 7.96 milliseconds (2496 samples) and contains two fields: frame synchronization and AGC domain 2004 and channel estimation domain 2006.

Frame synchronization and AGC field 2004 consists of a sequence of BPSK chips (chip rate of 156.75 MHz (each chip equals 2 samples)) that are filtered to conform to the 91 MHz LRP transmission mask. The chip sequence is equal to 14 repetitions of the 63-tap M-sequence to be specified for 936 chips, where the sequence is modulated/multiplied by [1 1-1-1 1 1 1 111-1-1111], respectively.

As illustrated in the sequence 2002 of Figure 20 (where the plus and minus signs mean that the corresponding samples are multiplied by 1 or -1, respectively), the channel estimation field 2006 repeats the time domain samples of the 128 OFDM training symbols by repetition (this Constructed in Table 35 in the frequency domain.

In LRP directional mode, the resulting signal has a similar range as in the forward channel, requiring only "reverse" hardware (ie, less Rx/Tx). In LRP orientation mode, each signal is repeated multiple times using the best antenna pattern. In an embodiment, the optimal antenna pattern is selected from the eight possible antenna patterns used in the omni mode. In one embodiment, each signal repeats 5 (= 4 + 1) times or 9 (= 8 + 1) times. The optimized TX phased array pattern can be tracked, for example, every 10 packets. The best TX diversified field type self-return channel receiver feeds back to the return channel transmitter.

The line rate in LRP directional mode can range from about 5 Mbps to about 10 Mbps. The directional LRP packet can be used as an ACK to confirm HRP or beamforming LRP, data packets with or without additional payload. Figure 21A illustrates a short 15-bit ACK header without a valid bearer. Figure 21B illustrates a short ACK header of 16 bits with payload. The directional LRP short ACK header is encoded by a 1/2 rate tail element gyro code and transmitted by 1 OFDM symbol. For a directional LRP packet with a payload (second format), the mode bit selects one of the following two non-beamforming PHY data rates: 5 Mbps: mode bit = 0 10 Mbps: mode bit = 1

In LRP orientation mode, information is encoded by a 2/3 rate convolutional code. If the tail part element can be used to reduce the number of OFDM symbols, the tail part element is used. Otherwise use at least 6 consecutive zeros to terminate the interleaving of the whirling code.

For such packages, the postamble flag specifies that a post-term is (flag = 1) no (flag = 0) attached to the packet.

Figure 22 illustrates a certain forward LRP packet preamble 2200. The LRPPDU preamble of the directed packet is 2.04 milliseconds (640 samples) in length and contains 5 OFDM training symbols as shown here. The first symbol 2202 is for AGC and the next 4 symbols are used for channel estimation and frequency offset estimation 2204. Pre-sets allow for limited (-/+150 nanoseconds) timing inaccuracies.

Figure 23 illustrates antenna direction tracking for directional LRP packets. As already mentioned, directional LRP packets are used for the validation of HRP or beamforming (BF) LRP packets. The packets use the best TX antenna direction from a group of up to 8 antenna directions, wherein optimizing the TX antenna direction needs to be tracked over time using a special frame structure as described in FIG. For every M regular HRP/short-ACK or beamforming-LRP/short-ACK, a frame can be formed as in 2300 of FIG. There is a pair of HRP/short-ACK or beamforming-LRP/short-ACK frames with the following special structure, where HR/LR beam tracking and LR antenna direction tracking (ADT) occur as illustrated in 2302 of FIG.

As shown, the antenna direction tracking occurs in two phases: (1) selecting the optimized TX antenna direction by using a dedicated post item and (2) using the dedicated preamble to select the selected TX antenna direction. RX beamforming/tuning. Between the above two phases, the selected antenna direction index is fed back from the short ACK RX to the short ACK TX via an HRP or beamforming LRP packet.

Figure 24 illustrates a Tx antenna direction tracking post item 2400. The TX antenna direction tracking post-term for directional LRPPDUs is attached to an directional LRP packet with payload. The TX ADT post-term is 9.24 microseconds in length (2896 samples) and contains three segments 2402, 2404, 2406. The two post-term fields 2404, 2406 follow a protection interval of 2404 of 2.04 milliseconds and consist of a sequence of BPSK chips (chip rate of 156.75 MHz (each chip equals 2 samples)) Filter to match the 91 MHz LRP transmission mask. The chip sequence is generated by repeating a 63 tap M-sequence to be specified. The second field 2404 is for AGC and has a length of 264 chips. The third field 2406 is 864 chips in length and is used to select the best TX diversity combination among the 8 antennas. The TX antenna phased array field pattern changes according to the regular time interval of the post item. For 8 TX antennas, the TX phased array is changed for every 48 and 192 samples for each of the above 2 fields.

Figure 25 illustrates a Tx antenna direction tracking preamble 2500. The RX ADT preamble is added to the directional LRP packet without payload and used for RX beamforming for the selected TX antenna direction. This additional preamble contains two sections 2502, 2504 (1152 samples). The two fields consist of a sequence of BPSK chips (chip rate of 156.75 MHz (each chip equals 2 samples)) that are filtered to conform to the 91 MHz LRP transmission mask. The chip sequence is generated by repeating a 63 tap M-sequence to be specified. The first field 2502 is for AGC and has a length of 128 chips. The second field 2504 is 448 chips in length and is used for RX beamforming.

It will be apparent to those skilled in the art that <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; Therefore, the reference to the details of the various embodiments is not intended to limit the scope of the claims.

100. . . Media receiver

101. . . content

102. . . Media receiver interface

103. . . processor

104. . . Optional baseband processing component

105. . . Phased array antenna

106. . . Line communication channel interface

107. . . Wireless communication channel/link

109. . . Wireless communication channel interface

110. . . Phased array antenna

111. . . Optional baseband processing component

112. . . processor

113. . . Media player interface

114. . . media Player

115. . . monitor

122. . . Control channel

140. . . Launcher

141. . . Receiving device

201. . . Digital signal processor

202. . . Digital/analog converter

203. . . Mixer

204. . . Local oscillator

205 _0-N . . . Phase shifter

206 _0-N . . . Power amplifier

207 _0-N . . . Antenna component

208. . . Control channel

210 _0-N . . . antenna

211 _0-N . . . Phase shifter

212. . . IF amplifier

213. . . Mixer

214. . . Local oscillator

215. . . Analog/digital converter

216. . . Digital signal processor

217. . . Control channel

220. . . Return channel

402. . . High rate channel

404. . . Low rate channel

502. . . Scrambler

504. . . Separation block

506. . . RS encoder

508. . . RS encoder

510. . . External interleaver

512. . . External interleaver

514. . . Breakdown circuit

516. . . Data multiplexer

518. . . Bit interleaver

520. . . QAM mapper

522. . . Carrier frequency interleaver

524. . . Pilot/DC/null insertion

526. . . IFFT

602. . . form

604. . . form

606. . . form

700. . . Circuit diagram

1202. . . Tail part tuple

1204. . . Byte

1206. . . Byte

1402. . . Scrambler

1404. . . Forward error correction

1406. . . Interleaver

1408. . . Mapping

1410. . . Upconversion

1412. . . Symbol shaping

1414. . . Cycle first code

1416. . . IFFT

1700. . . Long full forward

1702. . . Automatic Gain Control (AGC) and Signal Detection Section

1704. . . Coarse frequency offset estimation (FOE) and timing recovery section

1706. . . Fine FOE and timing recovery section

1708. . . RX beamforming section

1710. . . AGC section

1712. . . Channel estimation section

1800. . . Short full forward

1802. . . AGC section

1804. . . AGC section

1806. . . Signal detection and time synchronization section

1808. . . RX beamforming section

1810. . . AGC section

1812. . . Channel estimation section

1900. . . Data packet format

1902. . . Short predecessor

1904. . . Header

1906. . . Effective bearer

2000. . . LRP beamforming predecessor

2002. . . sequence

2004. . . Frame synchronization and AGC domain

2006. . . Channel estimation domain

2200. . . Directional LRP packet preamble

2202. . . First symbol

2204. . . Channel estimation and frequency offset estimation

2400. . . Tx antenna direction tracking back item

2402. . . Section/post field

2404. . . Section/post field

2406. . . Section/post field

2500. . . Tx antenna direction tracking front item

2502. . . Section/prefix field

2504. . . Section/prefix field

1 is a block diagram of one embodiment of a communication system.

2 is a more detailed block diagram of one embodiment of a communication system.

3 is a block diagram of one embodiment of a peripheral device.

4 is a block diagram of one embodiment of a different channel sharing frequency.

5A is a block diagram of one embodiment of a physical layer for the wireless HD communication system of FIG. 1.

Figure 5B is a table illustrating one example of a block interleaver code.

6 is a block diagram of one embodiment of a High Rate Packet (HRP) parameter for the wireless HD communication system of FIG. 1.

7 is a block diagram of an embodiment of an inner code circuit of the wireless HD communication system of FIG. 1.

Figure 8 is a table of the code rate of the inner code circuit of Figure 7.

9 is a block diagram of one embodiment of a bit interleaver of the wireless HD communication system of FIG. 1.

Figure 10 is a table of the specifications of the bit interleaver of Figure 9.

11 is a diagram of an embodiment of a carrier frequency interleaver of the wireless HD communication system of FIG. 1.

12 is a block diagram of one embodiment of an external FEC of a High Rate Packet (HRP) header of the wireless HD communication system of FIG.

13 is a block diagram of one embodiment of a high rate packet (HRP) data scrambler of the wireless HD communication system of FIG. 1.

14 is a block diagram of one embodiment of a physical layer of low rate packet (LRP) transmission of the wireless HD communication system of FIG.

15 is a table of low rate packet (LRP) data rates for the wireless HD communication system of FIG. 1.

16 is a block diagram of one embodiment of a format for an Omnidirectional Low Rate Packet (LRP) data packet.

17 is a block diagram of one embodiment of a long preamble format for an Omnidirectional Low Rate Packet (LRP) data packet.

18 is a block diagram of one embodiment of a short preamble format for an Omnidirectional Low Rate Packet (LRP) data packet.

19 is a block diagram of one embodiment of a format for beamformed low rate packet (LRP) data packets.

20 is a block diagram of one embodiment of a beamformed low rate packet (LRP) data packet preamble format.

21A is a block diagram of one embodiment of a format for a directional low rate packet (LRP) data packet without a valid bearer.

21B is a block diagram of one embodiment of a format for a directional low rate packet (LRP) data packet with payload.

22 is a block diagram of one embodiment of a format for a directional low rate packet (LRP) preamble.

23 is a block diagram of one embodiment of a format for directional low rate packet (LRP) for antenna direction tracking.

24 is a block diagram of one embodiment of a directional low rate packet (LRP) post-entry format for transmission antenna direction tracking.

25 is a block diagram of one embodiment of a directional low rate packet (LRP) preamble format for receiving antenna direction tracking.

201. . . Digital signal processor

202. . . Digital/analog converter

203. . . Mixer

204. . . Local oscillator

205 _0-N . . . Phase shifter

206 _0-N . . . Power amplifier

207 _0-N . . . Antenna component

208. . . Control channel

210 _0-N . . . antenna

211 _0-N . . . Phase shifter

212. . . IF amplifier

213. . . Mixer

214. . . Local oscillator

215. . . Analog/digital converter

216. . . Digital signal processor

217. . . Control channel

220. . . Return channel

Claims (74)

A communication device comprising: a processor; a radio frequency (RF) transmitter coupled to the processor and controlled by the processor to transmit data; a physical layer circuit coupled to the RF transmitter Encoding and decoding between a digital signal and a modulation analog signal, the physical layer circuit comprising a high rate physical layer circuit (HRP) and a low rate physical layer circuit (LRP); wherein the low rate physical layer circuit The low rate channel generated by (LRP) shares the same frequency band as the corresponding high rate channel generated by the high rate physical layer circuit (HRP); wherein the HRP includes one external code circuit coupled in series, an external interleaver circuit, and M internal encoders, wherein M is greater than 1, and the external interleaver circuit includes a block interleaver that maps consecutive bit groups of outer codewords to different inner codes, and the outer code The same byte in the codeword is mapped to consecutive bits of the inner code; and wherein the LRP is operative to generate an LRP data packet for acknowledgment of the HRP packet. The communication device of claim 1, wherein the high rate physical layer circuit (HRP) is to generate a data rate of about several billion bits per second, and the low rate physical layer circuit (LRP) will generate millions of bits per second. The data rate of the bit. A communication device as claimed in claim 1, wherein the three low rate channel systems generated by the low rate physical layer circuit (LRP) are configured by the high rate entity Layer circuit (HRP) is generated in a high rate channel. The communication device of claim 1, wherein the low rate channels and the high rate channels operate in a time division duplex (TDD) manner. The communication device of claim 1, wherein the radio frequency (RF) transmitter comprises a crystal to generate an intermediate frequency (IF) and a radio frequency (RF). A communication device as claimed in claim 5, wherein the crystal generating center is located at four channels between about 57 GHz and about 66 GHz. The communication device of claim 6, wherein the four channels comprise 58.608 GHz, 60.720 GHz, 62.832 GHz, and 64.944 GHz. The communication device of claim 1, wherein the high rate physical layer circuit (HRP) is to generate one or more wireless signals occupying a bandwidth of about 1.7 GHz. The communication device of claim 1, wherein the high rate physical layer circuit (HRP) is to generate a directional beamforming signal for the RF transmitter. The communication device of claim 1, wherein the high rate physical layer circuit (HRP) is associated with transmission of audio, video, data, and control messages. The communication device of claim 1, wherein the low rate physical layer circuit (LRP) is to generate one or more wireless signals occupying a sub-channel having a bandwidth of about 91 MHz. A communication device as claimed in claim 1, wherein the low rate physical layer circuit (LRP) is to generate a directional signal, an omnidirectional signal or a beamforming signal for the RF transmitter. The communication device of claim 1, wherein the low rate physical layer circuit (LRP) is associated with control messages, beacons, acknowledgments, and low speed data. The communication device of claim 1, wherein the HRP comprises coupling in series The outer code circuit, the outer interleaver circuit, an inner code circuit, a one-bit interleaver circuit, a carrier frequency interleaver circuit and a data scrambler circuit. The communication device of claim 1, wherein the external interleaver circuit coupled to the outer code circuit is configured to further divide the input bit groups into a group of consecutive M bytes, the M bits The tuple is input to consecutive bytes of the outer code, and the M bytes are mapped to M different inner codes. A communication device as claimed in claim 1, further comprising: a one-bit interleaver circuit coupled in series to the external interleaver circuit and mapping bits from the same inner code to an equal number of MSBs and LSBs of the signal cluster . The communication device of claim 1, wherein the LRP comprises a pilot carrier frequency modulation circuit, a carrier frequency interleaver circuit, an FEC circuit and a data scrambler circuit coupled in series. The communication device of claim 1, wherein the LRP is configured to generate an LRP long omnidirectional data packet, an LRP beamform data packet, and an LRP short directional data packet. The communication device of claim 18, wherein the LRP long omnidirectional data packet includes an LRP preamble, an LRP header, and an LRP payload. The communication device of claim 19, wherein the LRP header is encoded by a tail portion meta-rotation code. The communication device of claim 19, wherein the LRP preamble comprises a long omnidirectional LRP preamble or a short omnidirectional LRP preamble. The communication device of claim 21, wherein the length of the long omnidirectional LRP preamble It is about 57 microseconds. The communication device of claim 21, wherein the long omnidirectional LRP preamble is configured for beaconing and LRP data packets with blind timing synchronization. The communication device of claim 21, wherein the long omnidirectional LRP preamble includes a first AGC and signal detection section, a coarse FOE and timing recovery section, a fine FOE and timing recovery section, and a receiver A beamforming section, a second AGC section, and a channel estimation section. The communication device of claim 21, wherein the short omnidirectional LRP preamble is about 43 microseconds in length. The communication device of claim 21, wherein the short omnidirectional LRP preamble is configured for a contention period and an LRP data packet with timing synchronization. The communication device of claim 21, wherein the short omnidirectional LRP preamble comprises a first AGC segment, a second AGC segment, a signal detection and time synchronization segment, a receiver beamforming segment, A third AGC segment and a channel estimation segment. The communication device of claim 18, wherein the LRP beamformed data packet comprises an LRP beamforming preamble, an LRP beamforming header, and an LRP beamforming payload. The communication device of claim 28, wherein the LRP beamforming preamble comprises a frame synchronization and AGC segment, and a channel estimation segment. The communication device of claim 18, wherein the LRP short-directional data packet comprises an LRP short-directional preamble and an LRP short-directional header. The communication device of claim 18, wherein the LRP short-directional data packet comprises an LRP short-directional preamble, an LRP short-directional header, and an LRP short-term To be effectively carried. The communication device of claim 30, wherein the LRP short directional preamble comprises an AGC segment and a channel estimation segment. The communication device of claim 18, wherein the LRP short-directional data packet is configured for confirmation of HRP packets and beamforming LRP packets. A communication device comprising: a processor; a radio frequency (RF) transmitter having a digitally controlled phased array antenna coupled to the processor and controlled by the processor to transmit data or content An interface of one to one wireless communication channel coupled to the processor to convey antenna information about the use of the phased array antenna and to convey information to facilitate receiving the material or playing the content at another location; And a physical layer circuit coupled to the RF transmitter and the interface for encoding and decoding between a digital signal and a modulation analog signal, the physical layer circuit comprising a high rate physical layer circuit (HRP) and a low rate physical layer circuit (LRP), wherein a low rate channel generated by the low rate physical layer circuit (LRP) shares the same frequency band as a high rate channel corresponding to one of the high rate physical layer circuits (HRP) generation; The HRP includes an external code circuit coupled in series, an external interleaver circuit, and M inner encoders, wherein M is greater than 1, and the external interleaver circuit includes a block interleaver, the region The outer code interleaver successive bytes of the codeword is mapped to a different inner code and the outer code codeword The same tuple is mapped to consecutive bits of the inner code. The communication device of claim 34, wherein the high rate physical layer circuit (HRP) is to generate a data rate of approximately several billion bits per second, and the low rate physical layer circuit (LRP) will generate approximately millions per second The data rate of the bit. The communication device of claim 34, wherein the three low rate channels generated by the low rate physical layer circuit (LRP) are configured in a high rate channel generated by the high rate physical layer circuit (HRP). The communication device of claim 34, wherein the high rate physical layer circuit (HRP) is to generate one or more wireless signals occupying a bandwidth of about 1.7 GHz. The communication device of claim 34, wherein the high rate physical layer circuit (HRP) is to generate a directional beamforming signal for the RF transmitter. The communication device of claim 34, wherein the high rate physical layer circuit (HRP) is associated with the transmission of audio, video, data, and control messages. The communication device of claim 34, wherein the low rate physical layer circuit (LRP) is to generate one or more wireless signals occupying a sub-channel having a bandwidth of about 91 MHz. The communication device of claim 34, wherein the low rate physical layer circuit (LRP) is to generate a directional signal for the RF transmitter, an omnidirectional signal, or a beamforming signal. The communication device of claim 34, wherein the low rate physical layer circuit (LRP) is associated with control messages, beacons, acknowledgments, and low speed data. The communication device of claim 34, wherein the HRP comprises the outer code circuit coupled in series, the external interleaver circuit, an inner code circuit, and a A bit interleaver circuit, a carrier frequency interleaver circuit and a data scrambler circuit. The communication device of claim 34, wherein the external interleaver circuit coupled to the outer code circuit is further configured to further divide the input bit groups into a group of consecutive M bytes, the M bits The tuple is input to consecutive bytes of the outer code, and the M bytes are mapped to M different inner codes. The communication device of claim 44, further comprising: a one-bit interleaver circuit in series with the outer code circuit and mapping bits from the same inner code to an equal number of MSBs and LSBs of the signal cluster. The communication device of claim 34, wherein the LRP comprises a pilot carrier frequency modulation circuit, a carrier frequency interleaver circuit, an FEC circuit and a data scrambler circuit coupled in series. The communication device of claim 34, wherein the LRP is configured to generate an LRP long omnidirectional data packet, an LRP beamform data packet, and an LRP short directional data packet. The communication device of claim 47, wherein the LRP long omnidirectional data packet includes an LRP preamble, an LRP header, and an LRP payload. The communication device of claim 48, wherein the LRP header is encoded by a tail portion meta-rotation code. The communication device of claim 48, wherein the LRP preamble comprises a long omnidirectional LRP preamble or a short omnidirectional LRP preamble. The communication device of claim 50, wherein the long omnidirectional LRP preamble is about 57 microseconds in length. The communication device of claim 50, wherein the long omnidirectional LRP preamble is configured for beaconing and LRP data packets with blind timing synchronization. The communication device of claim 50, wherein the long omnidirectional LRP preamble includes a first AGC and signal detection section, a coarse FOE and timing recovery section, a fine FOE and a timing recovery section, and a receiving A beamforming section, a second AGC section, and a channel estimation section. The communication device of claim 50, wherein the short omnidirectional LRP preamble is about 43 microseconds in length. The communication device of claim 50, wherein the short omnidirectional LRP preamble is configured for a contention period and an LRP data packet with timing synchronization. The communication device of claim 50, wherein the short omnidirectional LRP preamble comprises a first AGC segment, a second AGC segment, a signal detection and time synchronization segment, a receiver beamforming segment, A third AGC segment and a channel estimation segment. The communication device of claim 47, wherein the LRP beamformed data packet comprises an LRP beamforming preamble, an LRP beamforming header, and an LRP beamforming payload. The communication device of claim 57, wherein the LRP beamforming preamble comprises a frame synchronization and an AGC segment and a channel estimation segment. The communication device of claim 57, wherein the LRP short-directional data packet comprises an LRP short-directional preamble and an LRP short-directional header. The communication device of claim 57, wherein the LRP short directional data packet comprises an LRP short directional preamble, an LRP short directional header, and an LRP short directional payload. The communication device of claim 59, wherein the LRP short-directional preamble comprises an AGC segment and a channel estimation segment. The communication device of claim 57, wherein the LRP short-directional data packet is configured for confirmation of HRP packets and beamforming LRP packets. A method of wireless communication, comprising: generating a modulation analog signal to transmit antenna information and content protection information corresponding to content via a wireless communication channel, wherein generating the modulation analog signal further comprises: using a low rate physical layer circuit ( LRP) generates a low rate channel; uses a high rate physical layer circuit (HRP) to generate a high rate channel; wherein the low rate channel generated by the low rate physical layer circuit (LRP) and by the high rate physical layer circuit (HRP) Generating one of the corresponding high rate channels to share the same frequency band; and wherein the HRP includes one of an outer code circuit coupled in series, an external interleaver circuit, and M inner encoders, wherein M is greater than 1, and the external interleaver circuit includes A block interleaver that maps consecutive groups of outer codewords to different inner codes and maps the same byte in the outer codeword to consecutive bits of the inner code. The method of wireless communication of claim 63, further comprising: configuring the three low rate channels in a high rate channel. The method of wireless communication of claim 63, wherein generating the modulated analog signal further comprises: generating four channels centered between about 57 GHz and about 66 GHz, wherein the four channels are at 58.608 GHz, 60.720 GHz, 62.832 GHz and 64.944GHz. A method of wireless communication, comprising: generating a modulation analog signal to transmit content protection information corresponding to content via a wireless communication channel, wherein generating the modulation analog signal further comprises: using a low rate occupying a bandwidth of about 91 MHz The physical layer circuit (LRP) generates a low rate channel and generates a high rate channel using a high rate physical layer circuit (HRP) occupying a bandwidth of about 1.7 GHz, wherein the low rate is generated by the low rate physical layer circuit (LRP) The channel shares the same frequency band with a corresponding high rate channel generated by the high rate physical layer circuit (HRP) and operates the low rate channel and the high rate channel in a time division duplex (TDD) manner; and wherein the HRP includes Integrating one of an outer code circuit, an outer interleaver circuit, and M inner encoders, wherein M is greater than 1, and the external interleaver circuit includes a block interleaver, the block interleaver will be an outer codeword The consecutive bytes are mapped to different inner codes, and the same byte in the outer code code word is mapped to consecutive bits of the inner code. A method of wireless communication as claimed in claim 66, wherein the modulated analog signal is transmittable from four channels centered between about 57 GHz and about 66 GHz. The method of wireless communication of claim 67, wherein the four channels comprise 58.608 GHz, 60.720 GHz, 62.832 GHz, and 64.944 GHz. The method of wireless communication of claim 66, wherein the LRP comprises a series of parties A pilot carrier frequency modulation circuit, a carrier frequency interleaver circuit, an FEC circuit and a data scrambler circuit are coupled. The wireless communication method of claim 66, wherein the HRP comprises the outer code circuit coupled in series, the external interleaver circuit, an inner code circuit, a bit interleaver circuit, a carrier frequency interleaver circuit, and a Data scrambler circuit. A communication device, comprising: a processor; a radio frequency (RF) transmitter coupled to the processor and controlled by the processor to transmit content; a physical layer circuit coupled to the RF transmitter and The processor encodes and decodes between a digital signal and a modulation analog signal, wherein the physical layer circuit includes a high rate physical layer circuit (HRP) and a low rate physical layer circuit (LRP), the high rate Each of the physical layer circuit and the low rate physical layer circuit is operable in one of the RF transmitter directional mode, an omnidirectional mode, or a beamforming mode, wherein the omnidirectional mode, the physical layer The circuit will generate the same signal that is replicated N times, each replica using a different TX antenna phase field type, and wherein the HRP includes an outer code circuit coupled in series, an external interleaver circuit, and M inner encoders, wherein M is greater than 1, and the external interleaver circuit includes a block interleaver that maps consecutive bytes of outer codewords to different inner codes, and the outer codewords are The same tuple is mapped to consecutive bits of the inner code. The communication device of claim 71, wherein the signal comprises an OFDM symbol and N=8. The communication device of claim 71, wherein in the directional mode, the physical layer circuit will generate the same signal that is replicated N+1 times, each replica using the same optimized TX antenna phase field type, the optimized TX antenna phase The field type is fed back from a return channel receiver to a return channel transmitter. The communication device of claim 73, wherein the signal comprises an OFDM symbol and N=8.