TW200803236A - HD physical layer of a wireless communication device - Google Patents

Abstract

A radio frequency (RF) transmitter is coupled to and controlled by a processor to transmit data. A physical layer circuit is coupled to the RF transmitter to encode and decode between a digital signal and a modulated analog signal. The physical layer circuit comprises a high ate physical layer circuit (HRP) and a low rate physical layer circuit (LRP). The low rate channels generated by the low rate physical layer circuit (LRP) share a same frequency band as a corresponding high rate channel generated by the high rate physical layer circuit (HRP).

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the field of wireless communication; more specifically, the present invention relates to a wireless communication device using adaptive beamforming. [Prior Art] In 1998, the Digital Display Working Group (DDWG) was formed to replace the analog video graphics interface card (VGA) connection standard by establishing a common interface standard between the computer and the display. The resulting standard is the Digital Video Interface (DVI) specification issued in April 1999. There are several content protection mechanisms available. For example, High Frequency Wide Digital Content Protection (HDCP) and Digital Transmission Content Protection (DTCP) are well known content protection mechanisms. It is recommended to design HDCP as a security component of DVI and for the digital video monitor interface. The High Definition Multimedia Audio Interface (HDMI) is a connectivity interface standard developed to meet the explosive demand for high definition audio and video. HDMI is capable of carrying video and audio and is backwards compatible with DVI, which only carries video signals. The main advantage of DVI and HDMI is that both can transmit uncompressed high definition digital bit streams over a single cable. HDCP is a system for protecting content transmitted on DVI and HDMI from being copied. See HDCP 1.0 for details. HDCP provides authentication, encryption and revocation. The dedicated circuitry in the playback device and display monitor encrypts the video data and sends it out. With HDCP, the content is immediately encrypted (or internally) on the DVI or HDMI transmitter chip and decrypted immediately after (or inside) the DVI or HDMI receiver chip 118831.doc 200803236. In addition to the encryption and decryption functions, the HDCP performs authentication to verify that the receiving device (e.g., display, television, etc.) is authorized to receive the encrypted content. Re-authentication is performed approximately every two seconds to continuously confirm the security of the DVI or HDMI interface. At any one time, if re-authentication does not occur by, for example, disconnecting the device and/or connecting an illegal recording device, the source device (eg, a digital versatile disc (DVD) player, a video converter) Etc.) End the transfer of encrypted content.

While the discussion of HDMI and DVI is generally focused on wired communications, the use of wireless communications to transmit content has become increasingly popular. Although there is currently a lot of attention to cellular technology and wireless networks, there is an increasing interest in unlicensed spectrum near 60 GHz for wireless video transmission or very high speed network connections. More specifically, 'in the United States and Japan, the adjacent bandwidth of the open 7 coffee is used for unauthorized use at a millimeter wave frequency around 60 GHz. [Inventive content] A radio frequency (RF) transmitter is coupled to - #处理为 and controlled by the processor to transfer data. A physical layer circuit is attached to the RF transmitter to push and encode between a digital signal and a modulation analog signal. The physical layer circuit includes a high rate physical layer circuit (Η lWRP) and a low rate physical layer circuit (LRP). From the low-rate physical layer, the mine tail is reversed? The resulting low rate channel shares the same frequency band as the high rate channel corresponding to one of the high rate physical layer circuits 1). [Embodiment] 118831.doc 200803236 The present invention discloses an apparatus and method for wireless communication. In one embodiment, a wireless communication transceiver having an adaptive beamforming antenna is used for wireless communication. As is apparent to those skilled in the art, wireless communication can be performed using a wireless receiver or transmitter. In an embodiment, the wireless communication includes an additional link or channel for transmitting information between the transmitter and the receiver. This link can be unidirectional or bidirectional. In one embodiment, the channel is used to transmit antenna information from the receiver back to the transmitter, thereby enabling the transmitter to adapt its antenna array to find the path in the other direction by manipulating the antenna elements. This method avoids obstacles. In one embodiment, the link is also used to transmit information corresponding to wirelessly transmitted content (e.g., wireless video). This information can be content protection information. For example, in one embodiment, the link is used to transmit an encryption key and an encryption key confirmation when the transceiver transmits HDMI data. Thus, in one embodiment, the link transmits control information and content protection information. This extra link can be an independent channel in the 60 GHz band. In an alternate embodiment, the link can be a wireless channel in the 2.4 GHz or 5 GHz band. In the following description, numerous details are set forth to provide a more comprehensive explanation of the invention. However, the present invention may be practiced without these specific details, as will be apparent to those skilled in the art. In other instances, well-known structures and devices are shown in the form of block diagrams and are not shown in detail in order to avoid obscuring the invention. Some portions of the detailed description that follows are presented in terms of calculations and symbolic representations of operations performed on the information bits in the computer memory. Such performances 118831.doc 200803236 Different descriptions and representations are used by those skilled in the art to best convey the essence of their work to those skilled in the art. The algorithm is here and is generally envisaged as a self-consistent sequence of steps that produce the desired result. These steps are steps that require physical manipulation of physical quantities. Usually, although not necessarily, such quantities are in the form of electrical or magnetic signals that can be stored, transferred, combined, compared and otherwise manipulated. In principle, it has proven convenient at times, principally, to refer to such signals as bits, values, elements, symbols, characters, terms, numbers, or the like. However, it should be borne in mind that all such and similar terms should be combined with the appropriate physical quantities and are merely the convenience of the application. Unless otherwise expressly stated (as will be apparent from the description below), it should be understood that throughout the description, such as processing '' or π computing, or 'calculating' or 'determining' or 'display' The discussion of the terminology of , or the like, refers to the act and process of a computer system or similar electronic computing device, which is expressed as a physical (electronic) amount of data manipulation in a computer system register and memory. Transitions to other materials that are similarly represented as computer system memory or as a physical quantity in a storage or transmission or display device of such other information. The present invention is also directed to apparatus for performing the operations herein. The device may be specially constructed for the desired purpose, or it may comprise a general purpose computer, the brain being selectively activated or reconfigured by a computer program stored in the computer. The computer program may be stored in a computer readable storage medium. For example (=: limited to) any type of disc, including flexible disk, optical disc, optical read memory (CD-R0M) and magneto-optical disc, read-only memory (r〇m), Random 118831.doc 200803236 Access memory (RAM), erasable programmable read-only memory (epr〇m), electronic erasable programmable read-only memory (EEpR〇M), magnetic or optical card or any - Types are suitable for media storing electronic instructions, and each of these media is coupled to a computer system bus. The algorithms and displays presented herein are not intrinsically related to any particular computer or other device. Various general-purpose systems may be used in conjunction with the programs taught herein, or more specialized apparatus may be conveniently constructed for performing the required method steps. The structures required for the various such structures will appear from the description below. The invention is described with reference to any specific programming language. It will be appreciated that the teachings of the present invention as described herein can be implemented using a variety of programming languages. - Machine-readable medium includes any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, a machine-readable medium includes a memory ("ROM"); a random access memory ("RAM"); a disk storage medium; an optical storage medium; a flash memory device; electrical, optical , acoustic or other forms of propagating signals (eg, carrier waves, infrared signals, digital signals, etc.). An Example of a Communication System FIG. 1 is a block diagram of an embodiment of a communication system. Referring to W, the system includes a media receiver 100, a media receiver interface 1, a transmitting device 140, a receiving device 141, a media player interface 113, a media player 114, and a display 115. Media receiver 100 receives content from a source (not shown). In one embodiment, media receiver 100 includes a video converter. This content may include base 118831.doc •10· 200803236 frequency bit video, such as (but not limited to) within the range of 11]0]^1 or 〇¥1. In this case, media receiver i00 may include a transmitter (e.g., an 'HDMI transmitter) to forward the received content. The media receiver 100 transmits the content 1〇1 to the transmitter device 140 via the media receiver interface 1〇2. In an embodiment, the media receiver interface 1 〇 2 includes logic to convert the content 101 to HDMI content. In this case, the media receiver interface 102 can include an HDMI plug and the content 101 is transmitted via a wired connection; however, it can be transmitted via a wireless connection. In another embodiment, content 1 〇 1 contains D VI content. In one embodiment, the transfer of content 101 between media receiver interface 102 and transmitter device 140 is performed over a wired connection; however, the transfer can occur via a wireless connection. Transmitter device 140 wirelessly transmits information to receiver device 141 using two wireless connections. One of the wireless connections is via a phased array antenna with adaptive beamforming. Another wireless connection is via wireless communication channel 107, referred to herein as a back channel. In one embodiment, 'WirelessC# channel 10 7 is unidirectional. In an alternate embodiment, the wireless communication channel 107 is bidirectional. The receiver device 141 transmits the content received from the transmitter device 140 to the media player 114 via the media player interface 113. In one embodiment, content transfer between the receiver device 141 and the media player interface 113 is via a wired connection; however, the transfer can be via a wireless connection. In one embodiment, the media player interface U3 includes an hdMU# header. Similarly, content transfer between the media player interface 113 and the media player 114 118831.doc • 11·200803236 is via a wired connection; however, the transfer can occur via a wireless connection. The media player 114 causes the content to be played on the display 115. In one embodiment, the content is HDMI content and the media player 114 communicates the media content to the display via a wired connection; however, the transmission can occur via a wireless connection. Display 115 can include a plasma display, a liquid crystal display (LCD), a cathode ray tube (crt), and the like. Note that the system of Figure 1 can be modified to include a DVD player/recorder instead of a DVD player/recorder for receiving and playing and/or recording the content. In one embodiment, the transmitter 140 and media receiver interface 1〇2 are part of the media receiver 100. Similarly, in one embodiment, the receiver 14, the media player interface 113, and the media player 114 are all part of the same device. In an alternate embodiment, the receiver 14A, the media player interface 113, the media player 114, and the display 115 are all part of the display. An example of such a device is shown in Figure 3. In one embodiment, the transmitter device 140 includes a processor 101, an optional baseband processing component 104, a phased array antenna 105, and a wireless communication channel interface 106. The phased array antenna 1〇5 includes a radio frequency (RF) transmitter having a digitally controlled phased array antenna coupled to the processor 103 and controlled by the processor 103 for transmission using adaptive beamforming. Content to the receiver device 141. In one embodiment, the receiver device 141 includes a processor 112, an optional baseband processing component 111, a phased array antenna 11A, and a wireless communication frequency 118831.doc -12-200803236 track interface 109. Phased array antenna 110 includes a radio frequency (RF) transmitter having a digitally controlled phased array antenna coupled to processor 112 and controlled by processor 112 for use with adaptive beamforming from the transmitter device 140 receives the content. In one embodiment, processor 103 generates baseband signals that are processed by baseband signal processing 1〇4 prior to wireless transmission by phased array antenna 105. In this case, the receiver device 141 includes baseband signal processing to convert the analog signal received by the phased array antenna 110 into a baseband signal processed by the processor 112. In an embodiment, the baseband signal is an orthogonal frequency division multiplexing (OFDM) signal. In one embodiment, the baseband signal is a single carrier phase, amplitude, or phase and amplitude modulated signal. In an embodiment, transmitter device 140 and/or receiver device 141 are part of a separate transceiver. Transmitter device 140 and receiver device 141 perform wireless communication using a phased array antenna with adaptive beamforming that allows beam steering. Beamforming is well known in the art. In one embodiment, processor 1 (10) sends a digital control signal to phased array antenna 1 〇 5 to indicate the amount used to offset one or more phase shifters in phased array antenna 105, thereby Beams formed in a manner well known in the art. Processor 1丨2 also uses digital control information to control the phased array antenna 丨1 〇. The digital control information is transmitted using the control channel 121 in the transmitter device 140 and the control channel 122 in the receiver device ι41. In one embodiment, the digital control information includes a set of coefficients. In one embodiment, each of processors 1〇3 and 112 includes a digital signal processor. 118831.doc • 13· 200803236 The wireless communication link interface 106 is coupled to the processor i〇3 and provides an interface between the wireless communication link 107 and the processor 1〇3 to convey the use of the phased array antenna. Antenna information and convey information to help play content at another location. In an embodiment, the information transmitted between the transmitter device 14 and the receiver device 141 to facilitate playback of the content includes: an encryption key sent from the processor 103 to the processor U2 of the receiver device 141 and a Or a plurality of acknowledgments from the processor 112 of the receiver device 141 to the processor 103 of the transmitter device 14. The wireless communication link 107 also transmits antenna information between the transmitter device 14A and the receiver device 141. During initialization of phased array antennas 1〇5 and 11〇, wireless communication link 107 transmits information to enable processor 1〇3 to select direction for phased array antenna 105. In one embodiment, the information includes, but is not limited to, antenna position information and performance information corresponding to the antenna position, such as one or more pairs of signals including the position of the phased array antenna 110 and the channel used for the antenna positioning. Strength data. In another embodiment, the information includes, but is not limited to, sent by the processor 112 to the processor 1〇3 to enable the processor 1 to determine which portions of the phased array antenna 1 〇$ are used. Information about the content being delivered. When the phased array antennas 105 and 110 operate in a mode that can transmit content (e.g., HDMI content) during operation in the mode, the wireless communication link 107 transmits a pair of processor ι2 from the receiver device 141. An indication of the status of the communication path. The indication of the communication status includes an indication from processor 112 that causes processor 1〇3 to manipulate the beam in another direction (e.g., to another channel). This motivates the response to interference with the transmission of part of the content: 118831.doc -14- 200803236. This information may specify that processor 103 may use one or more alternate channels. In one embodiment, the antenna information includes information transmitted by processor U2 to specify a location, and receiver device 141 will direct phased array antenna 11 to this location. This mode is available during initialization during initialization when the transmitter device 14 informs the receiver device 141 where to locate its antenna for signal quality measurements to identify the best channel. The designated location may be an exact location or may be a relative location, e.g., one of the predetermined locations of the sequence of locations followed by the transmitter device 14 and the receiver device.

In one embodiment, the wireless communication link 101 transmits information from the receiver device 14 1 to the transmitter device 140 to specify the antenna characteristics of the phased array antenna or vice versa. One example of a V transceiver architecture Figure 2 is a block diagram of one embodiment of an adaptive beamforming multi-antenna radio system that includes a transmitter device 14A and a receiver device (4). Transceiver 200 includes a plurality of independent transmit and receive chains. The transceiver uses a phased array of the same chirp signal to perform phased array beamforming' and offsets the phase of the antenna or elements in the array to achieve beam steering. Referring to Figure 2, the digital signal processor (Dsp) 2〇i formats the content and produces an instantaneous baseband signal. The DSP provides modulation, FEC encoding, packet assembly, interleaving, and automatic gain control. The DSP 201 then forwards the baseband signal to modulate and modulate outward on the rf portion of the transmitter. In one embodiment, the content is modulated into an OFDM signal in a manner known to those skilled in the art 118831.doc • 15-200803236. A digital/analog converter (DAC) 202 receives the digital signal output from the DSP 201 and converts it to an analog signal. In one embodiment, the signal output from DAC 202 is a signal between 0 MHz and 256 MHz. In an alternate embodiment, the signal output from DAC 202 is a signal between 〇 MHz and 750 MHz. Mixer 203 receives the signal output from DAC 202 and combines it with the signal from local oscillator (LO) 204. The signal output from the mixer 203 is at the intermediate frequency. In an embodiment, the intermediate frequency is between 2 GHz and 15 GHz. A plurality of phase shifters 205_ receive the output from the mixer 203. A doubler is included to control which phase shifters receive signals. In one embodiment, the phase shifters are quantized phase shifters. In an alternate embodiment, the phase shifters can be replaced by a complex multiplier. In one embodiment, DSP 20 1 also controls the phase and magnitude of the current in each of the antenna elements in phased array antenna 220 via control channel 208, as is well known in the art. The way produces the desired beam pattern. In other words, the DSP 201 controls the phase shifters 205 Ν·Ν of the phased array antenna 220 to produce the desired field pattern. Each of the phase shifters 205〇-Ν produces an output that is sent to one of the power amplifiers 206〇-Ν that amplifies the signal. The amplified signal is sent to an antenna array 2〇7 having a plurality of antenna elements 2〇7G-N. In one embodiment, the signal transmitted from the antenna 207 〇 Ν is a radio frequency signal between 56 GHz and 64 GHz. Therefore, a plurality of beams are output from the phased array antenna 22A. For the receiver, the antenna 210〇_N receives the wireless transmission from the antenna 207G-N and provides 118831.doc -16 - 200803236 to the phase shifter 211〇_Ν. As discussed above, in one embodiment, the phase shifter 211 〇 _N includes a quantized phase shifter. Alternatively, the phase shifter 211 can be replaced by a complex multiplier. Phase shifter 211 〇-N receives signals from antenna 21 〇0_N, which are combined to form a single feed line output. In one embodiment, a multiplexer is used to combine signals from different components and output the single feed. The output of the phase shifter 211 〇 Ν is input to an intermediate frequency (ip) amplifier 212, which reduces the frequency of the signal to the intermediate frequency. In one embodiment, the intermediate frequency is between 2 GHz and 9 GHz. This frequency 213 receives the output of IF amplifier 212 and combines it with the signal from LO 214 in a manner well known in the art. In one embodiment, the output of mixer 213 is a signal in the range of 〇 MHz to about 250 MHz. In one embodiment, each channel has a ** and a q signal. In an alternate embodiment, the output of mixer 213 is a signal in the range of 〇 MHz to about 750 MHz. An analog/digital converter (ADC) 215 receives the output of mixer 213 and converts it to digital form. The digital output from ADC 2 15 is received by DSP 216. The DSP 2 16 restores the amplitude and phase of the signal. The DSP 201 provides demodulation, packet deassembly, deinterlacing, FEC decoding, and automatic gain control. In one embodiment, each of the transceivers includes a control microprocessor that establishes control information for the DSP. The control microprocessor can be on the same die as the DSP. DSP-Controlled Adaptive Beamforming In one embodiment, the DSP implements an adaptive algorithm that enables beamforming weighting to be implemented in hardware. That is, the transmitter and receiver work together to enable the beam shaping in the RRF frequency with a digitally controlled analog phase shifter; however, in an alternative embodiment, the beamforming system (4) performs . The phase shifters, 205G_N & 211()_N are controlled via control channels 2〇8 and control channels 217, respectively, via their respective DSPs in a manner well known in the art. For example, DSP 201 controls phase shifter 205〇n to cause the transmitter to perform adaptive beamforming to manipulate the beam, while DSP 201 controls phase shifter 211〇ν to direct the antenna element to receive wireless transmissions from the antenna elements and combine Signals from different components form a single feeder output. In one embodiment, a multiplex is used to combine signals from different components and output the single feed. The DSP 201 performs beam steering by pulse or excitation, and a suitable phase shifter is connected to each antenna element. The pulse algorithm under DSP 201 controls the phase and gain of each component. Phased array beamforming to perform DSP control is well known in the art. Adaptive beamforming antennas are used to avoid interference barriers. By adapting the beamforming and steering the beam, communication can be avoided without hindering the wireless transmission between the transmitter and the receiver. In an embodiment, with respect to an adaptive beamforming antenna, it has three phases of operation. The three operational phases are the training phase, the search phase and the tracking phase. The training phase and the search phase are performed during the initialization period. The training phase determines the spatial profile of the predetermined sequence (4} and the channel profile. The search phase calculates the list of candidate spatial patterns {4}, {巧}, and selects a preferred {4, smart} for use in a transceiver. Data transfer between the transmitter and the receiver of the other transceiver. The tracking phase keeps track of the strength of the candidate list. When the first choice is blocked, the next pair of spatial fields are selected for use. 118831.doc -18- 200803236 In an embodiment, during the training phase, the transmitter transmits a sequence of spatial patterns {4} outward. For each spatial pattern {4}, the receiver projects the received ## to another The result of the projection is: the channel profile is obtained on the pair of {4}, {巧}. In an embodiment, thorough training is performed between the transmitter and the receiver, wherein the receiver The antenna is positioned at all locations and the transmitter transmits multiple spatial patterns. Thorough training is well known in the art. In this case, one transmission space pattern is transmitted by the transmitter and received by the receiver. Receive spatial field type to form a frequency The track matrix. Therefore, the transmitter traverses the field pattern of the transmission sector and the receiver searches to find the strongest signal for the transmission. Then, the transmitter moves to the next sector. At the end of the thorough search process, the transmitter is obtained. And the grading strength of all the positioning of the receiver and the nickname of the channel at the same position. The information remains the pairing of the position indicated by the antenna and the signal strength of the channel. This list can be used to control the antenna beam in the presence of interference. In an alternate embodiment, two-segment training is used in which the transmitted positive parent antenna field type divides the space into successive narrow segments to obtain a channel profile. False DSP 1 〇 1 is in a steady state and the antenna The direction that should be pointed is determined. In the nominal state, the DSP will have a set of coefficients that it sends to the phase shifter. The equal coefficient is the phase of the corresponding antenna indicating the phase shifter offset signal. For example, DSP 1 〇1 sends a set of digital control information to the phase shifter' indicating that different phase shifters will shift different amounts, for example, offset by 3 degrees, offset by 45 degrees, offset by 90 degrees, offset by 180 degrees Therefore, the phase of the signal sent to the antenna 118831.doc -19·200803236 will be offset by a certain number of degrees. For example, the 16, 36, 32, 64 components in the array are offset by different amounts of the final result to make the antenna It can be manipulated to provide the most sensitive receiving position for the receiving antenna. That is, the offset of the composite combination on the entire antenna array provides the ability to change the position of the most sensitive point of the antenna on the hemisphere. In an example, the appropriate connection between the transmitter and the receiver may not be a direct path from the transmitter to the receiver. For example, the most appropriate path may bounce back from the ceiling. In one embodiment, the wireless channel The communication system includes a return channel or link for transmitting information between wireless communication devices (e.g., transmitters and receivers, a pair of transceivers, etc.). This information relates to beamformed antennas and this information enables one or both of the wireless communication devices to adapt the array of antenna elements to better direct the antenna elements of the transmitter to the antenna elements of the receiving device. The information also includes information that facilitates the use of content that is wirelessly transmitted between the transmitter and receiver antenna elements. In FIG. 2, a return channel 220 is coupled between the DSP 216 and the DSP 201 to enable the DSP 216 to send tracking and control information to the DSP 201. In one embodiment, the return channel 220 acts as a high speed downlink and acknowledge channel. In one embodiment, the return channel is also used to communicate information corresponding to the application, and the wireless communication is performed for the application (e.g., wireless video). This information includes content protection information. For example, in one embodiment, the return channel is used to transmit encrypted information (e.g., an encryption key and an encryption key confirmation) when the transceiver transmits HDMI material. In this case, the return channel uses 118831.doc -20- 200803236 for content protection communication. More specifically, in HDMI, encryption is used to verify that the data store is a licensed device (eg, a licensed display). When the HDMI stream is transmitted, a continuous stream of new encryption keys is transmitted to verify that the licensed device has not been altered. The blocks of the HD TV data frame are encrypted by different keys, and then the keys must be returned on the return channel 220 for confirmation to verify the player. The return channel 220 transmits the encryption key to the receiver in the forward direction and transmits the confirmation of the key reception from the receiver in the return direction. Therefore, the encrypted information is sent in both directions. The use of a return channel for content protection communication is beneficial because it avoids having to complete a very long retraining process when the communication is sent with the content. For example, if the key from the transmitter is sent along with the content flowing through the primary link and the primary link is disconnected, for a typical HDMI/HDcp system it will impose a very long 2 seconds to 3 Retraining in seconds. In one embodiment, the separate bidirectional link has higher reliability than the primary direction link giving its omnidirectional orientation. By using this return channel for the HDcp key and communication from the receiving device's return acknowledgment, time-consuming retraining can be avoided even with the most impulsive obstacles. During the active period, when the beamforming antenna is transmitting content, the return frequency j is used to allow the receiver to know the state of the transmitter with respect to the channel. For example. When the channel between the S beamforming antennas is of sufficient quality, the receiver sends a message on the return channel to indicate that the channel is acceptable. The receiver can also use the return channel to send transmitter measurable information indicating the product f of the channel being used. If there is some form of interference (eg, 118831.doc • 21 · 200803236, if obstructed), it degrades the quality of the channel below an acceptable level or prevents complete transmission between beamforming antennas, then receives The device may indicate that the channel is not acceptable and/or may require a change in the channel on the return channel. Receiver: Requires a change to the next channel in the - scheduled group, or a specific channel can be assigned to the transmitter for use. In an embodiment, the return channel is bidirectional. In this case, in a = example, the transmitter uses the return channel to send information to the receiver. This messaging may include information that the command receiver positions its antenna elements at different fixed positions (the transmitter will scan for such positions during initialization). The transmitter may specify this by either explicitly indicating the location, or by indicating to the receiver which 5 x l2r ^ should only proceed to a predetermined order or list (transmitter and receiver) All of them travel through the position indicated by this order or list). In one embodiment, the return channel and the Iw back channel are used by either or both of the transmitter and the receiver to notify the other of the specific green primary antenna characteristics. For example, a hai antenna characteristic information can be reduced. The antenna antenna accepts a radius resolution as low as 6 degrees and the antenna has a certain number of components (for example, 32 components, 64 components, etc.). In one embodiment, the communication is performed on the return channel as soon as it is used. Any type of wireless communication can be used. In an embodiment, OFDM is used to obtain a broadcast on the return channel. In another embodiment, a low peak-to-average power ratio /, continuous phase modulation (CPM) of the drought is used to transmit information on the θ-back channel. SHIkou Physical Layer (ΡΗΥ) Overview 118831.doc -22- 200803236 The Wireless HD specification supports two basic types of PHYs: High Rate PHY (HRP) and Low Rate PHY (LRP). According to an embodiment, the HRP supports data rates of multiple Gbps. HRP can operate in a directional mode (usually beamforming mode). HRP can be used to transmit audio, video, data and control messages. The LRP can only be sent from the HTx/HTR unit to the HRx/HTR unit. In an embodiment, the HRP occupies a bandwidth of approximately 1.7 GHz. According to an embodiment, the LRP supports multiple data rates of Mbps. The LRP can operate in either directional, omnidirectional or beamforming mode. In an embodiment, the LRP can be used to transmit control messages, beacons, and acknowledgments. In an alternate embodiment, the LRP can be further used to transmit audio or compress video. In yet another embodiment, the LRP can be further used to transmit low speed data. LRP can be sent between any device. The LRP occupies one of the three 9 1 MHz subchannels of the HRP channel discussed below. Frequency plan HRP and LRP can share the same frequency band. Figure 4 illustrates one embodiment of a frequency plan for HRP and LRP. The low rate channel 404 shares the same frequency band as the corresponding high rate channel 402. The three low rate channels 1A, IB, 1C can be configured in each high rate channel bandwidth (channel 1) to avoid interference. According to another embodiment, the low rate and high rate channels can operate in a time division duplex mode. Figure 4 illustrates four examples of channels between 57 GHz and 66 GHz: Channel 1 operates between 57.2 GHz and 59.2 GHz, Channel 2 operates between 59·4 GHz and 61.4 GHz, and Channel 3 operates at 61.6 GHz. Operating between 63.6 GHz, channel 4 operates between 63.8 GHz and 65.8 GHz. 118831.doc •23· 200803236 A single low-cost crystal oscillator can generate these frequencies. The baseband clock frequency can approach 2. 5 GHz (for example, 2.508 GHz). According to an embodiment, the frequency plan can support the design of an easily implemented RF synthesizer. The resulting center frequencies can be: 58.608 GHz, 60.720 GHz, 62.832 GHz, and 64.944 GHz. Possible crystal frequencies can include 44 MHz, 66 MHz, and 132 MHz. High-rate PHY (HRP) HRP supports data rates of 3.76 Gbps, 1.88 Gbps, and 0.94 Gbps. The data rate can be individually matched to the video resolution standards of 1080p, 1080i, and 480p for various sampling rates. Therefore, this range can be increased at lower data rates. A higher PHY rate can still allow multiple lower rate streams via the MAC. HRP can utilize several types of coding and modulation: OFDM, 16QAM and QPSK modulation, internal convolutional codes (1/3, 2/3, 4/7, 4/5 rates) and Reed-Solomon (Reed) at a rate of 0.96 -Solomon) Outer code. In addition to the internal convolutional code, the Reed-Solomon outer code uses a lower SNR requirement of approximately 2 dB. An external interleaver can be used to achieve full gain of the outer code. HRP can utilize four channels for the channel bandwidth of 1.7 GHz over the global 60 GHz band. According to an embodiment, there may be three channels per region. HRP can be extended to include parallelization of FEC streams for cost-saving implementation and support for unequal error protection (UEP) concepts. Figure 5A illustrates an embodiment of a Tx PHY block diagram. The scrambler 502 receives the LMAC data and feeds it into the MSB/LSB separation block 504. For 118831.doc -24- 200803236 MSB, you can do it. RS, flat code 506 and external interleaver 510. For the LSB, the RS encoder 5〇8 and the external interleaver can be used. The breakdown circuit can be turned into a surface, and the P-interlaced 510 and 512. The following circuit is formed in the breakdown circuit 5 14 /, the factory multiplexer 5 16 , the bit interleaver 51 8 , QAM mapping

"Carrier frequency" parental error 522, pilot/DC/null value insertion 524 and IFFT 526 〇> HR: outer code interleaver 51G, 512 may include a block interleaver and a convolutional error. The function of the device is to ensure that the tuples of the outer code are mapped to successive bits of the inner codeword, and that the consecutive bytes of the outer code are mapped to different inner codewords. The block interleaver requires There is almost no hidden body in the transmitter and the efficiency can be improved without zero insertion. The tail part can be easily added by the external interleaver. The cyclotron requires several shift registers in the transmitter and has zero In the case of insertion, the efficiency may be degraded. When using the convolutional interleaving, four 〇FDM symbols (symb〇1) may be required to transmit the initial/final zero in the shift register. The efficiency may be approximately 〇·5. The % is downgraded to about 2%. The block external interleaver 51A, 512 minimizes the memory requirements between the Reed-Solomon outer code and the internal whirling code. In one embodiment, the block interleaver depth (depth) is 4 and there are M = 4 internal cyclotron encoders for each external interleaver. External The block interleaver will operate at a depth of four for the HRp data. In one embodiment, the block interleaver can be implemented by a table of octets such that the number of rows is the same as the depth and the number of columns is The length of the De-Solomon code is the same: b(i,k),i = 〇,1,...,depth -1; k = 〇山·. ·, N -1 印,幻,机特别+7入.·. The octet is b(i 〇), 118831.doc -25- 200803236 b(i,l),..., the octet of the Reed-Solomon code parity, where RS(N, K) is a Reed-Solomon code. In one embodiment, the parameters of the external interleaver are, K = 216 and N = 224. In another embodiment, the block interleaver is in the group of bits (referred to as Operation is performed on a byte. In another embodiment, each tuple has 8 bits or an octet. In another embodiment, each tuple has more than 1 bit. Figure 5B An example of a block interleaver code is shown. To reduce memory requirements, the following formula should be used for the mapping to the row and column of Figure 5B: i = floor {[l mod(depth * Μ)]/ Μ} k = M floor [l /(depth * M) +1 mod M 1 = 0 l "", -1 where / the number of octets depth * K at an external input of the interleaver. The external interleaver can output octets from the beginning i = 〇, 介 = 0 to the last i = 3 叩 / /2-7. In the case where Μ is in parallel with the whirling internal encoder of each RS codeword, the external interleaver assigns an octet of b(0,0),...,叩绐-7, to the first whirling encoder to LSB headed by. All octets of b(i,k*M+m)(i = Q,...,depth-1,1(:=0, 1,...,N/MJ) will be output to the mth cyclotron encoder The end of the whirling encoder is inserted by an external interleaver. The behavior of a co-located bit in Figure 5B is located at b (depth-l, KM-9), b (depth-l, KM-8),..., b(depth -l, KM-" at the shortened RS (NM, especially - Μ, ί = code. People iV- break in..., b (depth-l, Ν-1) bit paper on zero blessing. Figure 6 The various parameters of the HRP are illustrated in three different tables (602, 604, 606). Tables 602 and 604 illustrate different parameters of the HRP in accordance with the present invention. Table 118831.doc -26-200803236 606 illustrates the HRP in different modes. Support rate. One embodiment of the HRP inner code circuit is illustrated in Figures 7 and 8. Figure 7 illustrates a circuit diagram 700 of an HRP inner code. The polynomial of (133, 171, 165) can be used to describe the inner code circuit. Figure 8 illustrates the HRP. The table of the code rate, breakdown field type and transmission sequence of the inner code circuit. The breakdown type means that the breakdown or deletion and the breakdown of the field type "1" means no breakdown or deletion. 3.9 Gps data rate, may require a cyclotron encoder In one embodiment, a base 4 accumulation-comparison-selection technique can be used at the receiver. The base 4 ACS processes 2 bits in each cycle. The required clock frequency is equal to 3.9 Gps divided by the decoder. For example, for 8 decoders, a clock of 244 MHz may be required. HRP data multiplexer 516 can combine data from 8 cyclotron encoders. The mode can be determined by EEP or UEP. In the EEP mode, a round robin mechanism is implemented to evenly allocate bits. In the UEP modulation mode, the MSB corresponds to the I branch of the QAM mapper, and the LSB corresponds to the Q branch of the QAM mapper. In the UEP coding mode, The strong MSB convolutional code causes the MSB bit at the input of the data multiplexer 516 to be more than the LSB bit. The block of 4 input bits (32 in total) of each of the 8 convolutional encoders can be represented. One of the field-through modes is full-cycle. The UEP coding mode can cause 28 MSB bits and 20 LSB bits at the output of the cyclotron encoder, which are mapped to 48 transmission bits scattered over I and Q. HRP bit interleaver 518 can spread bits from HRP data multiplexer 516 to QAM or QPSK Group/Q-branch. The MSB and LSB of the QAM cluster do not provide the same encoded BER. The bit interleaver ensures the same BER for each element stream from the same 118831.doc -27-200803236 inner code encoder The metastreams are mapped to an equal number of MSBs and LSBs of the qAM cluster. The following is a suggested solution: P16 : 0, 1,2, 3, 4, 5, 6, 7, 9, 8, 11,1, 13, 12, 15, 14 , so i=M*fl〇or (k/M)+mod(2*fl〇〇r(k/2)+m〇d(k+fl〇〇r(k/M), 2), M),k=0,l”,2M_l , where in the block of 2M=16, 丨 is the index of the output bit, and k is the index of the input bit. P32 : 0, 1, 2, 3, 4, 5, 6, 7, 11, 8, 9, 10, 15, 12, 13, 14, 18, 19' 16,17, 22, 23, 20,21,25, 26,27, 24, 29, 30, 31,28, make i=M*fl 〇or(k/M)+m〇d(4*fl〇〇r(k/4)+m〇d(k+fi〇〇Kk/M), 4), M),k=0,l” ..4M-l, where in the block of 4M=32, 丨 is the index of the output bit, and k is the index of the input bit. The above solution is illustrated graphically in Figures 9 and 1〇. In the HRp channel with frequency selective fading, the different symbols of the circle symbol can have different channel responses and the adjacent subchannels are hanged and the same fading effect. To improve performance, the carrier interleaver maps the data to a distant DMFDM subchannel. In an embodiment, the Twisted Spiral Scanning Carrier Interleaver can include the following solutions: TMod(fl〇〇r^l4)*24W(k524), k^ /, where is the index of the output carrier tone and & is the index of the input carrier frequency. The above solution is illustrated graphically in Figure u. In an alternate embodiment, the carrier shift interleaver can be designed based on the bit reverse principle 118831.doc -28-200803236. In the actual implementation of IFFT, there is a one-bit inverse circuit before or after the IFFT calculation. In the bit-reverse circuit, the index of the input data first appears as a binary digit, and the resulting binary representation indicates that the legal system bit is inverted, and the reverse binary digit of the bit becomes the index of the output data. When using the bit-reverse carrier-frequency parental error, the carrier-shift interleaver and the IFFT calculation can be combined. The IFFT calculation circuit is embedded in a bit-inverse carrier-shift interleaver. The Dc, null, and pilot carrier tone are reversely positioned before the bit inserted into the carrier interleaver. In this way it is guaranteed that the DC, null and pilot carrier tones will appear in the pre-specified position after the alignment. Using the traveling pilot as will be described later, the bit reverse positioning for the pilot is sequentially changed in OFDM symbols. When used in a base 2 IFFT implementation (which uses multiple 2x2 basic architecture blocks), the bit reverse carrier interleaver can perform optimal operation. For example, for a base 8 IFFT implementation using multiple 8-shirt architecture blocks, the index of the input data should first be represented as an octet, and the octet inverse number as the output data. In this particular example, the octet reverse carrier interleaver provides the simplest implementation for combining the carrier interleaver and IFFT. HRP pilot 524 may include a rotating pilot mechanism to vary the pilot carrier per symbol, thereby allowing for better channel tracking of packets as necessary. This approach also avoids having to change the polarity of all pilots from one FDM symbol to the next OFDM pay according to the coverage sequence. The pilot value can be the same as the carrier frequency of the corresponding HRP preamble #5 (described later). The pilot carrier tone position can be defined by a symbol index starting with a preamble #5. For symbol=0:NsymboM,k=(.177+m〇d(3*symbol? 22):22:177), where k! = {-l,0,l}. According to an embodiment, the pilot rotational speed can be fixed, 118831.doc -29-200803236 to rotate each symbol by 3 bins. Conversely, if the pilot position is fixed, its value will need to change over time to avoid any spectral ripple effects. The HRP preamble can include 8 symbols. Symbols #1-#4 can be based on a PN sequence. Six consecutive m-sequences can be used in 4 symbols. Symbols #1-#4 can be used for packet detection, frame synchronization based AGC training. Symbol #5·#8 can be based on OFDM symbols and can be used for frequency offset estimation and channel estimation. According to an embodiment, scaling factor correction can be used to maintain the power of the eight preamble symbols the same as the remaining OFDM symbols used for data transmission. In one of these embodiments, the power of symbols #1-#4 can be 3 dB greater than the symbols #5-#8. Figure 12 illustrates one embodiment of an external FEC for an HRP header. The HRP header external FEC is somewhat similar to the external FEC for HRP data because it provides the same or better error protection as the data. It uses the same Reed-Solomon generator. It uses the same method to provide a tail element to terminate the whirling codeword. It uses the same Reed-Solomon decoder in the receiver. Four OFDM symbols can be used for the HRP header with 112 coded bytes at 1/4 rate. The HRP header FEC can use the same RS code generator polynomial as the data. The HRP header FEC may include 92 or more uncoded bytes. A coded branch may include four cyclotron encoders having four tail position tuples 1202. The depth of the HRP header FEC can be 2 bytes 1204 and 1206. The byte 1204 can include 44 data bytes, 8 parity bits, and tail location 1202. The byte 1206 can include 48 data bytes and 8 parity bits. The depth of the two block interleavers provides sufficient performance. Figure 13 illustrates one embodiment of an HRP data scrambler. A 15th polynomial (xI5+x14+l) can be used to improve the randomness of the transmitted data for HRP 118831.doc -30- 200803236. Figure 13 illustrates an initialization sequence with four bits at locations D12 through D15 (where D15 is first). Low Rate PHY (LRP) LRP can be used for MAC § hole frame transmission (eg, ack, beacon, discovery 4), for low rate (less than 4 Mbps) streams from A/V sources, for antenna manipulation and tracking The transmission of the data used. The LRP can be designed with a BPSK modulation based on OFDM of 128-point FFT and a gyro code of 1/3, 1/2 and 2/3 rates. The Wade-Solomon code is not required, because of the short message and the BER tolerance of the south. LRP can operate in three modes: lrp omnidirectional (long) mode, LRP beamforming mode, and LRP oriented (short) mode. These different modes are discussed further below. Figure 14 illustrates one embodiment of LRP Tx processing. LRP circuit can include scrambling code

The device 1402, the FEC 1404, the interleaver 1406, the mapping 1408, the IFFT 14 16, the cyclic first code 1414, the symbol shaping 14 12, and the up-conversion 141 〇. Figure 15 illustrates a table of LRP feed rates. As shown, different lrp modes produce different LRP data rates. The LRP pilot and data carrier frequency can be defined as follows: 128-point FFT, 30 data carrier frequency modulation and 4 pilot carrier frequency adjustments, and three unused carrier frequency adjustments at DC (carrier frequency adjustment number -1 , 〇 and 1), the pilot carrier frequency adjustment can be modified, and the fixed pilot carrier frequency adjustment at the carrier frequency number -14, -6, 6 and 14 is at all other positions from -Η to +18. The data carries the tone. The LRP scrambler 1402 can use a 6th degree polynomial. The scrambler initialization field can be 4 bits. To initialize this polynomial, the 4-bit initialization field can be concatenated with the 01 bit. 118831.doc -31- 200803236 In LRP omni mode, the resulting signal is omnidirectional, with at least as large as the any-forward channel mode, allowing for a stronger eve than the forward channel. . The line rate in LRP omni mode can range from about 5 Μ to about 10 Mbps with a target BER of less than 1 〇·6. In LRp omni mode, each signal is transmitted multiple times using different antenna patterns. In one embodiment, the (four) solid + same antenna pattern is used to repeat the money 8 times. In an embodiment, different antenna patterns are orthogonal to one another. Therefore, each copy uses a different TX phased array setting (exchanged during the first cycle of the cycle). The receiver can use MRC or similar technology to combine the copies. Diversification of space helps maintain omnidirectional coverage. Figure 16 δ 明 L LRP omnidirectional data packet format, which includes: pre-column 1602, header 1604, payload ι606. Header 16〇4 may include mode 1608, reserved 1610, length 1612, scrambler init 1614, and CRC-8. Header 1604 is a long format having 30 bits encoded as 2 〇Fdm symbols having a 1/2 rate tail portion elementary convolutional code. When the tail element is used, the initial and final states of the whirling code are the same. In one embodiment, the last six information bits of the header can be used to initialize the state of the cyclotron encoder. The LRP full forward term 1602 can include two types: a long omnidirectional preamble and a short full forward term. The long full forward term can be about 56.67 microseconds. This type of preamble can be used for beacons and other LRP data packets that require blind timing synchronization.

Figure 17 illustrates an embodiment of a long full forward term 1700 having six segments (with 17766 samples): automatic gain control (AGC) and signal detection segment 1702, coarse frequency offset estimation (FOE) and Timing recovery section 1704, fine FOE 118831.doc -32-200803236 and timing recovery section 1706, RX beamforming section 17〇8, agC section 1710, and channel estimation section 1710. The first three preamble segments 丨7〇2, 1704, and 1706 are composed of a sequence of offset-QPSK modulated chips (chip rate is 156.75 ΜΗζ (one of the sampling rate)). The chips are filtered to match the 91 MHz LRP transmission mask. The domain of the AGC and signal detection section 1702 contains 78 symbols, each of which is defined by Barker_13 for the I and Q components ([-1 -1 -1 -1 _ι 1 i -1 -1 1 -1 1 -1]) 1 or -1 dispersed by the chip sequence. The symbol sequence {Sk}(Sk=Tl) is constructed by differential encoding of 26 repetitions of the three symbol sequence J = [-1, 1, -1 ], specifically & = , center = 1. The domain of the coarse FOE (Frequency Offset Estimation) section 1704 contains 81 symbols, where each symbol is defined as 1 or _1 dispersed by the Buck-13 chip sequence for the I and Q components. The symbol sequence is constructed by the differential coding of 9 repetitions of the nine-symbol sequence /^7 = [-1 ·1 -1 -1 1 1 -1 1 -1], specifically, Ai + k^SM + kl Xh 'where S〇 is the last symbol of the previous field. The fields of the fine FOE and timing recovery section 1706 are comprised of a 1440 PN chip sequence for the I and Q components generated by the polynomial x72+;c"+/+x6+l under the initial conditions of 0xB95. The domain of the RX beamforming section 1708 consists of a 2560 PN chip sequence for the I and Q components, which is generated under the initial conditions of 101001 using polynomial +7. The AGC section 1710 is 20 repetitions of an OFDM training symbol of 32 samples long, which is equal to the IFFT of the following BPSK 32-point sequence: subcarriers 4 to 4 are equal to {1 1 1_10-1-1 1-1} and all others Equal to zero. 118831.doc -33- 200803236 The channel estimation section 1712 consists of 32 128 sample OFDM training symbols 'here each equals the following 128 points 3!> 8 £ sequence (previously 28 sample loop first code) IFFT : subcarrier 2-18 is equal to {1-1 i-1-i 1-1 1 1 1 1 1 1 -1 -1 1 1}, subcarrier _18 to _2 is equal to {_1 1 1 1 1 1 d 1 -1 1 -1 -1 -1 1 -1 1}, and all others are equal to zero. The TX antenna phased array field pattern can be varied at regular time intervals for each of the five fields in the LRP full forward term 16〇2. Therefore, for eight τχ antennas, the TX phased array is changed for every 78, 234, 160, 640, 64, and 156 samples for each of the above five domains. The short full forward term can be about 42.72 microseconds. This type of preamble can be used in the contention period (for slotted CSMA) and other LRP data packets that require only limited (+/_ 135 nanoseconds) timing synchronization. Figure 18 illustrates an embodiment of a short full forward term 1800 having six segments (13392 samples): AGC segment 1802, AGC segment 1804, signal detection and time synchronization segment 1806, RX beamforming Section 1808, AGC section 18 10 and channel estimation section 1812. The first four preamble fields 18〇2, 18 04, 1806, 1808 consist of a sequence of BPSK chips (chip rate 156.75 MHz (each chip equals 2 samples)), which are filtered To cover the 91 MHz LRP transmission mask. The chip sequence is generated by repeating the 63-tap M_ sequence to be specified. The first two domains, 1802 and 1804, are AGC fields with lengths of 336 and 2 64 chips, respectively. The third field 1806 is 720 chips in length and is used for debt measurement LRP packets and for timing synchronization in a window of -/+13 5 nanoseconds. The fourth field 1808 is 2560 chips in length and is used for rx beamforming. The second AGC field 1804 is a 32-sample length 〇fdm training symbol 118831.doc -34- 200803236 20 repetitions, which is equal to the following BPSK 32-point sequence IFFT: subcarriers _4 to 4 are equal to {1 1 l-lO -i-i丨·”, and all others are equal to zero. Channel estimation field 1812 consists of 32 128-sample OFDM training symbols, each of which is equal to the following 128-point BPSK sequence (previously 28 sample cycle first code) IFFT: Subcarrier 2-18 is equal to {1 -1 1 -1 -1 1 -1 1 1 1 i 1 1 -1"i 1}, subcarrier -18 to -2 is equal to {-1 1 1 1 1 1 -1 - 1 1 -1 i -ΐ ·ι < i -1 1}, and all others are equal to zero. The TX antenna phased array pattern can be changed at regular time intervals for each of the five fields in the short full forward term. Therefore, for eight ΤΧ antennas, the ΤΧ phased array is changed for every 32, 48, 160, 640, 64, and 156 samples for each of the above six domains. In the LRP beamforming mode, the same technique as hrp beamforming can be used. This mode is the highest data rate but is oriented and requires beam updates. Figure 19 illustrates an example of a data packet format 19 of LRP beamforming that includes a short preamble 1902, a header 1904, and a valid bearer 1906. Header 1904 can be 30 bits that are encoded as 3 symbols, which have a 1/3 rate tail elementary convolutional code. The LRP beamforming preamble 1902 allows for blind timing synchronization and has a structure similar to the HRP PDU preamble. Figure 20 illustrates one embodiment of an LRp beamforming preamble 2000. The LRP beamforming preamble 2〇〇〇 packet length is 7.96 耄 seconds (2496 samples)' and contains two fields: frame synchronization and agc domain 2004 and channel estimation domain 2006. Frame synchronization and AGC field 2004 consists of a sequence of BPSK chips (chip rate 156 75 MHz (each chip equals 2 samples)), which are filtered by 118831.doc -35-200803236 to match 91 MHz LRP transmission mask. The chip sequence is equal to 14 repetitions of the 63-tap M-sequence specified for 936 chips, where the sequence is modulated/multiplied by [1 1-1-1 1 1 1 111-1-1111], respectively. As illustrated in the sequence 2002 of Figure 20 (where the plus and minus signs mean that the corresponding samples are multiplied by 1 or -1, respectively), the channel estimation field 2006 repeats the time domain samples of the 128 OFDM training symbols by repetition (this Constructed in Table 3 5 in the frequency domain. In LRP directional mode, the resulting signal has a similar range as in the forward channel, requiring only "reverse, hardware (ie, less iRx/Tx). In LRP directional mode, the best antenna is used. The field pattern repeats each signal a plurality of times. In one embodiment, the optimal antenna pattern is selected from the eight possible antenna patterns used in the omni mode. In one embodiment, each signal repeats 5 (= 4 + 1) or 9 (= 8 + 1) times. The optimized τχ phased array pattern can be tracked, for example, every 1 。 packet. The best TX diversified field type self-return channel receiver feedback Return channel transmitter. Line rate in LRP directional mode can be from about $ Mbps to about 10

Mbps. The directional LRP packet can be used as an ACK to confirm HRp or beamforming LRP, data packets with or without additional payload. Figure 21A illustrates a short 15-bit ACK header without a valid bearer. Figure 21B illustrates a 16-bit short ACK header with a valid bearer. The directional LRP short ACK header is encoded by a 1/2 rate tail element gyro code and transmitted by a 〇 FDM symbol. For a directional LRp packet with a payload (second format), the 位 bit selects one of the following two non-beamforming ρ Η data rates: 118831.doc -36 - 200803236 5 Mbps : mode bit = 0 10 Mbps : Mode Bit = 1 In LRP Orientation mode, information is encoded by a 2/3 rate convolutional code. If the tail part element can be used to reduce the number of OFDM symbols, the tail bit is used. Otherwise use at least 6 consecutive zeros to terminate the interleaving of the whirling code. For these packages, the postamble flag specifies a post-item (flag = l) or no (flag = 0) attached to the packet. Figure 22 illustrates a certain forward LRP packet preamble 2200. The LRPPDU preamble of the directed packet is 2.04 milliseconds (040 samples) in length and contains 5 OFDM training symbols as shown here. The first symbol 2202 is for AGC and the next 4 symbols are used for channel estimation and frequency offset estimation 2204. Pre-sets allow for limited (-/+150 nanoseconds) timing inaccuracies. Figure 23 illustrates antenna direction tracking for directional LRP packets. As mentioned, directional LRP packets are used for HRP or beamforming (BF) LRP packets. The packets use the best TX antenna direction from a group of up to 8 antenna directions, wherein optimizing the TX antenna direction needs to be tracked over time using a special frame structure as described in Figure 23. For each rule HRP / short - eight (:: ^ or beamforming 丄 10 > / short - eight (: 1 ^, can be formed as shown in Figure 23, 23 00. There is a pair with the following special structure HRP/short-ACK or beamforming-LRP/short-ACK frame, where HR/LR beam tracking and LR antenna direction tracking (ADT) occur as illustrated in 2302 of Figure 23. As shown, antenna direction tracking This occurs in two phases: (1) by optimizing the ΤΧ antenna direction by using a dedicated post-term and (2) by RX beamforming/tuning the selected ΤΧ antenna direction by using a dedicated preamble. .doc -37- 200803236 The selected antenna direction index between the above two phases is fed back from short ACK RX to short ACK TX via an HRP or beamforming LRP packet. Figure 24 illustrates a Tx antenna direction tracking post item 2400. The ΤΧ antenna direction tracking post-term for directional LRPPDU is attached to a directional LRP packet with payload. The TX ADT post-term is 9.24 microseconds (2896 samples) and contains three segments 2402, 2404, 2406. Two post-term fields 2404, 2406 follow a protection time of 2.04 milliseconds 2404 and consists of a sequence of BPSK chips (chip rate of 156.75 ΜΗζ (each chip equals 2 samples)), which are filtered to conform to the 91 MHz LRP transmission mask. The chip sequence is repeated Generated by a specified 63 tap M-sequence. The second field 2404 is used for AGC and has a length of 264 chips. The third field 2406 is 864 chips long and is used to select the best among the 8 antennas. TX diversity combination. The TX antenna phased array field type changes according to the regular time interval of the post item. For 8 TX antennas, the TX phased array is for every 48 and 192 of each of the above 2 domains respectively. The sample is changed. Figure 25 illustrates a Tx antenna direction tracking preamble 2500. The RX ADT preamble is added to the directional LRP packet without payload and used for RX beamforming for the selected TX antenna direction. This additional preamble consists of two sections 2502, 2504 (1152 samples) consisting of a sequence of BPSK chips (chip rate of 156.75 MHz (each chip equals 2 samples)). The chips are filtered to match the 91 MHz LRP transmission mask. The chip sequence This is generated by repeating a 63 tap M-sequence to be specified. The first field 25〇2 is used for AGC and has a length of 128 chips. The second field 2504 is 448 chips long and is used for rx beamforming. 118831.doc -38-200803236 After reading the foregoing description, many variations and modifications of the present invention will be apparent to those skilled in the art. The examples are restrictive. Therefore, the reference to the details of the various embodiments is not intended to limit the scope of the claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of an embodiment of a communication system. 2 is a more detailed block diagram of one embodiment of a communication system. 3 is a block diagram of one embodiment of a peripheral device. 4 is a block diagram of one embodiment of a different channel sharing frequency. Figure 5A is a block diagram of one embodiment of a physical layer for the wireless hD communication system of Figure i. Figure 5B is a table illustrating one example of a block interleaver code. 6 is a block diagram of one embodiment of a High Rate Packet (HRp) parameter for the wireless 11-inch communication system of FIG. 1. Figure 7 is a block diagram of one embodiment of an inner code circuit of the wireless hd communication system of Figure 1. Figure 8 is a table of the code rate of the inner code circuit of Figure 7. Figure 9 is a block diagram of one embodiment of a bit interleaver of the wireless hd communication system of Figure 1. Figure 10 is a table of the specifications of the bit interleaver of Figure 9. Figure 11 is a diagram of an embodiment of a carrier interleaver of the wireless HD communication system of Figure 1. 118831.doc -39- 200803236 Figure 12 is a block diagram of an embodiment of the external FEC of the wireless hd communication vehicle of Figure 1 for the high-fidelity + 1 port, H, and HRP headers. Figure. FIG. 13 is a block diagram of an embodiment of the wireless hd communication of FIG. 1 for a high read, metaphysical, and dead rate packet (HRP) data scrambler. FIG. 14 is a block diagram of an embodiment of a physical layer of the low-reading ~s # rate packet (LRP) transmission of the wireless hd communication Li Tong of FIG. Fig. 15 is a table showing the data rate of the low-receiving rate (LRP) data of the wireless hd communication system of Fig. 1 . Figure 14 is a block diagram of one embodiment of a format for an omnidirectional low rate packet (LRp) data packet. 17 is a block diagram of one embodiment of a long preamble format for an omnidirectional low rate packet (LRp) data packet. Figure 18 is a block diagram of one embodiment of a short preamble format for an omnidirectional low rate packet (LRp) data packet. Figure 19 is a block diagram of one embodiment of a format for beamformed low rate packet (LRp) data packets. Figure 20 is a block diagram of one embodiment of a preamble format for packet-forming low rate packet (LRp) data packets. 21A is a block diagram of one embodiment of a format for a directional low rate packet (LRp) data packet without a valid bearer. Figure (10) is a block diagram of one embodiment of a format for a directional low rate packet (LRp) data packet with payload. Figure 22 is a block diagram of an embodiment of a format using μ to a low rate packet (LRp) preamble. 118831.doc -40. 200803236 Figure 23 is a block diagram of one embodiment of a directional low rate packet (LRp) for antenna direction tracking. 24 is a block diagram of one embodiment of a directional low rate seal & (LRp) post-entry format for transmission antenna direction tracking. 25 is a block diagram of one embodiment of a directional low rate packet (LRp) preamble format for receiving antenna direction tracking. [Main Component Symbol Description] 100 Media Receiver 101 Content 102 Media Receiver Interface 103 Processor 104 Optional Baseband Processing Component 105 Phased Array Antenna 106 Line Communication Channel Interface 107 Wireless Communication Channel/Link 109 Wireless Communication Channel Interface 110 Phased Array Antenna 111 Optional Baseband Processing Component 112 Processor 113 Media Player Interface 114 Media Player 115 Display 122 Control Channel 140 Transmitter 200803236 141 Receiver 201 Digital Signal Processor 202 Digital/Analog Converter 203 Mixer 204 Local oscillator 205〇.n Phase shifter 206〇-n Power amplifier 2〇7〇-n Antenna element 208 Control channel 21 〇〇-n Antenna 211 〇-N Phase shifter 212 IF amplifier 213 Mixer 214 Local Oscillator 215 Analog/Digital Converter 216 Digital Signal Processor 217 Control Channel 220 Return Channel 402 High Rate Channel 404 Low Rate Channel 502 Scrambler 504 Split Block 506 RS Encoder 508 RS Encoder 118831.doc - 42- 200803236

510 External Interleaver 512 External Interleaver 514 Breakdown Circuit 516 Data Multiplexer 518 Bit Interleaver 520 QAM Mapper 522 Carrier Interleaver 524 Pilot/DC/NULL Insert 526 IFFT 602 Table 604 Table 606 Table 700 Circuit Diagram 1202 Tail Section Tuple 1204 Bytes 1206 Bytes 1402 Scrambler 1404 Forward Error Correction 1406 Interleaver 1408 Mapping 1410 Upconversion Conversion 1412 Symbol Shaping 1414 Cycle First Code 1416 IFFT 118831.doc -43- 200803236 1700 Long Full Forwarding 1702 Automatic Gain Control (AGC) and Signal Detection Section 1704 Thick Frequency Offset Estimation (FOE) and Timing Recovery Section 1706 Fine FOE and Timing Recovery Section 1708 RX Beamforming Section 1710 AGC Section 1712 Channel estimation section 1800 short full forward term 1802 AGC sector 1804 AGC sector 1806 signal detection and time synchronization section 1808 RX beamforming section 1810 AGC section 1812 channel estimation section 1900 data packet format 1902 short before Set item 1904 header 1906 payload 2000 LRP beamforming preamble 2002 sequence 2004 frame synchronization and AGC domain 2006 frequency Estimation Domain 2200 Directional LRP Packet Preamble 2202 First Symbol 118831.doc -44- 200803236 2204 Channel Estimation and Frequency Offset Estimation 2400 Tx Antenna Direction Tracking Post 2402 Section/Post Field 2404 Section/Post Item Domain 2406 Zone/Postfield 2500 Τ X Antenna Direction Tracking Precursor 2502 Zone/Preamble Domain 2504 Zone/Preamble Field 118831.doc -45-

Claims (1)

200803236 X. Patent Application Range: 1. A device comprising: a processor; a radio frequency (RF) transmitter coupled to the processor and controlled by the processor to transmit data; and a physical layer circuit, It is coupled to the RF transmitter for encoding and decoding between a digital signal and a modulation analog signal. The physical layer circuit includes a high rate physical layer circuit (HRP) and a low rate physical layer circuit (LRP). The low rate channel generated by the low rate physical layer circuit (LRP) shares the same frequency band as the corresponding high rate channel generated by the high rate physical layer circuit (HRP). 2. The device of claim 1, wherein the high rate physical layer circuit (HRP) will generate a data rate of approximately several billion bits per second, and the low rate physical layer circuit (LRP) will generate approximately several hundred per second The data rate of 10,000 bits. 3. The device of claim 1, wherein the three low rate channels generated by the low rate physical layer circuit (LRP) are disposed in a high rate channel generated by the high rate physical layer circuit (HRP). 4. The device of claim 1, wherein the low rate channels and the high rate channels operate in a time division duplex (TDD) mode. 5. The device of claim 1, wherein the radio frequency (RF) transmitter comprises a crystal to generate intermediate frequency (IF) and radio frequency (RF). 6. The device of claim 5, wherein the crystal generating center is located at four channels between about 57 GHz and about 66 GHz. 118831.doc 200803236 1 The device of claim 6, wherein the four channels comprise 58.608 GHz, 60.720 GHz, 62.832 GHz, and 64.944 GHz 〇8. The device of claim 1, wherein the high rate physical layer circuit (HRP) One or more wireless signals occupying a bandwidth of approximately 1.7 GHz will be generated. 9. The device of claim 1 wherein the high rate physical layer circuit (HRP) is to generate a directional beamforming signal for the RF transmitter. 1) The device of claim 1, wherein the high rate physical layer circuit (HRP) is associated with the transmission of audio, video, data, and control messages. 11. The device of claim i, wherein the low rate physical layer circuit (LRp) is to generate one or more wireless signals 12 occupying a sub-channel having a bandwidth of about 91 MHz, such as the device of claim 1, wherein The low rate physical layer circuit (LRp) will generate a directional signal, an omnidirectional signal or a beamformed signal for one of the RF transmitters. 13. The device of claim 1, wherein the low rate physical layer circuit (LRp) is associated with control messages, beacons, acknowledgments, and low speed data. 14. The device of claim 1, wherein the HRP comprises an outer code circuit, an outer interleaver circuit, an inner code circuit, a bit interleaver circuit, a carrier frequency interleaver circuit, and a data scrambler circuit. . The device of claim 1, wherein the HRP comprises an outer code circuit, an outer interleaver circuit, and an inner code circuit, wherein Μ is greater than 1, and the external interleaver comprises a block interleaver, Guhai District The block interleaver maps successive contigs of the outer code codeword to different inner codes, and maps the same byte in the outer code codeword to the continuation bit of the inner rock horse 118831.doc 200803236. 16. The device of claim 15, wherein the external interleaver circuit is further configured to further divide the input byte into a group of consecutive ones, and input the one of the bytes to the outside A consecutive byte of code and maps the one byte to a different inner code. 17. The device of claim 15 further comprising: a one-bit interleaver circuit that maps bits from the same inner code to an equal number of MSBs and LSBs of the signal cluster. The device of claim 1, wherein the LRP comprises a pilot carrier frequency modulation circuit, a carrier frequency interleaver circuit, a FEC circuit and a data scrambler circuit. 19. The device of claim 1, wherein the LRP is configured to generate an LRP long omnidirectional data packet, an LRP beamform data packet, and an LRP short directional data packet. 20. The device of claim 19, wherein the LRP long omnidirectional data packet comprises an LRP preamble, an LRP header, and an LRP payload. 21. The device of claim 20, wherein the LRP header is encoded by a tail portion elementary convolutional code. 22. The device of claim 20, wherein the LRP preamble comprises a long omnidirectional LRP preamble or a short omnidirectional LRP preamble. 23. The device of claim 22, wherein the long omnidirectional LRP preamble is about 57 microseconds in length. 24. The device of claim 22, wherein the long omnidirectional LRP preamble is configured for beaconing and LRP data packets with blind timing synchronization. The apparatus of claim 22, wherein the long omnidirectional LRP preamble comprises a first AGC and signal detection section, a coarse FOE and timing recovery section, a fine FOE, and a timing recovery zone. And a receiver beamforming section, a second AGC section, and a channel estimation section. 26. The device of claim 22, wherein the short omnidirectional LRP preamble is approximately 43 microseconds in length. 27_ The device of claim 22, wherein the short omnidirectional LRP preamble is configured for use in a contention period and LRP data packet with timing synchronization. 28. The device of claim 22, wherein the short omnidirectional LRP preamble comprises a first AGC segment, a second AGC segment, a signal detection and time synchronization segment, and a receiver beamforming segment a third AGC segment and a channel estimation segment. 29. The apparatus of claim 19, wherein the LRP beamformed data packet comprises an LRP beamforming preamble, an LRP beamforming header, and an LRP beamforming payload. The device of claim 29, wherein the LRP beamforming preamble comprises a frame synchronization and AGC segment, and a channel estimation segment. 31. The device of claim 19, wherein the LRP short-directional data packet comprises an LRP short-directional preamble and an LRP short-directional header. 32. The device of claim 19, wherein the LRP short directional data packet comprises an LRP short directional preamble, an LRP short directional header, and an LRP short directional payload. 33. The device of claim 31, wherein the LRP short-directional preamble comprises an AGC segment and a channel estimation segment. 118831.doc -4-200803236 34. The device of claim 19, wherein the LRP short-directional data packet is configured for use in HRP packet and beamforming LRP packet validation. 35. An apparatus comprising: a processor; a radio frequency (RF) transmitter having a digitally controlled phased array antenna coupled to the processor and controlled by the processor for transmitting data Or content; an interface of one to one wireless communication channel, the interface being coupled to the processor to convey antenna information about the use of the phased array antenna and to convey information to facilitate receiving the data at another location or to play the And the κ layer circuit is spliced to the RF transmitter and the interface to encode and decode between a digital signal and a modulation analog signal, the physical layer circuit comprising a high rate physical layer circuit (HRp) And a low rate physical layer circuit (LRP), wherein the low rate channel generated by the low rate physical layer circuit (LRP) shares the same frequency band as the corresponding high rate channel generated by the high rate physical layer circuit (HRP). 36. The device of claim 35, wherein the high rate physical layer circuit (HRp) is to generate a data rate of about several billion bits per second, and the low rate physical layer circuit (LRP) will generate about hundreds of bits per second. The data rate of 10,000 bits. 37. The device of claim 35, wherein the two low rate channels generated by the low rate physical layer circuit (LRp) are disposed in a high rate channel generated by the high rate physical layer circuit (HRP). 38. The device of claim 35, wherein the high rate physical layer circuit generates 118831.doc 200803236 to generate one or more wireless signals occupying a bandwidth of about 1.7 GHz. 39. The device of claim 35, wherein the high rate physical layer circuit (HRp) is to generate a directional beamforming signal for the RF transmitter. 40. The device of claim 35, wherein the high rate physical layer circuit (hrP) is associated with the transmission of audio 'video, data, and control messages. 41. The device of claim 35, wherein the low rate physical layer circuit (lrP) is to generate one or more wireless signals occupying a subchannel having a bandwidth of about 91 MHz. 42. The device of claim 35, wherein the low rate physical layer circuit (LRp) is to generate a directional signal, an omnidirectional signal or a beam shaping signal for the RF transmitter. 43. The device of claim 35, wherein the low rate physical layer circuit (lrP) is associated with control messages, beacons, acknowledgments, and low speed data. 44. The device of claim 35, wherein the hrP comprises an outer code circuit, an outer interleaver circuit, an inner code circuit, a bit interleaver circuit, a carrier frequency interleaver circuit, and a data scrambler circuit . The device of claim 35, wherein the HRP comprises an outer code circuit, an outer interleaver circuit, an inner code circuit, wherein Μ is greater than 1, and the external interleaver comprises a block interleaver, the & The block parent errorer maps successive contigs of far-out codewords to different innercodes' and maps the same contig in the outercodewords to consecutive contigs of the innercode. 46. The device of claim 45, wherein the external interleaver circuit is further configured to further divide the input byte into a group of consecutive ones of a byte, 118831.doc 200803236 the one byte The consecutive bytes are input to the outer code, and the one byte is mapped to a different inner code. 47. The device of claim 46, further comprising: a one-bit interleaver circuit that maps bits from the same inner code to an equal number of MSBs and LSBs of the signal cluster. 48. The device of claim 35, wherein the LRP comprises a pilot carrier frequency modulation circuit, a carrier frequency interleaver circuit, a FEC circuit, and a data scrambler circuit. 49. The device of claim 35, wherein the LRP is configured to generate an LRP long omnidirectional data packet, an LRP beamform data packet, and an LRP short directional data packet. 50. The device of claim 49, wherein the LRP long omni-directional data packet comprises an LRP preamble, an LRP header, and an LRP payload. 51. The device of claim 50, wherein the LRP header is encoded by a tail portion elementary convolutional code. 52. The device of claim 50, wherein the LRP preamble comprises a long omnidirectional LRP preamble or a short omnidirectional LRP preamble. 53. The device of claim 52, wherein the long omnidirectional LRP preamble is approximately 57 microseconds in length. 54. The device of claim 52, wherein the long omnidirectional LRP preamble is configured for beaconing and LRP data packets with blind timing synchronization. 55. The device of claim 52, wherein the long omnidirectional LRP preamble comprises a first AGC and signal detection section, a coarse FOE and timing recovery section, a fine FOE and a timing recovery section, and a Receiver beamforming section, 118831.doc 200803236 a second AGC section and a channel estimation section. 56. The device of claim 52, wherein the short omnidirectional LRP preamble is about 43 microseconds in length. 57. The device of claim 52, wherein the short omnidirectional LRP preamble is configured for a contention period and LRP data packet with timing synchronization. 58. The device of claim 52, wherein the short omnidirectional LRP preamble comprises a first AGC segment, a second AGC segment, a signal detection and time synchronization segment, and a receiver beamforming segment a third AGC segment and a channel estimation segment. 59. The device of claim 49, wherein the LRP beamformed data packet comprises an LRP beamforming preamble, an LRP beamforming header, and an LRP beamforming payload. 60. The device of claim 59, wherein the LRP beamforming preamble comprises a frame synchronization and an AGC segment and a channel estimation segment. 61. The device of claim 59, wherein the LRP short directed data packet comprises an LRP short directed preamble and an LRP short oriented header. 62. The device of claim 59, wherein the LRP short directional data packet comprises an LRP short directional preamble, an LRP short directional header, and an LRP short directional payload. 63. The device of claim 61, wherein the LRP short-directional preamble comprises an AGC segment and a channel estimation segment. 64. The device of claim 59, wherein the LRP short-directional data packet is configured for confirmation of HRP packets and beamforming LRP packets. 65. A method, comprising: 118831.doc 200803236 generating a modulation analog signal to transmit antenna information and content protection information corresponding to content via a wireless communication channel, wherein generating the modulation analog signal further comprises: using a low A rate entity layer circuit (LRP) generates a low rate channel; a high rate physical layer circuit (HRP) is used to generate a high rate channel, wherein the low rate channels share the same frequency band as a corresponding high rate channel. 66. The method of claim 65, further comprising: configuring the three low rate channels in a high rate channel. 67. The method of claim 65, wherein generating the modulated analog signal further comprises: generating four channels between about 57 GHz and about 66 GHz, wherein the four channels are at 58.608 GHz, 60.720 GHz At 62.832 GHz and 64.944 GHz. 68. A method, comprising: generating a modulation analog signal to transmit content protection information corresponding to content via a wireless communication channel, wherein generating the modulation analog signal further comprises: using a bandwidth occupying approximately 91 MHz A low rate physical layer circuit (LRP) generates a low rate channel, which generates a high rate channel using a high rate physical layer circuit (HRP) occupying a bandwidth of about 1.7 GHz, wherein the low rate channels share the same frequency as a corresponding high rate channel The low frequency channels and the 118831.doc 200803236 high rate cheeks are operated in a frequency band and in a time division duplex (TDD) manner. 69. The method of claim 68, wherein the modulated analog signal is transmittable from four channels centered between about 57 GHz and about 66 GHz. The method of claim 69, wherein the four channels comprise 58.608 GHz, 60.720 GHz, 62.832 GHz, and 64.944 GHz. 71. The method of claim 68, wherein the LRp comprises a pilot carrier frequency modulation circuit, a carrier frequency interleaver circuit, a FEC circuit, and a data scrambler circuit. 72. The method of claim 68, wherein the HRP comprises an outer code circuit, an outer interleaver circuit, an inner code circuit, a bit interleaver circuit, a carrier frequency interleaver circuit, and a data scrambler circuit . 73. A physical layer circuit for providing error protection, comprising: an outer code circuit 'which encodes K bytes into n bytes; an external parental error circuit that forms one row and N columns a byte table; an inner code circuit that operates on a bit, where M is greater than upper, wherein the outer interleaver circuit outputs the bits from the same column to the bits in a sequential order to The internal code circuit. 74. The entity layer circuit of claim 73, wherein the input to the physical layer circuit is mapped to an external interleaver table using the following formula: z = floor{[/ mod (depth^M)]/Μ} k = M floor [l/(depth^M)] + l mod M l = 0,l,."'depthU where / is the index of the input of the external parent error, i is the row index, and k is 118831.doc -10- 200803236 Column index. 75. If the claim is a physical layer, the one or more tail elements are inserted to terminate the inner code by shortening the last outer code. 76. A physical layer circuit for providing error protection, comprising: a hard code circuit that operates on a bit Γ where Μ is greater than 1; a hopper multiplexer that modulates the inner code circuit The output is serialized; a one-bit interleaver circuit; and a signal mapper, wherein the bit interleaver circuit maps bits from the same inner code to an equal number of MSBs and LSBs of a signal cluster. 77. The physical layer circuit of claim 76, wherein the bit interleaver circuit divides the bit stream into a group of 16 bits, and 〇, i, 2, 3, 4, 5, 6, 7, 9' 8, U '10, 13, 12, 15, 14 output bit in the order. 78. The physical layer circuit of claim 76, wherein the bit interleaver circuit divides the bit stream into a group of 32 bits, and 〇, i, 2, 3, 4, 5, 6, 7, 11, 8, 9, 10, 15, 12, 13, 14, 18, 19, 16, 17, 22, 23, 20, 21, 25, 26 '27, 24, 29, 30, 3 1, 2 The order of 8 outputs the bit. 79. A physical layer circuit, comprising: an outer code circuit that encodes K bytes into N bytes; an external interleaver circuit that forms a byte table of jA rows and N columns An internal code circuit that operates on a bit, where μ is greater than 1, 118831.doc -11 - 200803236 where the external interleaver circuit places the bits from the same column in consecutive order Output to the M inner code circuits. - The physical layer circuit of claim 79, wherein the input to the set is mapped to an external interleaver table using the following formula: i-floor{[/ mod (depth^ M)]/M} floor [l/ (depth^M)] + l mod M Di, l, . ", depth This Kl i is the row index, and k is the index column index of / which is the input of the external interleaver. 81. The entity of claim 79, wherein the one or more tail elements are inserted to terminate the inner code by shortening the last outer code. 82. A physical layer circuit comprising: a Neem circuit that operates on a bit, wherein μ is greater than i; a body multiplexer that serializes the output of the intra-code circuit; a one-bit interleaver circuit; and a signal mapper, wherein the bit interleaver circuit maps bits from the same inner code to an equal number of MSBs and LSBs of a signal cluster. 83. For example, in the physical room of the claim 82, the Leica Gan a shell layer circuit, wherein the bit interleaver circuit divides the bit stream into one of 16 bits, and the number is 1, 2, 2 The bits are output in the order of 3, 4, 5, 6, 7, 9, 8, 11, 10, 13, 12, 15, and 14. The bit stream is divided into one group of 32 bits, and is 0, 1, 2, 3, 4, 84. The physical layer circuit of claim 82, wherein the bit interleaver circuit uses the bit & State A 4 H An-118831.doc •12- 200803236 5, 6, 7, 11, 8, 9, 10, 15, 12, 13, 14, 18, 19, 16, 17, 22, 23, 20, 21 Output bits in the order of 25, 26, 27, 24, 29, 30, 3 1, and 2 8 . 85. 86. 87. 88. A device comprising: a processor; a radio frequency (RF) transmitter coupled to the processor and controlled by the processor to transmit content; a physical layer circuit consuming And the RF transmitter and the processor encode and decode between a digital signal and a modulation analog signal, wherein the physical layer circuit includes a low rate physical layer circuit (LRP), and the low rate physical layer circuit can Operating in one of the RFa directional mode, an omni mode, or a beamforming mode, wherein in the omni mode, the physical layer circuit will produce the same k number of copies 'each copy uses a different one Antenna phase field type. The device of claim 85, wherein the signal comprises a 〇 FDm symbol, and N = 8, such as the device of claim 85, wherein in the directional mode, the physical layer circuit will generate the same signal that is replicated N+1 times Each replica uses the same optimized TX antenna phase field type, and the optimized TX antenna phase field pattern is fed back from a return channel receiver to a return channel transmitter. The device of claim 87, wherein the signal comprises a 〇Fdm symbol and N=8. 118831.doc -13-