TWI416525B - Nonvolatile memory apparatus and wear leveling method thereof - Google Patents

Abstract

A nonvolatile memory wear leveling method is provided. First, divide the nonvolatile memory into a data storage area and an empty queue according a plurality of physical block address. Second, compare the historical programming times of the data blocks of the empty queue. Finally, change the physical block address which corresponding to the data block which is most programmed in the empty queue with one of the physical block addresses corresponding to the data blocks of the data storage area.

Description

Non-volatile memory device and its loss averaging method

This invention relates to a non-volatile memory, and more particularly to a non-volatile memory wear leveling access method.

Flash memory is a programmable read only memory (ROM) that allows multiple erases and updates of stored data. This kind of flash memory is widely used in today's electronic products, and is commonly used as a medium for exchanging data between digital electronic products such as memory cards and flash drives.

Generally, flash memory is divided into a plurality of data blocks, and each data block is subdivided into a plurality of data pages of the same capacity. Here, there is a limitation in the flash memory, that is, when updating the data of the flash memory, it is necessary to erase the data block in which the address to be updated is located, and then new The data is written. However, data erasure for each data block in the flash memory has a certain lifetime (the number of erasures). In order to effectively increase the service life of the flash memory, the prior art proposes a so-called wear leveling technique to make the number of erasures per data block relatively average.

Please refer to FIG. 1 to FIG. 3 . FIG. 1 to FIG. 3 are schematic diagrams showing a conventional method for loss average access of a flash memory. In the illustration of FIG. 1, the flash memory 110 is divided into three partitions according to its physical block address PBA0~PBA767, wherein the physical addresses PBA0~PBA255 are the first partition DIV0, and the physical address is PBA256~PBA511 are the second partition DIV1, and the physical addresses PBA512~PBA767 are the third partition DIV2. Then, a corresponding lookup table 120 is established for the first partition DIV0 according to the logical addresses LBA0 L LBA255. Since the first partition DIV0 includes 256 data blocks (each physical block address represents a corresponding data block). The data stored in the corresponding lookup table 120 represents the correspondence between the logical block address and the physical block address. In the illustration of FIG. 1, the logical block address LBA0 corresponds to the physical block address PBA0.

Referring to FIG. 2, the conventional wear averaging technique further includes establishing a blank queue region 130, and the blank queue region 130 records the physical block address of the data block to which the data is not written. In the illustration of FIG. 2, the corresponding lookup table 120 on the left side of the figure is blank (not written), and the blank queue area 130 on the left side of the figure records all the physical block addresses PBA0~PBAN. Is blank. However, after the access command 210 is executed, since the logical block addresses LBA0~LBA2 are to be written, the flash memory provides physical block addresses PBA0, PBA1, and PBA2 according to the records of the blank queue area 130, respectively. The logical block addresses LBA0, LBA1, and LBA2 are used to store data. Therefore, the storage fields corresponding to the logical block addresses LBA0, LBA1, and LBA2 of the corresponding lookup table 120 on the right side of FIG. 2 are respectively stored in the physical block addresses PBA0, PBA1, and PBA2. The blank queue area 130 on the right side of FIG. 2 also removes the records of the original physical block addresses PBA0, PBA1, and PBA2.

Continuing with reference to FIG. 3, access command 310 is executed at this time to update the data for logical block addresses LBA1, LBA2. The physical block addresses PBA3, PBA4 are provided according to the blank queue area 130 (as shown in the left side of FIG. 3) to store the data to be updated to the logical block addresses LBA1, LBA2. And the physical block addresses PBA0, PBA1 are cleared, and the blank queue area 130 is added (as shown on the right side of FIG. 3).

Such a conventional wear averaging technique requires a relatively large memory space because the physical block address corresponding to the lookup table 120 and the flash memory must exist one-to-one, and the blank queue region 130 also requires a large memory space. . In other words, such conventional wear leveling techniques require higher costs.

The invention provides a non-volatile memory device and a loss averaging method thereof, which can effectively average the historical stylization times of each block in the non-volatile memory to prolong the service life of the non-volatile memory.

The invention provides a loss averaging method for non-volatile memory. First, a plurality of physical addresses of the non-volatile memory are segmented into a data storage area and a blank array area. Next, compare the historical stylized times of multiple data blocks in the blank queue area. Then, the data block with the largest number of historical stylizations in the blank queue area is reconfigured in the data storage area, and one of the plurality of data blocks in the data storage area is reconfigured in the blank queue area.

In an embodiment of the invention, when the data storage area needs to be written to an update data, the blank queue area is used to store the updated data.

The invention provides a memory device comprising a non-volatile memory and a controller. The controller is coupled to the non-volatile memory. The controller divides the non-volatile memory into a data storage area and a blank queue area. When the controller performs a wear averaging method, the wear averaging method includes: comparing the historical staging times of the plurality of data blocks in the blank queue area to the data block having the largest number of historical stylizations in the blank queue area The configuration is performed in the data storage area, and one of the plurality of data blocks in the data storage area is configured to be configured in the blank queue area.

Based on the above, the present invention utilizes a data block in the data storage area to exchange with the most historically-staffed data blocks in the blank queue area to extend the service life of the non-volatile memory.

The above described features and advantages of the present invention will be more apparent from the following description.

Referring to FIG. 4, FIG. 4 is a flow chart showing the operation of an embodiment of the loss averaging method for the non-volatile memory of the present invention. Please refer to FIG. 5A to FIG. 5B and FIG. 6 for a schematic diagram of the operation of the embodiment of the loss averaging method of the non-volatile memory of the present invention. Among them, a non-volatile memory (NVM) is, for example, a Mask Read-Only Memory (Mask ROM) or a Programmable Read-Only Memory (PROM). Erasable Programmable Read-Only Memory (EPROM), Electronically Erasable Programmable Read-Only Memory (EEPROM) or flash memory.

In this embodiment, the step of accessing the non-volatile memory includes: first, in step S410, the data storage area and the blank queue area are segmented according to the plurality of physical block addresses of the non-volatile memory. As shown in FIG. 5A, the non-volatile memory 510 has physical block addresses PBA0~PBA4095, and the non-volatile memory 510 is divided into a data storage area 511 and a blank array area 512. The data storage area 511 in this embodiment includes physical block addresses PBA0~PBA3999, and the blank array area 512 includes physical block addresses PBA4000~PBA4095 as shown in FIG. 5B. It should be noted that the division of the data storage area 511 and the blank array area 512 illustrated in FIG. 5A and FIG. 5B is only an example, and does not limit the physical storage area included in the data storage area 511 and the blank array area 512. The scope of the address. In fact, the manner in which the data storage area 511 and the blank array area 512 are divided can be dynamically adjusted.

In addition, a corresponding lookup table may be established according to the plurality of logical block addresses of the non-volatile memory 510, wherein the corresponding lookup table includes a plurality of storage fields for storing the physical block address of the data storage area 511. As shown in FIG. 5A, the corresponding lookup table 520 is established according to LBA0~LBA249 to LBA249 to LBA249 of the logical block address LDIV0 of the non-volatile memory 510. The corresponding lookup table 520 includes storage fields ST0~ST3999, each of which stores each physical block address PBA0~PBA3999 in the data storage area 511. For example, the data stored in the storage field ST0 of the LBA0 corresponding to the logical block address LDIV0 in the lookup table 520 is the physical block address PBA0, indicating the LBA0 and the physical block address of the logical block address LDIV0. PBA0 corresponds. It is further indicated that when the LBA0 of the logical block address LDIV0 of the non-volatile memory 510 is to be accessed, the physical block address PBA0 of the non-volatile memory 510 is actually accessed. Here, the corresponding lookup table 520 is built in a memory device, and the memory device can be dynamic memory or static memory.

Next, referring to FIG. 4, each time an access command for writing an update data to the target logical block address of the non-volatile memory 510 is received, the same target is judged besides executing the access command. Whether the logical block address is accessed repeatedly multiple times. For example, it can be determined whether the number of times the same target logical block address is continuously accessed data reaches a preset value (for example, 50 times). When the same target logical block address is repeatedly accessed for data (that is, when the target logical block address is continuously accessed for data, or when the number of consecutive address/data reordering reaches the preset value) Then, step S420 and step S430 of the wear averaging method illustrated in FIG. 4 are performed once.

Step S420 compares the historical stylized number EC of the plurality of data blocks in the blank queue area 512. The historical stylized number EC of each data block in the non-volatile memory 510 can be recorded in the spare area of the belonging data block, respectively. For example, suppose a certain data block is divided into 256 pages PAG000~PAG255, each of which has 8K bytes of storage space and a 400-byte spare area. The historical stylized number EC of this data block can be stored in the spare area of the first page PAG000 to record the number of times the data block has been programmed. In this embodiment, the backup area of the page PAG000 is taken as an example for recording the history stylization number EC, but is not limited thereto.

The historical stylization number EC indicates the number of times the own data block has been programmed. For example, when erasing a data block corresponding to a physical block address, the historical stylization number EC recorded in the spare area of the data block corresponding to the physical block address is incremented by one. Therefore, the historical stylization number EC can indicate the value of the number of times the associated data block has been erased (ie, the erase count value).

In another embodiment, when the data is written into the data block corresponding to a physical block address, the historical stylized number recorded in the spare area of the data block corresponding to the physical block address is recorded. EC plus 1. Therefore, the historical stylization number EC can also indicate the number of times the data block has been written to the data (ie, the write count value).

After step S420 is completed, it can be known which of the data blocks of the blank queue area 512 has the largest number of historical stylized times EC. When a certain data block of the data storage area 511 needs to be written into the update data, a data block is selected from the blank queue area 512 to store the updated data, and the data block of the data storage area 511 is not directly used. Update the data (including reading old data, erasing and writing back updated data). If the data storage area 511 needs to be resorted, or the physical block address corresponding to the data storage area 511 can no longer be written, the blank storage area 512 is selected for storing the update. The data block of the data will be erased for the next update. Therefore, the data block of the blank queue area 512 will be the most frequently programmed data block in all the data blocks of the non-volatile memory 510.

Therefore, in step S430, one of the physical addresses corresponding to the data block having the largest number of historical stylizations EC in the blank queue area 512 and one of the plurality of physical addresses corresponding to the plurality of data blocks in the data storage area 511 can be Exchange. That is, the data block having the largest number of historical stylizations EC in the blank queue area 512 is relocated to the data storage area 511, and one of the plurality of data blocks of the data storage area 511 is selected and configured. The blank queue area 512. Of course, when the data block of the data storage area 511 is exchanged with the data block of the blank queue area 512, the contents of the two data blocks are also exchanged correspondingly.

In addition, in some applications, when the data block needs to erase the previously stored data due to the need to store new data, the historical stylized number EC of the data block will also be erased, so After the history stylization number EC of the data block is read first, the data block is erased, and then the read history number of programmed ECs is increased by one and then written back to the data block. Since the frequency of the data block in the data storage area 511 is small, and the frequency of the data block in the blank queue area 512 is accessed, the data blocks of the two areas are exchanged to make the non-volatile memory The data blocks of the volume 510 are accessed on average, avoiding a small number of data blocks being repeatedly accessed repeatedly to reduce the useful life of the non-volatile memory 510.

For example, referring to FIG. 6, before receiving the access command, the physical block address of each data block in the data storage area 511 is PBA0~PBA3999, and the physical area of each data block in the blank queue area 512. The block address is PBA4000~PBA4095. After receiving the access command, it is first determined whether the logical block address accessed by the access command is continuously accessed for 50 times. If it is found that the same logical address has been continuously accessed for 50 times, then a loss averaging method 610 is performed (refer to FIG. 4 and related description).

In the process of performing the wear averaging method 610, one data block having the largest history stylization number EC is selected from all the data blocks of the blank queue area 512. In the example shown in FIG. 6, the data block of the physical block address PBA4000 has the largest number of historical programming times EC (100 times), so the data block of the physical block address PBA4000 is selected and configured in the data storage area. 511. In addition, one of the plurality of data blocks of the data storage area 511 is selected to be configured in the blank queue area 512 by the data block (for example, the data block of the physical block address PBA0). In the example shown in FIG. 6, the data block of the physical block address PBA0 has a history stylization number EC of 10 times.

The above method of selecting a data block from the data storage area 511 can take different selection means depending on system design requirements. For example, a data block having the smallest history stylization number EC may be selected in the data storage area 511. However, if the data storage area 511 searches for a data block with a minimum number of historical staging times EC for a large number of data blocks, the search process may take too much time. In some embodiments, the data block configured from the data storage area 511 and disposed in the blank queue area 512 is randomly selected from the plurality of data blocks of the data storage area 511.

In other embodiments, the data block configured from the data storage area 511 and configured in the blank queue area 512 is selected according to the order of the physical block addresses of the plurality of data blocks in the data storage area 511. For example, in FIG. 6 , in the process of performing the wear averaging method 610, the smallest physical block address (for example, PBA0) is selected from the plurality of data blocks of the data storage area 511, and the loss average method is performed next time. In the process, the physical block address is selected from the data storage area 511 to be the second smallest (for example, PBA1), and so on.

After the loss averaging method 610 is completed, the physical block address of the LBA0 corresponding to the logical address LDIV0 is changed from PBA0 to PBA4000. And so on, when the next logical block address is accessed more than 50 times (for example, the logical block address LBA3), the wear averaging method can be performed again as described above, and the blank queue area 512 is used. The data block with the highest number of historical stylizations EC (ie, the data block of the physical block address PBA4001, which is 90 times) and one data block of the data storage area 511 (for example, the data block of the physical block address PBA1) ) to exchange.

From the above description, it is not difficult to find that the access operation of the block in which the physical addresses are distributed on the average of the present embodiment is effective, and the demand for the wear level is achieved.

In the following, an embodiment of the memory control device for accessing non-volatile memory of the present invention is described, and the present invention can be easily understood and implemented by those skilled in the art.

Please refer to FIG. 7. FIG. 7 is a block diagram of a non-volatile memory device according to an embodiment of the present invention. The memory control device 700 is coupled to the non-volatile memory 740 and performs access control on the non-volatile memory 740. The memory control device 700 includes a controller 710, a memory device 720, and a transmission interface 730. The controller 710 is coupled to the non-volatile memory 740. The controller 710 divides the non-volatile memory 740 into the data storage area 511 and the blank queue area 512.

The memory device 720 is coupled to the controller 710. The memory device 720 is configured to establish a corresponding lookup table according to the plurality of logical addresses of the non-volatile memory 740, wherein the corresponding lookup table includes a plurality of storage fields. These storage fields are used to store the physical address of the data storage area.

Further, when the controller 710 receives an access command to write update data for the target logical address, the controller 710 determines whether the target logical address is accessed repeatedly multiple times. When the controller 710 determines that the target logical address is repeatedly accessed for data, the controller 710 performs the above-described wear averaging method. When the controller 710 performs the wear averaging method, the wear averaging method includes: comparing the historical stylized number EC of the plurality of data blocks in the blank queue area 512 to maximize the EC stylized number of times in the blank queue area 512 The data block is configured to be configured in the data storage area 511, and one of the plurality of data blocks in the data storage area 511 is configured to be disposed in the blank queue area 512. . The above-described details of the operation related to the memory control device 700 are believed to have been described in detail in the description of the embodiment of the non-volatile memory access method of the present invention. Therefore, the details of the operation of the memory control device 700 will not be repeatedly described herein.

It should be noted that the memory control device 700 further includes a transmission interface 730. The transmission interface 730 is coupled to the controller 710 for receiving an access command transmitted by the user to the non-volatile memory 740. Of course, the transmission interface 730 can also be used to transfer data stored in or read from the non-volatile memory 740. The function and construction of such a transmission interface are well known to those skilled in the art and will not be described in detail herein.

In summary, the present invention utilizes the record of the number of historical stylizations of each block, and the entity address of the data block in the data storage area and the entity of the data block with the most stylized times in the blank queue area. Address exchange, to effectively distribute the historical stylized times of each block of non-volatile memory, and prolong the service life of non-volatile memory. Also, there is no need for a corresponding lookup table that is equal to the total capacity of the non-volatile memory, and no additional memory is needed to create a blank queue. Effectively achieves a loss-average access operation of non-volatile memory at a minimum circuit area.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

110. . . Flash memory

120, 520. . . Corresponding lookup table

130, 512. . . Blank area

210, 310. . . Access command

510, 740. . . Non-volatile memory

511. . . Data storage area

610. . . Loss averaging method

700. . . Memory control device

710. . . Controller

720. . . Storage device

730. . . Transmission interface

ST0~ST3999. . . Storage field

PBA0~PBA4095, PBAN. . . Physical address

DIV0~DIV2. . . Partition

LBA0~LBA245, LBAN, LBAM, LDIV0, LDIV15. . . Logical address

EC. . . Historical stylization times

S410~S430. . . Steps in the memory loss averaging method

1 to 3 are schematic diagrams showing a conventional method of loss average access of a flash memory.

4 is a flow chart showing the operation of an embodiment of the loss averaging method of the non-volatile memory of the present invention.

5A-5B and FIG. 6 are schematic diagrams showing operations of an embodiment of a loss averaging method for a non-volatile memory according to the present invention.

FIG. 7 is a block diagram of a non-volatile memory control device according to an embodiment of the present invention.

S410~S430. . . Steps in the memory loss averaging method

Claims (25)

A method for loss averaging of a non-volatile memory, comprising: dividing the non-volatile memory into a data storage area and a blank queue area; and comparing historical programming times of the plurality of data blocks in the blank array area And arranging the data block having the largest number of historical stylizations in the blank queue area in the data storage area, and configuring one of the plurality of data blocks in the data storage area to be configured in the blank queue area. The loss averaging method for non-volatile memory according to claim 1, wherein the blank queue area is used to store the update data when the data storage area needs to be written into an update data. The method for loss averaging of non-volatile memory according to claim 2, wherein the step of writing the update data comprises receiving an access command, wherein the access command writes the target data address Updates. The method for averaging non-volatile memory according to claim 2, wherein the step of writing the update data comprises: when writing the update data to a data block corresponding to a physical address, The number of historical stylizations recorded in the spare area of the data block corresponding to the physical address is incremented by one. The loss averaging method for non-volatile memory according to claim 1, wherein when the data block corresponding to a physical block address is erased, the data area corresponding to the physical block address is recorded. The number of historical stylizations in the spare area of the block is increased by one. The method for averaging the non-volatile memory according to claim 1 further includes: performing the wear averaging method when the number of consecutive accesses of the same logical block address reaches a preset value . The method for averaging the non-volatile memory as described in claim 1 further includes: performing the average loss when the number of consecutive data reordering of a logical block address reaches a preset value method. The method for loss averaging of a non-volatile memory according to claim 1, wherein the data block configured from the data storage area to be disposed in the blank queue area is the plurality of data storage areas Randomly selected in the data block. The loss average method for non-volatile memory according to claim 1, wherein the data block configured from the data storage area in the blank queue area is based on the plurality of data storage areas. The order of the physical block addresses of the data block is selected. The method for averaging the non-volatile memory according to claim 1, further comprising: establishing a corresponding lookup table according to a plurality of logical addresses of the non-volatile memory, wherein the corresponding lookup table includes a plurality of A storage field for storing a plurality of physical addresses of the data storage area. The loss average method for non-volatile memory according to claim 10, wherein the corresponding lookup table is established in static memory or dynamic memory. The method for averaging the non-volatile memory as described in claim 1 further includes: dynamically adjusting the memory capacity of the data storage area and the blank queue area. A memory device includes: a non-volatile memory; and a controller coupled to the non-volatile memory, the non-volatile memory is segmented into a data storage area and a blank array area, wherein the control When performing a wear averaging method, the wear averaging method includes comparing a historical stylized number of a plurality of data blocks in the blank queue region to change a data block having the largest number of historical stylization times in the blank queue region. And configured in the data storage area, and one of the plurality of data blocks in the data storage area is configured in the blank queue area. The memory device of claim 13, wherein the blank queue area is used to store the update data when the data storage area needs to be written with an update data. The memory device of claim 14, wherein the controller further receives an access command, wherein the access command writes the update data for a target logical address. The memory device of claim 15, further comprising: a transmission interface coupled to the controller for receiving the access command. The memory device of claim 14, wherein the controller further records the data block corresponding to the physical address when the update data is written to the data block corresponding to the physical address. The number of historical stylizations in the spare area is increased by one. The memory device of claim 13, wherein when a data block corresponding to a physical block address is erased, the controller records the data block corresponding to the physical block address. The number of historical stylizations in the spare area is increased by one. The memory device of claim 13, wherein the controller performs the wear averaging method when the number of consecutive accesses of the same logical block address reaches a preset value. The memory device of claim 13, wherein the controller performs the wear averaging method when the number of consecutive data reordering of a logical block address reaches a preset value. The memory device of claim 13, wherein the controller randomly selects a data block from the plurality of data blocks of the data storage area when the loss averaging method is performed. Configured in this blank queue area. The memory device of claim 13, wherein the controller performs the wear averaging method according to the order of the physical block addresses and the plurality of data blocks in the data storage area. A data block is selected to be configured in the blank queue area. The memory device of claim 13 further comprising: a memory device coupled to the controller for establishing a corresponding lookup table according to a plurality of logical addresses of the non-volatile memory, wherein the corresponding The lookup table includes a plurality of storage fields for storing a plurality of physical addresses of the data storage area. The memory control device of claim 22, wherein the memory device is a static memory or a dynamic memory. The memory device of claim 13, wherein the controller dynamically adjusts the memory capacity of the data storage area and the blank queue area.