TWI416481B - Liquid crysatl display and liquid crystal display panel - Google Patents

Abstract

A liquid crystal display (LCD) and an LCD panel are provided. A bias line channel of the gate driver corresponds to two or two more bias lines in the LCD panel based on the present invention, such that further to effectively design the operation timing of the driving channels and the bias line channels of the gate driver so as to achieve the purpose of reducing the number of channels in the whole gate driver.

Description

Liquid crystal display and liquid crystal display panel

The present invention relates to a flat display technology, and more particularly to a liquid crystal display and a liquid crystal display panel which can reduce the number of channels of a gate driver.

Although the multi-domain vertical alignment type liquid crystal display (hereinafter referred to as MVA LCD) can achieve a wide viewing angle, the problem of color washout phenomenon is also criticized. The so-called color shift refers to when the user views the image displayed by the liquid crystal display at different viewing angles, the user can see images of different color tones, for example, the user displays the display at a more oblique angle. The image will be more white when you see the image.

In order to solve the above problem of color shift, the conventional art mainly divides each pixel unit in the liquid crystal display panel of the MVA LCD into two regions with different light transmittances, and the light transmittance of one region is relatively high. (ie bright area) to display the color of the higher gray level; and the light transmittance of the other area will be lower (ie dark area) to display the lower gray color. Thereby, the color of the upper gray scale is mixed with the color of the higher gray scale and the color of the lower gray scale, so that the user can view the image displayed by the monitor from a front view or a tilt angle. You can see similar color images.

For this reason, under certain design concepts (as shown in FIG. 1A, wherein the labels Vst1 to Vst3 are the bias line channels of the gate driver, and the labels G1 to G3 are the driving channels of the gate driver), if the gate is utilized When the pole driver provides the bias signal required by the pixel unit (including the A+B two regions), a bias line channel of the gate driver (ie, the channel providing the bias signal) only corresponds to the liquid crystal display panel. a bias line. As a result, the number of channels of the gate driver as a whole must be doubled. This design concept not only causes the manufacturing cost of the gate driver to be high, but also increases the power consumption of the gate driver as a whole.

In view of this, the present invention provides a liquid crystal display and a liquid crystal display panel which can reduce the number of channels of a gate driver.

The invention provides a liquid crystal display comprising a liquid crystal display panel, a backlight module, and a gate driver. The liquid crystal display panel has an active device array substrate, and the active device array substrate includes first to fourth scan lines, first to fourth pixels, and first and second bias lines. The first pixel includes a first sub-pixel and a second sub-pixel, wherein the first sub-pixel includes a first active component and a first storage capacitor, and the second sub-pixel includes a second active component and a second storage capacitor .

The second pixel includes a third sub-pixel and a fourth sub-pixel, wherein the third sub-pixel includes a third active component and a third storage capacitor, and the fourth sub-pixel includes a fourth active component and a fourth storage capacitor . The third pixel includes a fifth sub-pixel and a sixth sub-pixel, wherein the fifth sub-pixel includes a fifth active element and a fifth storage capacitor, and the sixth sub-pixel includes a sixth active element and a sixth storage capacitor . The fourth pixel includes a seventh sub-pixel and an eighth sub-pixel, wherein the seventh sub-pixel includes a seventh active element and a seventh storage capacitor, and the eighth sub-pixel includes an eighth active element and an eighth storage capacitor .

The first bias line is coupled to the first, fourth, and fifth storage capacitors, and the second bias line is coupled to the second, third, sixth, and seventh storage capacitors. The backlight module is disposed under the liquid crystal display panel to provide a surface light source required for the liquid crystal display panel. The gate driver includes first to fourth scan pins and first and second bias pins. The scan pins are respectively coupled to the first to fourth scan lines, and the gate driver transmits the first, second, third, and fourth scan pins according to a basic timing, and sequentially outputs the first First, second, third and fourth scan signals. The first and second biasing pins are respectively coupled to the first and second biasing lines.

In an embodiment of the invention, during the Nth picture period (N is a positive integer), when the third scan signal does not fall to the scan low potential, the first bias signal output by the first bias pin The voltage level will remain at the bias high potential, and the voltage level of the second bias signal output by the second bias pin will remain at the bias low potential. In addition, when the third scan signal falls to the scan low potential, the voltage level of the first bias signal outputted by the first bias pin can be converted into a bias low potential, and the second bias pin outputs The voltage level of the second bias signal is then maintained at a low bias voltage. Moreover, after the fourth scan signal falls to the scan low potential, the voltage level of the second bias signal outputted by the second bias pin can be converted into a bias high potential.

In an embodiment of the invention, during the (N+1)th picture, when the third scan signal does not fall to the scan low level, the voltage level of the first bias signal output by the first bias pin is The bias voltage will be maintained at a low potential, and the voltage level of the second bias signal outputted by the second bias pin will be maintained at a bias high potential. In addition, when the third scan signal falls to the scan low potential, the voltage level of the first bias signal outputted by the first bias pin can be converted into a bias high potential, and the second bias pin outputs The voltage level of the second bias signal continues to be maintained at a bias high potential. Moreover, after the fourth scan signal falls to the scan low potential, the voltage level of the second bias signal outputted by the second bias pin can be converted into a bias low potential.

The present invention further provides a liquid crystal display panel in which the above-described gate driver is directly disposed.

Based on the above, the present invention is based on the fact that one bias line channel of the gate driver corresponds to two bias lines (or even more than two bias lines) in the liquid crystal display panel. In this way, after effectively designing the operation timing of the driving channel and the bias line channel of the gate driver, the purpose of reducing the number of channels of the gate driver as a whole can be achieved.

It is to be understood that the foregoing general description and claims

Reference will now be made in detail to the exemplary embodiments embodiments In addition, wherever possible, the same reference numerals in the drawings

FIG. 1B is a schematic diagram of a liquid crystal display (eg, an MVA LCD) according to an embodiment of the invention. 1B, the liquid crystal display 100 includes a liquid crystal display panel 101, a gate driver 103, a source driver 105, a timing controller (T-con) 107, and is disposed under the liquid crystal display panel 101 to provide the liquid crystal display panel 101. The backlight module 109 of the surface light source. The liquid crystal display panel 101 is composed of an active device array substrate 101a, an opposite substrate 101c (color filter substrate) having a common electrode, and a liquid crystal layer 101b disposed between the active device array substrate 101a and the opposite substrate 101c. .

In the present embodiment, the active device array substrate 101a includes at least four scan lines SL1 to SL4, one data line DL, four pixels P1 to P4, and two bias lines BL1 and BL2, but are not limited thereto. The scan lines SL1 SLSL4 are formed on the active device array substrate 101a in a first direction, and the data lines DL are formed on the active device array substrate 101a in a second direction, and the first direction and the second direction are perpendicular.

The pixel P1 is formed at the intersection of the scan line SL1 and the data line DL, and the pixel P1 includes the first sub-pixel P11 and the second sub-pixel P12. In this embodiment, the first sub-pixel P11 includes a first active device T1 (which can be understood as a thin film transistor, a TFT), a first liquid crystal capacitor CLC1, and a first storage capacitor CST1. The first active device T1 has a first 汲/source coupled to the data line DL, and the first active device T1 is coupled to the data line DL. The first active device T1 has a second 汲/source. The pixel electrode is coupled to one end of the first liquid crystal capacitor CLC1 and the first storage capacitor CST1, and the other end of the first liquid crystal capacitor CLC1 is coupled to the common electrode of the opposite substrate 101c. Vcom.

The second sub-pixel P12 includes a second active device T2, a second liquid crystal capacitor CLC2, and a second storage capacitor CST2. The gate of the second active device T2 is coupled to the scan line SL1, the first source/source of the second active device T2 is coupled to the data line DL, and the second source/source of the second active device T2 is coupled. One end of the second liquid crystal capacitor CLC2 and the second storage capacitor CST2, and the other end of the second liquid crystal capacitor CLC2 is coupled to the common electrode Vcom of the opposite substrate 101c.

The pixel P2 is formed at the intersection of the scanning line SL2 and the data line DL, and the pixel P2 includes a third sub-pixel P21 and a fourth sub-pixel P22. The third sub-pixel P21 includes a third active device T3, a third liquid crystal capacitor CLC3, and a third storage capacitor CST3. The gate of the third active device T3 is coupled to the SL2 scan line, the first NMOS/source of the third active device T3 is coupled to the data line DL, and the second NMOS/source of the third active device T3 is coupled. The other end of the third liquid crystal capacitor CLC3 and the third storage capacitor CC3 is coupled to the common electrode Vcom of the counter substrate 101c.

The fourth sub-pixel P22 includes a fourth active device T4, a fourth liquid crystal capacitor CLC4, and a fourth storage capacitor CST4. The gate of the fourth active device T4 is coupled to the scan line SL2, the first source/source of the fourth active device T4 is coupled to the data line DL, and the second source/source of the fourth active device T4 is coupled. One end of the fourth liquid crystal capacitor CLC4 and the fourth storage capacitor CST4, and the other end of the fourth liquid crystal capacitor CLC4 is coupled to the common electrode Vcom of the opposite substrate 101c.

The pixel P3 is formed at the intersection of the scan line SL3 and the DL data line, and the pixel P3 includes a fifth sub-pixel P31 and a sixth sub-pixel P32. The fifth sub-pixel P31 includes a fifth active element T5, a fifth liquid crystal capacitor CLC5, and a fifth storage capacitor CST5. The gate of the fifth active component T5 is coupled to the scan line SL3, the first NMOS/source of the fifth active component T5 is coupled to the data line DL, and the second NMOS/source of the fifth active component T5 is coupled. The other end of the fifth liquid crystal capacitor CLC5 and the fifth storage capacitor CC5 are coupled to the common electrode Vcom of the opposite substrate 101c.

The sixth sub-pixel P32 includes a sixth active element T6, a sixth liquid crystal capacitor CLC6, and a sixth storage capacitor CST6. The gate of the sixth active device T6 is coupled to the scan line SL3, the first source/source of the sixth active device T6 is coupled to the data line DL, and the second source/source of the sixth active device T6 is coupled. The other ends of the sixth liquid crystal capacitor CLC6 and the sixth storage capacitor CST6 are coupled to the common electrode Vcom of the opposite substrate 101c.

The pixel P4 is formed at the intersection of the scanning line SL4 and the data line DL, and the pixel P4 includes a seventh sub-pixel P41 and an eighth sub-pixel P42. The seventh sub-pixel P41 includes a seventh active device T7, a seventh liquid crystal capacitor CLC7, and a seventh storage capacitor CST7. The gate of the seventh active device T7 is coupled to the scan line SL4, the first source/source of the seventh active device T7 is coupled to the data line DL, and the second source/source of the seventh active device T7 is coupled. The other ends of the seventh liquid crystal capacitor CLC7 and the seventh storage capacitor CST7 are coupled to the common electrode Vcom of the counter substrate 101c.

The eighth sub-pixel P42 includes an eighth active element T8, an eighth liquid crystal capacitor CLC8, and an eighth storage capacitor CST8. The gate of the eighth active component T8 is coupled to the scan line SL4, the first NMOS/source of the eighth active component T8 is coupled to the data line DL, and the second NMOS/source of the eighth active component T8 is coupled. One end of the eighth liquid crystal capacitor CLC8 and the eighth storage capacitor CST8, and the other end of the eighth liquid crystal capacitor CLC8 is coupled to the common electrode Vcom of the opposite substrate 101c.

The bias line BL1 is formed on the active device array substrate 101a in a first direction, and is coupled to the other ends of the first storage capacitor CST1, the fourth storage capacitor CST4, and the fifth storage capacitor CST5. The bias line BL2 is also formed on the active device array substrate 101a in a first direction, and is coupled to the other ends of the second storage capacitor CST2, the third storage capacitor CST3, the sixth storage capacitor CST6, and the seventh storage capacitor CST7.

Although the coupling relationship between each of the pixels P1 to P4 and the scanning lines SS1 to SS4, the data line DL, and the bias lines BL1 and BL2 is described by using only four pixels P1 to P4 in a single line of pixels, the field is described in the field. After referring to the above-mentioned teachings, the technician should not be able to self-deduct or introduce the overall appearance of the liquid crystal display 101, and therefore will not be further described herein.

In the present embodiment, the gate driver 103 and the source driver 105 are controlled by the timing controller 107 to drive the pixels P1 to P4 in the liquid crystal display panel 101. The source driver 105 is configured to provide corresponding display data to the pixels P1 P P4, and the gate driver 103 is configured to turn on the active elements of each column of pixels in the liquid crystal display panel 101 and provide each A set of pixels required for the bias signal.

More specifically, the gate driver 103 includes four scan pins G1 G G4 (which can be understood as the drive channels of the gate driver 103) and two bias pins VST1 and VST2 (which can be understood as the bias of the gate driver 103). Line channel). The scan pins G1 G G4 are respectively coupled to the scan lines SL1 - SL4 , and the gate driver 103 sequentially outputs the scan signals according to the basic timing CPV provided by the timing controller 107 through the scan pins G1 G G4 . (scan signal) SS1 to SS4. The bias pins VST1 and VST2 are respectively coupled to the bias lines BL1 and BL2.

FIG. 2 is a timing chart showing the operation of the gate driver 103 according to an embodiment of the present invention. Referring to FIG. 1B and FIG. 2 together, it can be clearly seen from FIG. 2 that during the Nth picture period of the liquid crystal display 100 (the frame period, N is a positive integer), the scan signal SS3 received by the scan line SL3 does not fall. When the scan is low (ie, VGL), the voltage level of the bias signal BV1 output from the bias pin VST1 is maintained at the bias high potential (BVH), and the bias signal BV2 output from the bias pin VST2. The voltage level will remain at the bias low potential (BVL).

In addition, during the Nth picture period of the liquid crystal display 100, when the scan signal SS3 received by the scan line SL3 falls to the scan low potential, the voltage level of the bias signal BV1 outputted by the bias pin VST1 can be converted into The bias voltage is low, and the voltage level of the bias signal BV2 outputted by the bias pin VST2 continues to be maintained at a low bias voltage. Moreover, during the Nth picture of the liquid crystal display 100, when the scan signal SS4 received by the scan line SL4 falls to the scan low level, the voltage level of the bias signal BV2 outputted by the bias pin VST2 can be changed. Is biased high.

On the other hand, during the (N+1)th screen of the liquid crystal display 100, when the scan signal SS3 received by the scan line SL3 does not fall to the scan low potential, the voltage of the bias signal BV1 outputted by the bias pin VST1 The level will remain at the bias low level, and the voltage level of the bias signal BV2 output by the bias pin VST2 will remain at the bias high potential.

In addition, during the (N+1)th screen of the liquid crystal display 100, when the scan signal SS3 received by the scan line SL3 falls to the scan low potential, the voltage level of the bias signal BV1 outputted by the bias pin VST1 can be The voltage is converted to a high bias voltage, and the voltage level of the bias signal BV2 outputted by the bias pin VST2 is maintained at a high bias voltage. Furthermore, during the (N+1)th screen of the liquid crystal display 100, when the scan signal SS4 received by the scan line SL4 falls to the scan low potential, the voltage level of the bias signal BV2 outputted by the bias pin VST2 Can be converted to a low bias voltage.

In other words, during the Nth picture period of the liquid crystal display 100, the voltage level of the bias signal BV1 outputted by the bias pin VST1 is turned from the bias high potential after the scan signal SS3 falls to the scan low potential. Is biased low. In addition, during the (N+1)th screen of the liquid crystal display 100, the voltage level of the bias signal BV1 outputted by the bias pin VST1 is changed from the bias low potential to the equal scan signal SS3 after falling to the scan low potential. The bias voltage is high.

In addition, during the Nth picture period of the liquid crystal display 100, the voltage level of the bias signal BV2 outputted by the bias pin VST2 is after the scan signal SS4 drops to the scan low potential, and is turned from the bias low potential. Is biased high. In addition, during the (N+1)th picture period of the liquid crystal display 100, the voltage level of the bias signal BV2 outputted by the bias pin VST2 is changed from the bias high potential after the equal scan signal SS4 falls to the scan low potential. Is biased low.

Although the above embodiment is described by taking two biasing pins VST1 and VST2 and four scanning signals SS1 to SS4 as an example, it should be easily found by those skilled in the art after referring to the teachings of the above embodiments. During the Nth picture of the liquid crystal display 100, the bias signal BV _2n-1 output by the bias pin VST _2n- 1 (n is a positive integer) of the gate driver 103 is the _isochronous scan signal SS _2n+1 After the low potential of the scan, the high potential is turned to the low bias voltage. In addition, during the (N+1)th screen of the liquid crystal display 100, the bias signal BV _2n-1 output by the bias pin VST _{2n-1 of} the gate driver 103 is equal to the scan signal SS _2n+1 After the low potential, it is turned from a low bias voltage to a high bias voltage.

In addition, during the Nth picture period of the liquid crystal display 100, the bias signal BV _2n outputted by the bias pin VST _{2n of} the gate driver 103 is after the scan signal SS _2n+2 falls to the scan low potential. , from a low bias voltage to a high bias voltage. In addition, during the N+1th picture period of the liquid crystal display 100, the bias signal BV _2n outputted by the bias pin VST _{2n of} the gate driver 103 is after the scan signal SS _2n+2 falls to the scan low level. It is switched from a high bias voltage to a low bias voltage.

Based on the above, as long as one bias line channel of the gate driver 103 corresponds to two or more bias lines in the liquid crystal display panel 101, and through the control channel and bias of the control/design gate driver 103 Other variant embodiments of the operational timing of the line channels to reduce the overall number of channels of the gate driver 103 are also within the scope of the present invention. Therefore, the embodiments of the above embodiments are not intended to limit the scope of the invention as claimed.

In addition, the gate driver 103 of the above embodiment can be fabricated on the Y-side control board to turn on the active elements of each column of pixels in the liquid crystal display panel 101 and to provide each column of pixels. Bias signal. However, in other embodiments of the present invention, the gate driver 103 can also be directly disposed on the liquid crystal display panel 101 through a chip-on-glass (COG) process, and the modified embodiments are also One of the areas to be protected by the present invention.

In addition, the scanning signals generated by the gate driver 103 of the above embodiment are all described by taking the second order as an example. However, in other embodiments of the present invention, the scanning signals generated by the gate driver 103 may be third or fourth. Order, everything depends on the actual design needs to decide.

In summary, the present invention is based on the fact that one bias line channel of the gate driver corresponds to two bias lines (or even more than two bias lines) in the liquid crystal display panel. In this way, after effectively controlling/designing the operation timing of the driving channel and the bias line channel of the gate driver, the purpose of reducing the number of channels of the gate driver as a whole can be achieved.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100. . . LCD Monitor

101. . . LCD panel

101a. . . Active device array substrate

101b. . . Liquid crystal layer

101c. . . Counter substrate

103. . . Gate driver

105. . . Source driver

107. . . Timing controller

109. . . Backlight module

P1 ~ P4. . . Pixel

P11, P12, P21, P22, P31, P32, P41, P42, A, B. . . Subpixel

T1 ~ T8. . . Active component

CLC1~CLC8. . . Liquid crystal capacitor

CST1～CST8. . . Storage capacitor

Vcom. . . Common electrode

SL1～SL4. . . Scanning line

DL. . . Data line

BL1, BL2. . . Bias line

G1～G4. . . Scanning pin (drive channel of the gate driver)

VST1, VST2. . . Bias pin (bias line channel of the gate driver)

BV1, BV2. . . Bias signal

CPV. . . Basic timing

FIG. 1A is a partial schematic view of a conventional multi-domain vertical alignment type liquid crystal display (MVA LCD).

FIG. 1B is a schematic diagram of a liquid crystal display according to an embodiment of the invention.

2 is a timing chart showing the operation of a gate driver according to an embodiment of the invention.

100. . . LCD Monitor

101. . . LCD panel

101a. . . Active device array substrate

101b. . . Liquid crystal layer

101c. . . Counter substrate

103. . . Gate driver

105. . . Source driver

107. . . Timing controller

109. . . Backlight module

P1 ~ P4. . . Pixel

P11, P12, P21, P22, P31, P32, P41, P42. . . Subpixel

T1 ~ T8. . . Active component

CLC1~CLC8. . . Liquid crystal capacitor

CST1～CST8. . . Storage capacitor

Vcom. . . Common electrode

SL1～SL4. . . Scanning line

DL. . . Data line

BL1, BL2. . . Bias line

G1～G4. . . Scanning pin (drive channel of the gate driver)

VST1, VST2. . . Bias pin (bias line channel of the gate driver)

BV1, BV2. . . Bias signal

CPV. . . Basic timing

Claims (5)

A liquid crystal display comprising: a liquid crystal display panel having an active device array substrate, the active device array substrate comprising: a first scan line, a second scan line, a third scan line and a fourth scan line; The first pixel includes: a first sub-pixel including a first active component and a first storage capacitor; and a second sub-pixel including a second active component and a second storage capacitor; The second pixel includes a third sub-pixel including a third active component and a third storage capacitor; and a fourth sub-pixel including a fourth active component and a fourth storage capacitor; a third drawing And comprising: a fifth sub-pixel comprising a fifth active component and a fifth storage capacitor; and a sixth sub-pixel comprising a sixth active component and a sixth storage capacitor; a fourth pixel The method includes a seventh sub-pixel including a seventh active component and a seventh storage capacitor, and an eighth sub-pixel including an eighth active component and an eighth storage capacitor; a first bias line , coupling the first, the fourth, and the a storage capacitor; and a second bias line coupled to the second, the third, the sixth, and the seventh storage capacitor; a backlight module disposed under the liquid crystal display panel for providing the liquid crystal a surface light source required for the display panel; and a gate driver comprising: a first scan pin, a second scan pin, a third scan pin, and a fourth scan pin, each coupled to the The first scan line, the second scan line, the third scan line and the fourth scan line pass through the first, the second, the third, and the fourth scan pin according to a basic timing And outputting a first scan signal, a second scan signal, a third scan signal and a fourth scan signal; and a first bias pin and a second bias pin, respectively coupled to the first a bias line and the second bias line, wherein during the Nth picture, N is a positive integer, and when the third scan signal does not fall to a scan low level, the first bias pin The voltage level of the output first bias signal will be maintained at a bias high potential, and the second bias The voltage level of a second bias signal outputted by the pin is maintained at a low bias voltage. When the third scan signal drops to the scan low potential, the first bias pin outputs the first The voltage level of a bias signal can be converted to the bias low potential, and the voltage level of the second bias signal output by the second bias pin continues to remain at the bias low level, and when the first After the four scan signals fall to the low level of the scan, the voltage level of the second bias signal outputted by the second bias pin can be converted to the bias high potential. The liquid crystal display according to claim 1, wherein during the (N+1)th screen, when the third scan signal does not fall to the scan low level, the first bias pin outputs the The voltage level of the first bias signal is maintained at the bias low potential, and the voltage level of the second bias signal output by the second bias pin is maintained at the bias high potential, and After the third scan signal falls to the low level of the scan, the voltage level of the first bias signal outputted by the first bias pin can be converted to the bias high potential, and the second bias pin The voltage level of the outputted second bias signal continues to be maintained at the bias high level, and when the fourth scan signal falls to the scan low potential, the second bias pin outputs the The voltage level of the second bias signal can be converted to the bias low potential. The liquid crystal display according to claim 1, wherein the liquid crystal display panel further has a pair of a substrate and a liquid crystal layer, wherein the opposite substrate has a common electrode, and the liquid crystal layer is disposed on the active device array Between the substrate and the opposite substrate. A liquid crystal display panel comprising: an active device array substrate, comprising: a first scan line, a second scan line, a third scan line and a fourth scan line; a first pixel comprising: a first The sub-pixel includes a first active component and a first storage capacitor; and a second sub-pixel including a second active component and a second storage capacitor; and a second pixel, including: a third sub-pixel The pixel includes a third active component and a third storage capacitor; and a fourth sub-pixel including a fourth active component and a fourth storage capacitor; and a third pixel comprising: a fifth sub-picture And comprising a fifth active component and a fifth storage capacitor; and a sixth sub-pixel comprising a sixth active component and a sixth storage capacitor; and a fourth pixel comprising: a seventh sub-pixel a seventh active component and a seventh storage capacitor; and an eighth sub-pixel comprising an eighth active component and an eighth storage capacitor; a first bias line coupled to the first, the first And the fifth storage capacitor; and a second bias line, coupled The second, the third, the sixth, and the seventh storage capacitor; the pair of substrates having a common electrode; and a liquid crystal layer disposed between the active device array substrate and the opposite substrate; The gate driver includes: a first scan pin, a second scan pin, a third scan pin, and a fourth scan pin, each coupled to the first scan line and the second scan line And the third scan line and the fourth scan line, and sequentially output a first scan signal, a first through the first, the second, the third, and the fourth scan pin according to a basic timing a second scan signal, a third scan signal, and a fourth scan signal; and a first bias pin and a second bias pin are respectively coupled to the first bias line and the second bias a line, wherein during the Nth picture, N is a positive integer, and when the third scan signal does not fall to a scan low level, the voltage of a first bias signal output by the first bias pin The level will be maintained at a bias high potential, and the second bias pin outputs a second bias The voltage level of the signal will be maintained at a low bias voltage, and after the third scan signal falls to the scan low potential, the voltage level of the first bias signal output by the first bias pin can Converting to the bias low potential, and the voltage level of the second bias signal output by the second bias pin continues to remain at the bias low potential, and when the fourth scan signal falls to the scan low After the potential, the voltage level of the second bias signal output by the second bias pin can be converted to the bias high potential. The liquid crystal display panel of claim 4, wherein during the (N+1)th screen, when the third scan signal does not fall to the scan low potential, the first bias pin outputs The voltage level of the first bias signal is maintained at the bias low potential, and the voltage level of the second bias signal output by the second bias pin is maintained at the bias high potential, and After the third scan signal falls to the scan low potential, the voltage level of the first bias signal outputted by the first bias pin can be converted to the bias high potential, and the second bias pin The voltage level of the second bias signal outputted by the bit continues to be maintained at the bias high level, and after the fourth scan signal falls to the scan low potential, the second bias pin outputs The voltage level of the second bias signal can be converted to the bias low potential.