TWI413052B - Pixel array and driving method thereof and display panel employing the pixel array - Google Patents

Abstract

A pixel array and a driving method thereof are provided. The pixel array includes pixels, scan lines, data lines and a source driving circuit. A pixel of the pixels at column 2m row n is presented to P(2m, n), wherein m and n are integer. A 2nth scan line of the scan lines is presented to G(2n). A mth data line of the data lines is presented to X(m). The scan line G(2n-1) couples to control ends of the pixels P(2m-1, n) and P(2m+2, n). The scan line G(2n) couples to control ends of the pixels P(2m, n) and P(2m+1, n). The data line X(m) couples to data ends of the pixels P(2m-1, n) and P(2m, n). In a tth frame period, the source driving circuit drives pixels P(2m-1, n), P(2m, n), P(2m-1, n+1), P(2m, n+1), P(2m-1, n+2), P(2m, n+2), P(2m-1, n+3) and P(2m, n+3) with order of polarity inversion ''positive, negative, negative, positive, negative, positive, positive, negative'' via the data line X(m).

Description

Pixel array and driving method thereof and display panel using the same

The present invention relates to a pixel array and driving method thereof, and a display panel using the pixel array, and particularly to a dual gate pixel array and driving method thereof, and a display panel using the pixel array .

With the demand for products of large-sized display panels, the structure of liquid crystal display panels has developed a so-called double-gate pixel array. In a dual gate pixel array, two scan lines are arranged in the same pixel column. In the same pixel column, two adjacent pixels share a data line, thereby halving the number of data lines, thereby relatively reducing the cost of the source driver. In the conventional art, two adjacent pixels sharing the same data line are driven by the source driver with the same polarity.

When testing the flickering situation of the liquid crystal display panel, the test method of the double gate and the non-double gate pixel array is not the same, which causes procedural complexity.

Embodiments of the present invention provide a pixel array including a plurality of pixels, a plurality of scan lines, a plurality of data lines, and a source driving circuit. Wherein P(2m,n) is the pixel of the 2nd row and the nth column of these pixels, and the 2nth scan line of these scan lines is represented by G(2n), and these are represented by X(m) The mth data line of the data line, and m and n are integers. The scan line G(2n-1) is coupled to the control end of the pixel P(2m-1, n) and the pixel P(2m+2, n). The scan line G(2n) is coupled to the control end of the pixel P(2m, n) and the pixel P(2m+1, n). The data line X(m) is coupled to the data end of the pixel P (2m-1, n) and the pixel P (2m, n). During the t-th frame period, the source driving circuit drives the pixel P sequentially in the order of "positive polarity, negative polarity, negative polarity, positive polarity, negative polarity, positive polarity, positive polarity, and negative polarity" via the data line X(m). (2m-1,n), P(2m,n), P(2m-1,n+1), P(2m,n+1), P(2m-1,n+2), P(2m,n+2),P(2m -1, n+3) and P(2m, n+3), where t is an integer.

Embodiments of the present invention propose a driving method to drive the above pixel array. The driving method includes driving the pixels sequentially in the "th positive polarity, the negative polarity, the negative polarity, the positive polarity, the negative polarity, the positive polarity, the positive polarity, and the negative polarity" via the data line X(m) during the t-th frame period. P(2m-1,n), P(2m,n), P(2m-1,n+1), P(2m,n+1), P(2m-1,n+2),P(2m , n+2), P(2m-1, n+3) and P(2m, n+3), where t is an integer.

Embodiments of the present invention provide a display panel including a plurality of pixels, a plurality of scan lines, and a plurality of data lines. Wherein P(2m,n) is the pixel of the 2nd row and the nth column of these pixels, and the 2nth scan line of these scan lines is represented by G(2n), and these are represented by X(m) The mth data line of the data line, and m and n are integers. The scan line G(2n-1) is coupled to the control end of the pixel P(2m-1, n) and the pixel P(2m+2, n). The scan line G(2n) is coupled to the control end of the pixel P(2m, n) and the pixel P(2m+1, n). The data line X(m) is coupled to the data end of the pixel P (2m-1, n) and the pixel P (2m, n). The data line X(m+1) is coupled to the data end of the pixel P (2m+1, n) and the pixel P (2m+2, n).

Based on the above, the present invention provides a pixel array and a driving method thereof, which can realize "1+2 line point inversion (1+) in a double gate pixel array without changing the source driving circuit and the gate driving circuit. 2 line dot inversion)" polarity reversal technique. The flicker case of the dual gate pixel array can be tested using the same set of methods as testing a non-double gate pixel array.

The above described features and advantages of the present invention will be more apparent from the following description.

1 is a block diagram showing a system of a flat panel display 100 in accordance with an embodiment of the invention. Referring to FIG. 1, the flat panel display 100 includes a timing controller 110, a source driving circuit 120, a gate driving circuit 130, and a dual gate (Dual Gate). The display panel 140. The double gate display panel 140 is a liquid crystal display panel in this embodiment. The source driver circuit 120 and/or the gate driver circuit 130 may be disposed on a glass substrate of a printed circuit board, a flexible circuit board, or a dual gate display panel 140 in accordance with design requirements and processes. For example, the source driving circuit 120 of the present embodiment is disposed on the glass substrate of the double gate display panel 140 to form a pixel array module.

The pixel array (or double gate display panel 140) further includes a plurality of pixels, a plurality of data lines, and a plurality of scan lines. In FIG. 1, P (2m, n) represents the pixel of the nth row of the second m rows of these pixels, and G(2n) represents the 2nth scan line of these scan lines. , the mth data line of these data lines is represented by X(m), where m and n are integers. It should be noted that the data line X(m) may be any one of the double gate display panels 140, and the scan lines G(2n-1) and the scan lines G(2n) may be in the double gate display panel 140. Any two adjacent scan lines.

The scan line G(2n-1) is coupled to the control end of the pixel P(2m-1, n) and the pixel P(2m+2, n). The scan line G(2n) is coupled to the control end of the pixel P(2m, n) and the pixel P(2m+1, n). The data line X(m) is coupled to the data end of the pixel P (2m-1, n) and the pixel P (2m, n). The data line X(m+1) is coupled to the data end of the pixel P (2m+1, n) and the pixel P (2m+2, n). Other pixels P(2m+3,n)~P(2m+10,n), pixels P(2m-1,n+1)~P(2m+10,n+1), pixel P(2m -1,n+2)~P(2m+10,n+2), pixel P(2m-1,n+3)~P(2m+10,n+3) can refer to the aforementioned pixel P (2m) -1, n) ~ P (2m + 2, n) are respectively coupled to the corresponding scan line and data line, as shown in Figure 1.

FIG. 2A is a timing waveform diagram illustrating a plurality of signals in FIG. 1 during a certain frame period (hereinafter referred to as a t-th frame period F(t)) according to an embodiment of the present invention. FIG. 3A is a timing waveform diagram illustrating a plurality of signals of FIG. 1 during a next frame period (hereinafter referred to as a t+1th frame period F(t+1)) according to an embodiment of the present invention. In FIGS. 2A, 2B, 3A, and 3B, "+" indicates positive polarity, and "-" indicates negative polarity.

Please refer to FIG. 1 and FIG. 2A. The gate driving circuit 130 is controlled by the timing controller 110 to sequentially drive the scanning lines, such as the signal waveforms of the scanning lines G(2n-1) to G(2n+6) as shown in FIG. 2A. The pulses output from the scanning lines G(2n-1) to G(2n+6) can turn on the corresponding pixels in the dual gate display panel 140. The source driving circuit 120 controlled by the timing controller 110 can drive the data lines X(m)~X(m+5) in accordance with the timing of the gate driving circuit 130, so as to write multiple grayscale data into corresponding ones. Picture.

According to the polarity control signal POL outputted by the timing controller 110, the source driving circuit 120 can determine the polarity of the gray scale data on the data lines X(m) to X(m+5). It should be particularly noted that the polarity control signal POL shown in FIG. 2A only draws a complete period, and the undrawn portion can be analogized with reference to the waveform already drawn.

During the t-th frame period F(t), the polarity control signal POL output from the timing controller 110 to the source driving circuit 120 is "1, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, 1 , 0, 1, 1, 0, ...". The source driving circuit 120 determines the polarity of the gray line data of the data line X(m) according to the polarity control signal POL as "+--+-++-+--+-++-..." (where "+" Indicates positive polarity, "-" indicates negative polarity), and determines the polarity of the data line X (m+1) gray scale data as "-++-+--+-++-+--+...". The polarity transformation of the data lines X(m+2) and X(m+4) is the same as the data line X(m), and the polarity transformation of the data lines X(m+3) and X(m+5) is the same as the data line. X(m+1). Therefore, in conjunction with the pulse of the scanning lines G(2n-1) to G(2n+6) shown in FIG. 2A, the source driving circuit 120 can sequentially "positive polarity, negative polarity, and negative polarity" via the data line X(m). , positive polarity, negative polarity, positive polarity, positive polarity, negative polarity" gray scale data are written into pixels P (2m-1, n), P (2m, n), P (2m-1, n + 1) , P(2m, n+1), P(2m-1, n+2), P(2m, n+2), P(2m-1, n+3) and P(2m, n+3), At the same time, the gray scale data of "negative polarity, positive polarity, positive polarity, negative polarity, positive polarity, negative polarity, negative polarity, and positive polarity" are sequentially written into the pixel P (2m+) via the data line X(m+1). 2,n), P(2m+1,n), P(2m+2,n+1), P(2m+1,n+1), P(2m+2,n+2), P(2m+1,n+2), P(2m+2,n+3) and P(2m+1, n+3).

2B is a diagram showing the gray-scale data writing order (driving order) of a plurality of pixels in the double-gate display panel 140 of FIG. 1 during the t-th frame period F(t) according to an embodiment of the present invention. As described above, in conjunction with the timing of the gate driving circuit 130, the source driving circuit 120 can sequentially polarity "+--+-++-+--+-++-.. via the data line X(m). The grayscale data is written into the corresponding pixels, and the polarity "-++-+--+-++-+--+..." is sequentially sequenced via the data line X(m+1). Grayscale data is written into the corresponding pixels. For any of the pixel columns Y(n)~Y(n+7), the polarity of each pixel is "+-+-+-+-..." or "-+- +-+-+..."; for any pixel row, the polarity of each pixel is "+--++--+..." or "-++--++-.. ." Therefore, in the case of not changing the circuit design of the source driving circuit 120 and the gate driving circuit 130, "1+2 line dot inversion" can be realized in the dual gate display panel 140. Polarity reversal technology. Through the present invention, a test method for testing the scintillation of a non-double gate pixel array can be applied to the dual gate pixel array design of the present invention.

Please refer to FIG. 1 and FIG. 3A. In the t+1th frame period F(t+1), the polarity control signal POL output from the timing controller 110 to the source driving circuit 120 is "0, 1, 1, 0, 1, 0, 0, 1, 0, 1 1, 0, 1, 0, 0, 1, ...". The source driving circuit 120 determines the polarity of the gray line data of the data line X(m) according to the polarity control signal POL as "-++-+--+-++-+--+...", and determines the data line. The polarity of the X(m+1) gray scale data is "+--+-++-+--+-++-...". Therefore, in conjunction with the pulse of the scanning lines G(2n-1) to G(2n+6) shown in FIG. 3A, the source driving circuit 120 can sequentially "negative polarity, positive polarity, positive polarity" via the data line X(m). Gray-scale data such as negative polarity, positive polarity, negative polarity, negative polarity, and positive polarity are written into pixels P(2m-1,n), P(2m,n), P(2m-1,n+1, respectively. ), P(2m, n+1), P(2m-1, n+2), P(2m, n+2), P(2m-1, n+3) and P(2m, n+3), and gray scales such as "positive polarity, negative polarity, negative polarity, positive polarity, negative polarity, positive polarity, positive polarity, and negative polarity" are sequentially sequentially supplied through the data line X(m+1). The data is written into pixels P(2m+2,n), P(2m+1,n), P(2m+2,n+1), P(2m+1,n+1),P(2m+ 2, n+2), P(2m+1, n+2), P(2m+2, n+3) and P(2m+1, n+3).

FIG. 3B illustrates a gray scale data writing sequence (driving order) of a plurality of pixels in the double gate display panel 140 of FIG. 1 during the t+1th frame period F(t+1) according to an embodiment of the present invention. As described above, in conjunction with the timing of the gate driving circuit 130, the source driving circuit 120 can sequentially polarity "-++-+--+-++-+--+.. via the data line X(m). .. and other grayscale data are written into the corresponding pixels, and the polarity "+--+-++-+--+-++-..." is sequentially sequenced via the data line X(m+1). Grayscale data is written into the corresponding pixels. For any of the pixel columns Y(n)~Y(n+7), the polarities of the respective pixels are "-+-+-+-+..."; In other words, the polarity of each pixel is "-++--++-..." or "+--++--+...". Therefore, in the t+1th frame period F(t+1), the polarity inversion technique of "1+2 line dot inversion" can be realized in the dual gate display panel 140 in this embodiment.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100‧‧‧ flat panel display

110‧‧‧Sequence Controller

120‧‧‧Source drive circuit

130‧‧ ‧ gate drive circuit

140‧‧‧Double gate display panel

G(2n-1)~G(2n+6)‧‧‧ scan line

P(2m-1,n)~P(2m+10,n), P(2m-1,n+1)~P(2m+10,n+1),P(2m-1,n+2) ~P(2m+10,n+2), P(2m-1,n+3)~P(2m+10,n+3)‧‧‧ pixels

X(m)~X(m+5)‧‧‧ data line

Y(n)~Y(n+7)‧‧‧

1 is a block diagram showing a system of a flat panel display according to an embodiment of the invention.

2A is a timing waveform diagram illustrating a plurality of signals of FIG. 1 during a t-th frame period F(t), in accordance with an embodiment of the present invention.

2B is a diagram showing the driving sequence of a plurality of pixels in the double gate display panel of FIG. 1 during the t-th frame period F(t) according to an embodiment of the present invention.

FIG. 3A is a timing waveform diagram illustrating a plurality of signals of FIG. 1 during a t+1th frame period F(t+1) according to an embodiment of the present invention.

FIG. 3B illustrates a driving sequence of a plurality of pixels in the dual gate display panel of FIG. 1 during a t+1th frame period F(t+1) according to an embodiment of the present invention.

100‧‧‧ flat panel display

110‧‧‧Sequence Controller

120‧‧‧Source drive circuit

130‧‧ ‧ gate drive circuit

140‧‧‧Double gate display panel

G(2n-1)~G(2n+6)‧‧‧ scan line

P(2m-1,n)~P(2m+10,n), P(2m-1,n+1)~P(2m+10,n+1),P(2m-1,n+2) ~P(2m+10,n+2), P(2m-1,n+3)~P(2m+10,n+3)‧‧‧ pixels

X(m)~X(m+5)‧‧‧ data line

Y(n)~Y(n+7)‧‧‧

Claims (12)

A pixel array includes: a plurality of pixels, wherein pixels of the 2nd row and the nth column of the pixels are represented by P(2m, n), and m and n are integers; and a plurality of scan lines, wherein The 2nth scan line of the scan lines is represented as G(2n), and the scan line G(2n-1) is coupled to the pixel P(2m-1, n) and the pixel P(2m+2, n) The control terminal, and the scan line G(2n) is coupled to the control end of the pixel P (2m, n) and the pixel P (2m+1, n); a plurality of data lines, wherein the data lines are m data lines are represented as X(m), and data line X(m) is coupled to the pixel P(2m-1,n) and the data end of the pixel P(2m,n), and the data line X(m+1) is coupled to the pixel P (2m+1, n) and the data end of the pixel P(2m+2, n); and a source driving circuit electrically coupling the data a line in which the source driving circuit has "positive polarity, negative polarity, negative polarity, positive polarity, negative polarity, positive polarity, positive polarity, and negative polarity" via the data line X(m) during a t-frame period. The pixels P(2m-1,n), P(2m,n), P(2m-1,n+1), P(2m,n+1), P(2m-1,n are sequentially driven. +2), P(2m, n+2), P(2m-1, n+3) and P(2m, n+3), where t is an integer. The pixel array according to claim 1, wherein during the t-th frame, the source driving circuit respectively uses "negative polarity, positive polarity, positive polarity, and negative polarity" via the data line X(m+1). The polarity, the positive polarity, the negative polarity, the negative polarity, and the positive polarity drive the pixels P(2m+2,n), P(2m+1,n), P(2m+2,n+1), P(2m+1,n+1), P(2m+2,n+2), P(2m+1,n+2), P(2m+2,n+3) and P(2m+1, n+3). The pixel array of claim 1, wherein during a t+1th frame, the source driving circuit respectively uses a negative electrode via the data line X(m). The polarity, positive polarity, positive polarity, negative polarity, positive polarity, negative polarity, negative polarity, positive polarity" sequentially drive the pixels P(2m-1,n), P(2m,n), P(2m- 1,n+1), P(2m,n+1), P(2m-1,n+2), P(2m,n+2), P(2m-1,n+3) and P(2m , n+3). The pixel array according to claim 3, wherein during the (t+1)th frame, the source driving circuit respectively uses "the positive polarity, the negative polarity, and the negative polarity" via the data line X(m+1). , positive polarity, negative polarity, positive polarity, positive polarity, and negative polarity" sequentially drive the pixels P(2m+2,n), P(2m+1,n), P(2m+2,n+1 ), P(2m+1, n+1), P(2m+2, n+2), P(2m+1, n+2), P(2m+2, n+3) and P(2m+ 1,n+3). The pixel array of claim 1, further comprising: a gate driving circuit electrically coupled to the scan lines, wherein the gate driving circuit sequentially drives the timing of the source driving circuit Some scan lines. A pixel array driving method, wherein the pixel array comprises the pixel array according to claim 1, wherein the driving method comprises: respectively, during a t-frame, via the data line X(m) "Positive polarity, negative polarity, negative polarity, positive polarity, negative polarity, positive polarity, positive polarity, and negative polarity" sequentially drive the pixels P(2m-1,n), P(2m,n), P( 2m-1, n+1), P(2m, n+1), P(2m-1, n+2), P(2m, n+2), P(2m-1, n+3) and P (2m, n+3), where t is an integer. The method for driving a pixel array according to claim 6, further comprising: "negative polarity, positive polarity, positive polarity, and negative polarity" respectively via the data line X(m+1) during the t-th frame period , positive polarity, negative polarity, negative polarity, positive polarity" sequentially drive the pixels P(2m+2,n), P(2m+1,n), P(2m+2,n+1),P (2m+1,n+1), P(2m+2,n+2), P(2m+1,n+2), P(2m+2,n+3) and P(2m+1,n +3). The method for driving a pixel array according to claim 6, further comprising: “negative polarity, positive polarity, positive polarity, and negative polarity” respectively via the data line X(m) during a t+1th frame period , positive polarity, negative polarity, negative polarity, positive polarity" sequentially drive the pixels P(2m-1,n), P(2m,n), P(2m-1,n+1), P(2m , n+1), P (2m-1, n+2), P(2m, n+2), P(2m-1, n+3), and P(2m, n+3). The method for driving a pixel array according to claim 8 , further comprising: “positive polarity, negative polarity, negative polarity, respectively, via the data line X(m+1) during the t+1th frame period; Positive polarity, negative polarity, positive polarity, positive polarity, and negative polarity" sequentially drive the pixels P(2m+2,n), P(2m+1,n), P(2m+2,n+1) , P(2m+1, n+1), P(2m+2, n+2), P(2m+1, n+2), P(2m+2, n+3) and P(2m+1) , n+3). A display panel includes: a plurality of pixels, wherein pixels of the 2nd row and the nth column of the pixels are represented by P(2m, n), and m and n are integers; and a plurality of scan lines, wherein The 2nth scan line of the scan lines is represented as G(2n), and the scan line G(2n-1) is coupled to the pixel P(2m-1, n) and the pixel P(2m+2, a control terminal of n), wherein the scan line G(2n) is coupled to the pixel P(2m, n) and the control end of the pixel P(2m+1, n); a plurality of data lines, wherein The mth data line of some data lines is represented as X(m), and the data line X(m) is coupled to the pixel P(2m-1,n) and the data end of the pixel P(2m,n) And the data line X(m+1) is coupled to the pixel P(2m+1, n) and the data end of the pixel P(2m+2, n); and a source driving circuit, electrical The data lines are coupled to the source driving circuit via the data line X(m) during a t-th frame, respectively. The negative polarity, the negative polarity, the positive polarity, the negative polarity, the positive polarity, the positive polarity, and the negative polarity are sequentially driven to drive the pixels P (2m-1, n), P (2m, n), and P (2m-1, n+1), P(2m, n+1), P(2m-1, n+2), P(2m, n+2), P(2m-1, n+3) and P(2m,n +3), where t is an integer; wherein during the t-th frame, the source driving circuit respectively has "negative polarity, positive polarity, positive polarity, negative polarity, positive polarity," via the data line X(m+1) The negative polarity, the negative polarity, and the positive polarity drive the pixels P(2m+2,n), P(2m+1,n), P(2m+2,n+1), P(2m+1) sequentially. , n+1), P(2m+2, n+2), P(2m+1, n+2), P(2m+2, n+3), and P(2m+1, n+3). The display panel of claim 10, further comprising a source driving circuit electrically coupled to the data lines. The display panel of claim 11, further comprising a gate driving circuit electrically coupled to the scan lines, wherein the gate driving circuit sequentially drives the timings of the source driving circuit Scan line.