TWI413052B - Pixel array and driving method thereof and display panel employing the pixel array - Google Patents

Pixel array and driving method thereof and display panel employing the pixel array Download PDF

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TWI413052B
TWI413052B TW98133554A TW98133554A TWI413052B TW I413052 B TWI413052 B TW I413052B TW 98133554 A TW98133554 A TW 98133554A TW 98133554 A TW98133554 A TW 98133554A TW I413052 B TWI413052 B TW I413052B
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polarity
pixel
negative polarity
positive polarity
pixels
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TW98133554A
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TW201113846A (en
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Jui Feng Ko
Cheng Hsiu Lee
Yi Zhong Sheu
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Innolux Corp
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Abstract

A pixel array and a driving method thereof are provided. The pixel array includes pixels, scan lines, data lines and a source driving circuit. A pixel of the pixels at column 2m row n is presented to P(2m, n), wherein m and n are integer. A 2nth scan line of the scan lines is presented to G(2n). A mth data line of the data lines is presented to X(m). The scan line G(2n-1) couples to control ends of the pixels P(2m-1, n) and P(2m+2, n). The scan line G(2n) couples to control ends of the pixels P(2m, n) and P(2m+1, n). The data line X(m) couples to data ends of the pixels P(2m-1, n) and P(2m, n). In a tth frame period, the source driving circuit drives pixels P(2m-1, n), P(2m, n), P(2m-1, n+1), P(2m, n+1), P(2m-1, n+2), P(2m, n+2), P(2m-1, n+3) and P(2m, n+3) with order of polarity inversion ''positive, negative, negative, positive, negative, positive, positive, negative'' via the data line X(m).

Description

畫素陣列與其驅動方法及採用該畫素陣列之顯示面板Pixel array and driving method thereof and display panel using the same

本發明是有關於一種畫素陣列與其驅動方法及採用該畫素陣列的顯示面板,且特別是有關於一種雙閘極(Dual Gate)畫素陣列與其驅動方法及採用該畫素陣列的顯示面板。The present invention relates to a pixel array and driving method thereof, and a display panel using the pixel array, and particularly to a dual gate pixel array and driving method thereof, and a display panel using the pixel array .

隨著大尺寸顯示面板的產品需求,液晶顯示面板的結構發展出一種被稱為雙閘極畫素陣列(pixel array)。在雙閘極畫素陣列中,同一個畫素列配置兩條掃描線。在同一個畫素列中,兩相鄰的畫素(pixel)共用一條資料線,因而得以使資料線數目減半,所以相對地降低源極驅動器(source driver)的成本。在傳統技術中,共用同一條資料線的兩相鄰畫素是以相同極性而被源極驅動器所驅動著。With the demand for products of large-sized display panels, the structure of liquid crystal display panels has developed a so-called double-gate pixel array. In a dual gate pixel array, two scan lines are arranged in the same pixel column. In the same pixel column, two adjacent pixels share a data line, thereby halving the number of data lines, thereby relatively reducing the cost of the source driver. In the conventional art, two adjacent pixels sharing the same data line are driven by the source driver with the same polarity.

而在測試液晶顯示面板的閃爍情形時,雙閘極與非雙閘極畫素陣列的測試方法並不相同,此會造成程序上的繁雜。When testing the flickering situation of the liquid crystal display panel, the test method of the double gate and the non-double gate pixel array is not the same, which causes procedural complexity.

本發明之實施例提出一種畫素陣列,包括多個畫素、多條掃描線、多條資料線以及一源極驅動電路。其中,以P(2m,n)表示於這些畫素中第2m行第n列的畫素,以G(2n)表示於這些掃描線的第2n條掃描線,以X(m)表示於這些資料線的第m條資料線,而m、n為整數。掃描線G(2n-1)耦接至畫素P(2m-1,n)與畫素P(2m+2,n)的控制端。掃描線G(2n)耦接至畫素P(2m,n)與畫素P(2m+1,n)的控制端。資料線X(m)耦接至畫素P(2m-1,n)與畫素P(2m,n)的資料端。於第t幀期間,源極驅動電路經由資料線X(m)分別以「正極性、負極性、負極性、正極性、負極性、正極性、正極性、負極性」依序驅動畫素P(2m-1,n)、 P(2m,n)、P(2m-1,n+1)、P(2m,n+1)、P(2m-1,n+2)、P(2m,n+2)、P(2m-1,n+3)與P(2m,n+3),其中t為整數。Embodiments of the present invention provide a pixel array including a plurality of pixels, a plurality of scan lines, a plurality of data lines, and a source driving circuit. Wherein P(2m,n) is the pixel of the 2nd row and the nth column of these pixels, and the 2nth scan line of these scan lines is represented by G(2n), and these are represented by X(m) The mth data line of the data line, and m and n are integers. The scan line G(2n-1) is coupled to the control end of the pixel P(2m-1, n) and the pixel P(2m+2, n). The scan line G(2n) is coupled to the control end of the pixel P(2m, n) and the pixel P(2m+1, n). The data line X(m) is coupled to the data end of the pixel P (2m-1, n) and the pixel P (2m, n). During the t-th frame period, the source driving circuit drives the pixel P sequentially in the order of "positive polarity, negative polarity, negative polarity, positive polarity, negative polarity, positive polarity, positive polarity, and negative polarity" via the data line X(m). (2m-1,n), P(2m,n), P(2m-1,n+1), P(2m,n+1), P(2m-1,n+2), P(2m,n+2),P(2m -1, n+3) and P(2m, n+3), where t is an integer.

本發明之實施例提出一種驅動方法,以驅動上述畫素陣列。該驅動方法包括:於第t幀期間,經由資料線X(m)分別以「正極性、負極性、負極性、正極性、負極性、正極性、正極性、負極性」依序驅動畫素P(2m-1,n)、P(2m,n)、P(2m-1,n+1)、P(2m,n+1)、P(2m-1,n+2)、P(2m,n+2)、P(2m-1,n+3)與P(2m,n+3),其中t為整數。Embodiments of the present invention propose a driving method to drive the above pixel array. The driving method includes driving the pixels sequentially in the "th positive polarity, the negative polarity, the negative polarity, the positive polarity, the negative polarity, the positive polarity, the positive polarity, and the negative polarity" via the data line X(m) during the t-th frame period. P(2m-1,n), P(2m,n), P(2m-1,n+1), P(2m,n+1), P(2m-1,n+2),P(2m , n+2), P(2m-1, n+3) and P(2m, n+3), where t is an integer.

本發明之實施例提出一種顯示面板,包括多個畫素、多條掃描線以及多條資料線。其中,以P(2m,n)表示於這些畫素中第2m行第n列的畫素,以G(2n)表示於這些掃描線的第2n條掃描線,以X(m)表示於這些資料線的第m條資料線,而m、n為整數。掃描線G(2n-1)耦接至畫素P(2m-1,n)與畫素P(2m+2,n)的控制端。掃描線G(2n)耦接至畫素P(2m,n)與畫素P(2m+1,n)的控制端。資料線X(m)耦接至畫素P(2m-1,n)與畫素P(2m,n)的資料端。資料線X(m+1)耦接至畫素P(2m+1,n)與畫素P(2m+2,n)的資料端。Embodiments of the present invention provide a display panel including a plurality of pixels, a plurality of scan lines, and a plurality of data lines. Wherein P(2m,n) is the pixel of the 2nd row and the nth column of these pixels, and the 2nth scan line of these scan lines is represented by G(2n), and these are represented by X(m) The mth data line of the data line, and m and n are integers. The scan line G(2n-1) is coupled to the control end of the pixel P(2m-1, n) and the pixel P(2m+2, n). The scan line G(2n) is coupled to the control end of the pixel P(2m, n) and the pixel P(2m+1, n). The data line X(m) is coupled to the data end of the pixel P (2m-1, n) and the pixel P (2m, n). The data line X(m+1) is coupled to the data end of the pixel P (2m+1, n) and the pixel P (2m+2, n).

基於上述,本發明提供一種畫素陣列與其驅動方法,在不更動源極驅動電路與閘極驅動電路的情況下,可以在雙閘極畫素陣列實現「1+2線點反轉(1+2 line dot inversion)」的極性反轉技術。且可使用與測試非雙閘極畫素陣列的同一套方法,測試雙閘極畫素陣列的閃爍情形。Based on the above, the present invention provides a pixel array and a driving method thereof, which can realize "1+2 line point inversion (1+) in a double gate pixel array without changing the source driving circuit and the gate driving circuit. 2 line dot inversion)" polarity reversal technique. The flicker case of the dual gate pixel array can be tested using the same set of methods as testing a non-double gate pixel array.

為讓本發明之上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。The above described features and advantages of the present invention will be more apparent from the following description.

圖1為依照本發明一實施例說明平面顯示器100的系統方塊示意圖。請參照圖1,平面顯示器100包括時序控制器110、源極驅動電路120、閘極驅動電路130以及雙閘極(Dual Gate) 顯示面板140。雙閘極顯示面板140在本實施例中是液晶顯示面板。依照設計需求與製程,源極驅動電路120與\或閘極驅動電路130可能配置在印刷電路板、軟性電路板或雙閘極顯示面板140的玻璃基板上。例如,本實施例之源極驅動電路120係配置在雙閘極顯示面板140的玻璃基板上,而構成一個畫素陣列模組。1 is a block diagram showing a system of a flat panel display 100 in accordance with an embodiment of the invention. Referring to FIG. 1, the flat panel display 100 includes a timing controller 110, a source driving circuit 120, a gate driving circuit 130, and a dual gate (Dual Gate). The display panel 140. The double gate display panel 140 is a liquid crystal display panel in this embodiment. The source driver circuit 120 and/or the gate driver circuit 130 may be disposed on a glass substrate of a printed circuit board, a flexible circuit board, or a dual gate display panel 140 in accordance with design requirements and processes. For example, the source driving circuit 120 of the present embodiment is disposed on the glass substrate of the double gate display panel 140 to form a pixel array module.

此畫素陣列(或雙閘極顯示面板140)尚包括多個畫素、多條資料線以及多條掃描線。於圖1中,以P(2m,n)表示於這些畫素中第2m行(column)第n列(row)的畫素,以G(2n)表示於這些掃描線的第2n條掃描線,以X(m)表示於這些資料線的第m條資料線,其中m、n為整數。值得注意的是,資料線X(m)可以是雙閘極顯示面板140中任何一條資料線,而掃描線G(2n-1)與掃描線G(2n)可以是雙閘極顯示面板140中任何兩條相鄰的掃描線。The pixel array (or double gate display panel 140) further includes a plurality of pixels, a plurality of data lines, and a plurality of scan lines. In FIG. 1, P (2m, n) represents the pixel of the nth row of the second m rows of these pixels, and G(2n) represents the 2nth scan line of these scan lines. , the mth data line of these data lines is represented by X(m), where m and n are integers. It should be noted that the data line X(m) may be any one of the double gate display panels 140, and the scan lines G(2n-1) and the scan lines G(2n) may be in the double gate display panel 140. Any two adjacent scan lines.

掃描線G(2n-1)耦接至畫素P(2m-1,n)與畫素P(2m+2,n)的控制端。掃描線G(2n)耦接至畫素P(2m,n)與畫素P(2m+1,n)的控制端。資料線X(m)耦接至畫素P(2m-1,n)與畫素P(2m,n)的資料端。資料線X(m+1)耦接至畫素P(2m+1,n)與畫素P(2m+2,n)的資料端。其它畫素P(2m+3,n)~P(2m+10,n)、畫素P(2m-1,n+1)~P(2m+10,n+1)、畫素P(2m-1,n+2)~P(2m+10,n+2)、畫素P(2m-1,n+3)~P(2m+10,n+3)可以參照前述畫素P(2m-1,n)~P(2m+2,n)之說明而分別耦接至對應的掃描線與資料線,如圖1所示。The scan line G(2n-1) is coupled to the control end of the pixel P(2m-1, n) and the pixel P(2m+2, n). The scan line G(2n) is coupled to the control end of the pixel P(2m, n) and the pixel P(2m+1, n). The data line X(m) is coupled to the data end of the pixel P (2m-1, n) and the pixel P (2m, n). The data line X(m+1) is coupled to the data end of the pixel P (2m+1, n) and the pixel P (2m+2, n). Other pixels P(2m+3,n)~P(2m+10,n), pixels P(2m-1,n+1)~P(2m+10,n+1), pixel P(2m -1,n+2)~P(2m+10,n+2), pixel P(2m-1,n+3)~P(2m+10,n+3) can refer to the aforementioned pixel P (2m) -1, n) ~ P (2m + 2, n) are respectively coupled to the corresponding scan line and data line, as shown in Figure 1.

圖2A是依照本發明實施例說明圖1中多個信號於某一個幀(frame)期間(以下稱第t幀期間F(t))的時序波形圖。圖3A是依照本發明實施例說明圖1中多個信號於下一個幀期間(以下稱第t+1幀期間F(t+1))的時序波形圖。圖2A、2B、3A、3B中以「+」表示正極性,而以「-」表示負極性。FIG. 2A is a timing waveform diagram illustrating a plurality of signals in FIG. 1 during a certain frame period (hereinafter referred to as a t-th frame period F(t)) according to an embodiment of the present invention. FIG. 3A is a timing waveform diagram illustrating a plurality of signals of FIG. 1 during a next frame period (hereinafter referred to as a t+1th frame period F(t+1)) according to an embodiment of the present invention. In FIGS. 2A, 2B, 3A, and 3B, "+" indicates positive polarity, and "-" indicates negative polarity.

請參照圖1與圖2A。閘極驅動電路130受控於時序控制器110而循序驅動該些掃描線,如圖2A所示掃描線G(2n-1)~G(2n+6)的信號波形。掃描線G(2n-1)~G(2n+6)所輸出的脈衝可以開啟雙閘極顯示面板140中對應的畫素。受控於時序控制器110的源極驅動電路120可以配合閘極驅動電路130之時序而驅動資料線X(m)~X(m+5),以將多個灰階資料分別寫入對應的畫素。Please refer to FIG. 1 and FIG. 2A. The gate driving circuit 130 is controlled by the timing controller 110 to sequentially drive the scanning lines, such as the signal waveforms of the scanning lines G(2n-1) to G(2n+6) as shown in FIG. 2A. The pulses output from the scanning lines G(2n-1) to G(2n+6) can turn on the corresponding pixels in the dual gate display panel 140. The source driving circuit 120 controlled by the timing controller 110 can drive the data lines X(m)~X(m+5) in accordance with the timing of the gate driving circuit 130, so as to write multiple grayscale data into corresponding ones. Picture.

依照時序控制器110所輸出的極性控制信號POL,源極驅動電路120可以決定資料線X(m)~X(m+5)上灰階資料的極性。須特別注意的是,圖2A所示極性控制信號POL僅繪出一個完整的週期,未繪出的部份可以參照已繪出的波形而類推之。According to the polarity control signal POL outputted by the timing controller 110, the source driving circuit 120 can determine the polarity of the gray scale data on the data lines X(m) to X(m+5). It should be particularly noted that the polarity control signal POL shown in FIG. 2A only draws a complete period, and the undrawn portion can be analogized with reference to the waveform already drawn.

於第t幀期間F(t),時序控制器110輸出給源極驅動電路120的極性控制信號POL為「1、0、0、1、0、1、1、0、1、0、0、1、0、1、1、0、...」。源極驅動電路120依據極性控制信號POL而決定資料線X(m)灰階資料的極性為「+--+-++-+--+-++-...」(其中「+」表示正極性,「-」表示負極性),以及決定資料線X(m+1)灰階資料的極性為「-++-+--+-++-+--+...」。資料線X(m+2)與X(m+4)的極性變換相同於資料線X(m),而資料線X(m+3)與X(m+5)的極性變換相同於資料線X(m+1)。因此,配合圖2A所示掃描線G(2n-1)~G(2n+6)之脈衝,源極驅動電路120可以經由資料線X(m)依序將「正極性、負極性、負極性、正極性、負極性、正極性、正極性、負極性」灰階資料分別寫入畫素P(2m-1,n)、P(2m,n)、P(2m-1,n+1)、P(2m,n+1)、P(2m-1,n+2)、P(2m,n+2)、P(2m-1,n+3)與P(2m,n+3),同時經由資料線X(m+1)依序將「負極性、正極性、正極性、負極性、正極性、負極性、負極性、正極性」灰階資料分別寫入畫素P(2m+2,n)、P(2m+1,n)、P(2m+2,n+1)、 P(2m+1,n+1)、P(2m+2,n+2)、P(2m+1,n+2)、P(2m+2,n+3)與P(2m+1,n+3)。During the t-th frame period F(t), the polarity control signal POL output from the timing controller 110 to the source driving circuit 120 is "1, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, 1 , 0, 1, 1, 0, ...". The source driving circuit 120 determines the polarity of the gray line data of the data line X(m) according to the polarity control signal POL as "+--+-++-+--+-++-..." (where "+" Indicates positive polarity, "-" indicates negative polarity), and determines the polarity of the data line X (m+1) gray scale data as "-++-+--+-++-+--+...". The polarity transformation of the data lines X(m+2) and X(m+4) is the same as the data line X(m), and the polarity transformation of the data lines X(m+3) and X(m+5) is the same as the data line. X(m+1). Therefore, in conjunction with the pulse of the scanning lines G(2n-1) to G(2n+6) shown in FIG. 2A, the source driving circuit 120 can sequentially "positive polarity, negative polarity, and negative polarity" via the data line X(m). , positive polarity, negative polarity, positive polarity, positive polarity, negative polarity" gray scale data are written into pixels P (2m-1, n), P (2m, n), P (2m-1, n + 1) , P(2m, n+1), P(2m-1, n+2), P(2m, n+2), P(2m-1, n+3) and P(2m, n+3), At the same time, the gray scale data of "negative polarity, positive polarity, positive polarity, negative polarity, positive polarity, negative polarity, negative polarity, and positive polarity" are sequentially written into the pixel P (2m+) via the data line X(m+1). 2,n), P(2m+1,n), P(2m+2,n+1), P(2m+1,n+1), P(2m+2,n+2), P(2m+1,n+2), P(2m+2,n+3) and P(2m+1, n+3).

圖2B是依照本發明實施例說明於第t幀期間F(t),圖1之雙閘極顯示面板140中多個畫素的灰階資料寫入順序(驅動順序)。如前所述,配合閘極驅動電路130之時序,源極驅動電路120可以經由資料線X(m)依序將極性「+--+-++-+--+-++-...」的灰階資料分別寫入對應的畫素中,同時經由資料線X(m+1)依序將極性「-++-+--+-++-+--+...」灰階資料分別寫入對應的畫素中。就畫素列Y(n)~Y(n+7)中任一畫素列而言,其各個畫素的極性分別為「+-+-+-+-...」或「-+-+-+-+...」;就任一畫素行而言,其各個畫素的極性分別為「+--++--+...」或「-++--++-...」。因此,在不更動源極驅動電路120與閘極驅動電路130的電路設計之情況下,可以在雙閘極顯示面板140實現「1+2線點反轉(1+2 line dot inversion)」的極性反轉技術。經由本發明,可將測試非雙閘極畫素陣列閃爍情形的測試方法,應用至本發明的雙閘極畫素陣列設計。2B is a diagram showing the gray-scale data writing order (driving order) of a plurality of pixels in the double-gate display panel 140 of FIG. 1 during the t-th frame period F(t) according to an embodiment of the present invention. As described above, in conjunction with the timing of the gate driving circuit 130, the source driving circuit 120 can sequentially polarity "+--+-++-+--+-++-.. via the data line X(m). The grayscale data is written into the corresponding pixels, and the polarity "-++-+--+-++-+--+..." is sequentially sequenced via the data line X(m+1). Grayscale data is written into the corresponding pixels. For any of the pixel columns Y(n)~Y(n+7), the polarity of each pixel is "+-+-+-+-..." or "-+- +-+-+..."; for any pixel row, the polarity of each pixel is "+--++--+..." or "-++--++-.. ." Therefore, in the case of not changing the circuit design of the source driving circuit 120 and the gate driving circuit 130, "1+2 line dot inversion" can be realized in the dual gate display panel 140. Polarity reversal technology. Through the present invention, a test method for testing the scintillation of a non-double gate pixel array can be applied to the dual gate pixel array design of the present invention.

請參照圖1與圖3A。於第t+1幀期間F(t+1),時序控制器110輸出給源極驅動電路120的極性控制信號POL為「0、1、1、0、1、0、0、1、0、1、1、0、1、0、0、1、...」。源極驅動電路120依據極性控制信號POL而決定資料線X(m)灰階資料的極性為「-++-+--+-++-+--+...」,以及決定資料線X(m+1)灰階資料的極性為「+--+-++-+--+-++-...」。因此,配合圖3A所示掃描線G(2n-1)~G(2n+6)之脈衝,源極驅動電路120可以經由資料線X(m)依序將「負極性、正極性、正極性、負極性、正極性、負極性、負極性、正極性」等灰階資料分別寫入畫素P(2m-1,n)、P(2m,n)、P(2m-1,n+1)、P(2m,n+1)、P(2m-1,n+2)、P(2m,n+2)、P(2m-1,n+3)與 P(2m,n+3),同時經由資料線X(m+1)依序將「正極性、負極性、負極性、正極性、負極性、正極性、正極性、負極性」等灰階資料分別寫入畫素P(2m+2,n)、P(2m+1,n)、P(2m+2,n+1)、P(2m+1,n+1)、P(2m+2,n+2)、P(2m+1,n+2)、P(2m+2,n+3)與P(2m+1,n+3)。Please refer to FIG. 1 and FIG. 3A. In the t+1th frame period F(t+1), the polarity control signal POL output from the timing controller 110 to the source driving circuit 120 is "0, 1, 1, 0, 1, 0, 0, 1, 0, 1 1, 0, 1, 0, 0, 1, ...". The source driving circuit 120 determines the polarity of the gray line data of the data line X(m) according to the polarity control signal POL as "-++-+--+-++-+--+...", and determines the data line. The polarity of the X(m+1) gray scale data is "+--+-++-+--+-++-...". Therefore, in conjunction with the pulse of the scanning lines G(2n-1) to G(2n+6) shown in FIG. 3A, the source driving circuit 120 can sequentially "negative polarity, positive polarity, positive polarity" via the data line X(m). Gray-scale data such as negative polarity, positive polarity, negative polarity, negative polarity, and positive polarity are written into pixels P(2m-1,n), P(2m,n), P(2m-1,n+1, respectively. ), P(2m, n+1), P(2m-1, n+2), P(2m, n+2), P(2m-1, n+3) and P(2m, n+3), and gray scales such as "positive polarity, negative polarity, negative polarity, positive polarity, negative polarity, positive polarity, positive polarity, and negative polarity" are sequentially sequentially supplied through the data line X(m+1). The data is written into pixels P(2m+2,n), P(2m+1,n), P(2m+2,n+1), P(2m+1,n+1),P(2m+ 2, n+2), P(2m+1, n+2), P(2m+2, n+3) and P(2m+1, n+3).

圖3B是依照本發明實施例說明於第t+1幀期間F(t+1),圖1之雙閘極顯示面板140中多個畫素的灰階資料寫入順序(驅動順序)。如前所述,配合閘極驅動電路130之時序,源極驅動電路120可以經由資料線X(m)依序將極性「-++-+--+-++-+--+...」等灰階資料分別寫入對應的畫素中,同時經由資料線X(m+1)依序將極性「+--+-++-+--+-++-...」等灰階資料分別寫入對應的畫素中。就畫素列Y(n)~Y(n+7)中任一畫素列而言,其各個畫素的極性分別為「-+-+-+-+...」;就任一畫素行而言,其各個畫素的極性分別為「-++--++-...」或「+--++--+...」。因此,於第t+1幀期間F(t+1),本實施例依然可以在雙閘極顯示面板140實現「1+2線點反轉」的極性反轉技術。FIG. 3B illustrates a gray scale data writing sequence (driving order) of a plurality of pixels in the double gate display panel 140 of FIG. 1 during the t+1th frame period F(t+1) according to an embodiment of the present invention. As described above, in conjunction with the timing of the gate driving circuit 130, the source driving circuit 120 can sequentially polarity "-++-+--+-++-+--+.. via the data line X(m). .. and other grayscale data are written into the corresponding pixels, and the polarity "+--+-++-+--+-++-..." is sequentially sequenced via the data line X(m+1). Grayscale data is written into the corresponding pixels. For any of the pixel columns Y(n)~Y(n+7), the polarities of the respective pixels are "-+-+-+-+..."; In other words, the polarity of each pixel is "-++--++-..." or "+--++--+...". Therefore, in the t+1th frame period F(t+1), the polarity inversion technique of "1+2 line dot inversion" can be realized in the dual gate display panel 140 in this embodiment.

雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作些許之更動與潤飾,故本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100‧‧‧平面顯示器100‧‧‧ flat panel display

110‧‧‧時序控制器110‧‧‧Sequence Controller

120‧‧‧源極驅動電路120‧‧‧Source drive circuit

130‧‧‧閘極驅動電路130‧‧ ‧ gate drive circuit

140‧‧‧雙閘極顯示面板140‧‧‧Double gate display panel

G(2n-1)~G(2n+6)‧‧‧掃描線G(2n-1)~G(2n+6)‧‧‧ scan line

P(2m-1,n)~P(2m+10,n)、P(2m-1,n+1)~P(2m+10,n+1)、P(2m-1,n+2)~P(2m+10,n+2)、P(2m-1,n+3)~P(2m+10,n+3)‧‧‧畫素P(2m-1,n)~P(2m+10,n), P(2m-1,n+1)~P(2m+10,n+1),P(2m-1,n+2) ~P(2m+10,n+2), P(2m-1,n+3)~P(2m+10,n+3)‧‧‧ pixels

X(m)~X(m+5)‧‧‧資料線X(m)~X(m+5)‧‧‧ data line

Y(n)~Y(n+7)‧‧‧畫素列Y(n)~Y(n+7)‧‧‧

圖1為依照本發明一實施例說明平面顯示器的系統方塊示意圖。1 is a block diagram showing a system of a flat panel display according to an embodiment of the invention.

圖2A是依照本發明實施例說明圖1中多個信號於第t幀期間F(t)的時序波形圖。2A is a timing waveform diagram illustrating a plurality of signals of FIG. 1 during a t-th frame period F(t), in accordance with an embodiment of the present invention.

圖2B是依照本發明實施例說明於第t幀期間F(t),圖1之雙閘極顯示面板中多個畫素的驅動順序。2B is a diagram showing the driving sequence of a plurality of pixels in the double gate display panel of FIG. 1 during the t-th frame period F(t) according to an embodiment of the present invention.

圖3A是依照本發明實施例說明圖1中多個信號於第t+1幀期間F(t+1)的時序波形圖。FIG. 3A is a timing waveform diagram illustrating a plurality of signals of FIG. 1 during a t+1th frame period F(t+1) according to an embodiment of the present invention.

圖3B是依照本發明實施例說明於第t+1幀期間F(t+1),圖1之雙閘極顯示面板中多個畫素的驅動順序。FIG. 3B illustrates a driving sequence of a plurality of pixels in the dual gate display panel of FIG. 1 during a t+1th frame period F(t+1) according to an embodiment of the present invention.

100‧‧‧平面顯示器100‧‧‧ flat panel display

110‧‧‧時序控制器110‧‧‧Sequence Controller

120‧‧‧源極驅動電路120‧‧‧Source drive circuit

130‧‧‧閘極驅動電路130‧‧ ‧ gate drive circuit

140‧‧‧雙閘極顯示面板140‧‧‧Double gate display panel

G(2n-1)~G(2n+6)‧‧‧掃描線G(2n-1)~G(2n+6)‧‧‧ scan line

P(2m-1,n)~P(2m+10,n)、P(2m-1,n+1)~P(2m+10,n+1)、P(2m-1,n+2)~P(2m+10,n+2)、P(2m-1,n+3)~P(2m+10,n+3)‧‧‧畫素P(2m-1,n)~P(2m+10,n), P(2m-1,n+1)~P(2m+10,n+1),P(2m-1,n+2) ~P(2m+10,n+2), P(2m-1,n+3)~P(2m+10,n+3)‧‧‧ pixels

X(m)~X(m+5)‧‧‧資料線X(m)~X(m+5)‧‧‧ data line

Y(n)~Y(n+7)‧‧‧畫素列Y(n)~Y(n+7)‧‧‧

Claims (12)

一種畫素陣列,包括:多個畫素,其中於該些畫素中第2m行第n列的畫素表示為P(2m,n),而m、n為整數;多條掃描線,其中於該些掃描線的第2n條掃描線表示為G(2n),掃描線G(2n-1)耦接至畫素P(2m-1,n)與畫素P(2m+2,n)的控制端,而掃描線G(2n)耦接至畫素P(2m,n)與畫素P(2m+1,n)的控制端;多條資料線,其中於該些資料線的第m條資料線表示為X(m),而資料線X(m)耦接至該畫素P(2m-1,n)與該畫素P(2m,n)的資料端,而該資料線X(m+1)耦接至該畫素P(2m+1,n)與該畫素P(2m+2,n)的資料端;以及一源極驅動電路,電性耦接該些資料線,其中於一第t幀期間,該源極驅動電路經由該資料線X(m)分別以「正極性、負極性、負極性、正極性、負極性、正極性、正極性、負極性」依序驅動該些畫素P(2m-1,n)、P(2m,n)、P(2m-1,n+1)、P(2m,n+1)、P(2m-1,n+2)、P(2m,n+2)、P(2m-1,n+3)與P(2m,n+3),其中t為整數。 A pixel array includes: a plurality of pixels, wherein pixels of the 2nd row and the nth column of the pixels are represented by P(2m, n), and m and n are integers; and a plurality of scan lines, wherein The 2nth scan line of the scan lines is represented as G(2n), and the scan line G(2n-1) is coupled to the pixel P(2m-1, n) and the pixel P(2m+2, n) The control terminal, and the scan line G(2n) is coupled to the control end of the pixel P (2m, n) and the pixel P (2m+1, n); a plurality of data lines, wherein the data lines are m data lines are represented as X(m), and data line X(m) is coupled to the pixel P(2m-1,n) and the data end of the pixel P(2m,n), and the data line X(m+1) is coupled to the pixel P (2m+1, n) and the data end of the pixel P(2m+2, n); and a source driving circuit electrically coupling the data a line in which the source driving circuit has "positive polarity, negative polarity, negative polarity, positive polarity, negative polarity, positive polarity, positive polarity, and negative polarity" via the data line X(m) during a t-frame period. The pixels P(2m-1,n), P(2m,n), P(2m-1,n+1), P(2m,n+1), P(2m-1,n are sequentially driven. +2), P(2m, n+2), P(2m-1, n+3) and P(2m, n+3), where t is an integer. 如申請專利範圍第1項所述之畫素陣列,其中於該第t幀期間,該源極驅動電路經由該資料線X(m+1)分別以「負極性、正極性、正極性、負極性、正極性、負極性、負極性、正極性」依序驅動該些畫素P(2m+2,n)、P(2m+1,n)、P(2m+2,n+1)、P(2m+1,n+1)、P(2m+2,n+2)、P(2m+1,n+2)、P(2m+2,n+3)與P(2m+1,n+3)。 The pixel array according to claim 1, wherein during the t-th frame, the source driving circuit respectively uses "negative polarity, positive polarity, positive polarity, and negative polarity" via the data line X(m+1). The polarity, the positive polarity, the negative polarity, the negative polarity, and the positive polarity drive the pixels P(2m+2,n), P(2m+1,n), P(2m+2,n+1), P(2m+1,n+1), P(2m+2,n+2), P(2m+1,n+2), P(2m+2,n+3) and P(2m+1, n+3). 如申請專利範圍第1項所述之畫素陣列,其中於一第t+1幀期間,該源極驅動電路經由該資料線X(m)分別以「負極 性、正極性、正極性、負極性、正極性、負極性、負極性、正極性」依序驅動該些畫素P(2m-1,n)、P(2m,n)、P(2m-1,n+1)、P(2m,n+1)、P(2m-1,n+2)、P(2m,n+2)、P(2m-1,n+3)與P(2m,n+3)。 The pixel array of claim 1, wherein during a t+1th frame, the source driving circuit respectively uses a negative electrode via the data line X(m). The polarity, positive polarity, positive polarity, negative polarity, positive polarity, negative polarity, negative polarity, positive polarity" sequentially drive the pixels P(2m-1,n), P(2m,n), P(2m- 1,n+1), P(2m,n+1), P(2m-1,n+2), P(2m,n+2), P(2m-1,n+3) and P(2m , n+3). 如申請專利範圍第3項所述之畫素陣列,其中於該第t+1幀期間,該源極驅動電路經由該資料線X(m+1)分別以「正極性、負極性、負極性、正極性、負極性、正極性、正極性、負極性」依序驅動該些畫素P(2m+2,n)、P(2m+1,n)、P(2m+2,n+1)、P(2m+1,n+1)、P(2m+2,n+2)、P(2m+1,n+2)、P(2m+2,n+3)與P(2m+1,n+3)。 The pixel array according to claim 3, wherein during the (t+1)th frame, the source driving circuit respectively uses "the positive polarity, the negative polarity, and the negative polarity" via the data line X(m+1). , positive polarity, negative polarity, positive polarity, positive polarity, and negative polarity" sequentially drive the pixels P(2m+2,n), P(2m+1,n), P(2m+2,n+1 ), P(2m+1, n+1), P(2m+2, n+2), P(2m+1, n+2), P(2m+2, n+3) and P(2m+ 1,n+3). 如申請專利範圍第1項所述之畫素陣列,更包括:一閘極驅動電路,電性耦接該些掃描線,其中該閘極驅動電路配合該源極驅動電路之時序而循序驅動該些掃描線。 The pixel array of claim 1, further comprising: a gate driving circuit electrically coupled to the scan lines, wherein the gate driving circuit sequentially drives the timing of the source driving circuit Some scan lines. 一種畫素陣列的驅動方法,其中該畫素陣列包含如申請專利範圍第1項所述之畫素陣列,該驅動方法包括:於一第t幀期間,經由該資料線X(m)分別以「正極性、負極性、負極性、正極性、負極性、正極性、正極性、負極性」依序驅動該些畫素P(2m-1,n)、P(2m,n)、P(2m-1,n+1)、P(2m,n+1)、P(2m-1,n+2)、P(2m,n+2)、P(2m-1,n+3)與P(2m,n+3),其中t為整數。 A pixel array driving method, wherein the pixel array comprises the pixel array according to claim 1, wherein the driving method comprises: respectively, during a t-frame, via the data line X(m) "Positive polarity, negative polarity, negative polarity, positive polarity, negative polarity, positive polarity, positive polarity, and negative polarity" sequentially drive the pixels P(2m-1,n), P(2m,n), P( 2m-1, n+1), P(2m, n+1), P(2m-1, n+2), P(2m, n+2), P(2m-1, n+3) and P (2m, n+3), where t is an integer. 如申請專利範圍第6項所述畫素陣列的驅動方法,更包括:於該第t幀期間,經由該資料線X(m+1)分別以「負極性、正極性、正極性、負極性、正極性、負極性、負極性、正極性」依序驅動該些畫素P(2m+2,n)、P(2m+1,n)、P(2m+2,n+1)、P(2m+1,n+1)、P(2m+2,n+2)、P(2m+1,n+2)、P(2m+2,n+3)與P(2m+1,n+3)。 The method for driving a pixel array according to claim 6, further comprising: "negative polarity, positive polarity, positive polarity, and negative polarity" respectively via the data line X(m+1) during the t-th frame period , positive polarity, negative polarity, negative polarity, positive polarity" sequentially drive the pixels P(2m+2,n), P(2m+1,n), P(2m+2,n+1),P (2m+1,n+1), P(2m+2,n+2), P(2m+1,n+2), P(2m+2,n+3) and P(2m+1,n +3). 如申請專利範圍第6項所述畫素陣列的驅動方法,更包括:於一第t+1幀期間,經由該資料線X(m)分別以「負極性、正極性、正極性、負極性、正極性、負極性、負極性、正極性」依序驅動該些畫素P(2m-1,n)、P(2m,n)、P(2m-1,n+1)、P(2m,n+1)、P(2m-1,n+2)、P(2m,n+2)、P(2m-1,n+3)與P(2m,n+3)。 The method for driving a pixel array according to claim 6, further comprising: “negative polarity, positive polarity, positive polarity, and negative polarity” respectively via the data line X(m) during a t+1th frame period , positive polarity, negative polarity, negative polarity, positive polarity" sequentially drive the pixels P(2m-1,n), P(2m,n), P(2m-1,n+1), P(2m , n+1), P (2m-1, n+2), P(2m, n+2), P(2m-1, n+3), and P(2m, n+3). 如申請專利範圍第8項所述畫素陣列的驅動方法,更包括:於該第t+1幀期間,經由該資料線X(m+1)分別以「正極性、負極性、負極性、正極性、負極性、正極性、正極性、負極性」依序驅動該些畫素P(2m+2,n)、P(2m+1,n)、P(2m+2,n+1)、P(2m+1,n+1)、P(2m+2,n+2)、P(2m+1,n+2)、P(2m+2,n+3)與P(2m+1,n+3)。 The method for driving a pixel array according to claim 8 , further comprising: “positive polarity, negative polarity, negative polarity, respectively, via the data line X(m+1) during the t+1th frame period; Positive polarity, negative polarity, positive polarity, positive polarity, and negative polarity" sequentially drive the pixels P(2m+2,n), P(2m+1,n), P(2m+2,n+1) , P(2m+1, n+1), P(2m+2, n+2), P(2m+1, n+2), P(2m+2, n+3) and P(2m+1) , n+3). 一種顯示面板,包括:多個畫素,其中於該些畫素中第2m行第n列的畫素表示為P(2m,n),而m、n為整數;多條掃描線,其中於該些掃描線的第2n條掃描線表示為G(2n),該掃描線G(2n-1)耦接至該畫素P(2m-1,n)與該畫素P(2m+2,n)的控制端,而該掃描線G(2n)耦接至該畫素P(2m,n)與該畫素P(2m+1,n)的控制端;多條資料線,其中於該些資料線的第m條資料線表示為X(m),該資料線X(m)耦接至該畫素P(2m-1,n)與該畫素P(2m,n)的資料端,而該資料線X(m+1)耦接至該畫素P(2m+1,n)與該畫素P(2m+2,n)的資料端;以及一源極驅動電路,電性耦接該些資料線,其中於一第t幀期間,該源極驅動電路經由該資料線X(m)分別以「正極性、 負極性、負極性、正極性、負極性、正極性、正極性、負極性」依序驅動該些畫素P(2m-1,n)、P(2m,n)、P(2m-1,n+1)、P(2m,n+1)、P(2m-1,n+2)、P(2m,n+2)、P(2m-1,n+3)與P(2m,n+3),其中t為整數;其中於該第t幀期間,該源極驅動電路經由該資料線X(m+1)分別以「負極性、正極性、正極性、負極性、正極性、負極性、負極性、正極性」依序驅動該些畫素P(2m+2,n)、P(2m+1,n)、P(2m+2,n+1)、P(2m+1,n+1)、P(2m+2,n+2)、P(2m+1,n+2)、P(2m+2,n+3)與P(2m+1,n+3)。 A display panel includes: a plurality of pixels, wherein pixels of the 2nd row and the nth column of the pixels are represented by P(2m, n), and m and n are integers; and a plurality of scan lines, wherein The 2nth scan line of the scan lines is represented as G(2n), and the scan line G(2n-1) is coupled to the pixel P(2m-1, n) and the pixel P(2m+2, a control terminal of n), wherein the scan line G(2n) is coupled to the pixel P(2m, n) and the control end of the pixel P(2m+1, n); a plurality of data lines, wherein The mth data line of some data lines is represented as X(m), and the data line X(m) is coupled to the pixel P(2m-1,n) and the data end of the pixel P(2m,n) And the data line X(m+1) is coupled to the pixel P(2m+1, n) and the data end of the pixel P(2m+2, n); and a source driving circuit, electrical The data lines are coupled to the source driving circuit via the data line X(m) during a t-th frame, respectively. The negative polarity, the negative polarity, the positive polarity, the negative polarity, the positive polarity, the positive polarity, and the negative polarity are sequentially driven to drive the pixels P (2m-1, n), P (2m, n), and P (2m-1, n+1), P(2m, n+1), P(2m-1, n+2), P(2m, n+2), P(2m-1, n+3) and P(2m,n +3), where t is an integer; wherein during the t-th frame, the source driving circuit respectively has "negative polarity, positive polarity, positive polarity, negative polarity, positive polarity," via the data line X(m+1) The negative polarity, the negative polarity, and the positive polarity drive the pixels P(2m+2,n), P(2m+1,n), P(2m+2,n+1), P(2m+1) sequentially. , n+1), P(2m+2, n+2), P(2m+1, n+2), P(2m+2, n+3), and P(2m+1, n+3). 如申請專利範圍第10項所述的顯示面板,更包括一源極驅動電路,其電性耦接該些資料線。 The display panel of claim 10, further comprising a source driving circuit electrically coupled to the data lines. 如申請專利範圍第11項所述的顯示面板,更包括一閘極驅動電路,其電性耦接該些掃描線,其中該閘極驅動電路配合該源極驅動電路之時序而循序驅動該些掃描線。 The display panel of claim 11, further comprising a gate driving circuit electrically coupled to the scan lines, wherein the gate driving circuit sequentially drives the timings of the source driving circuit Scan line.
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