TWI412487B - Method of forming nanowire structure - Google Patents

Abstract

A method of forming a nanowire structure is provided. First, a monocrystalline sacrificial layer and a dielectric pattern are sequentially formed on a substrate. Thereafter, a monocrystalline semiconductor film is formed on the substrate covering the monocrystalline sacrificial layer and the dielectric pattern. Then, a portion of the monocrystalline semiconductor film is removed, so as to form a nanowire structure in the form of a spacer on the sidewall of the dielectric pattern.

Description

Method for manufacturing nanowire structure

This invention relates to a nanotechnology, and more particularly to a method of making a nanowire structure.

With the demand for miniaturization of various products, the development of science and technology has gradually entered the so-called nano era from the micron era. There are quite a variety of nanomaterials, including metal nanomaterials, semiconductor nanomaterials, structural nanoceramics, and nanopolymer materials.

Although nanotechnology is the focus of technology development at home and abroad, the production of the nano-line is not easy and the reproducibility is low. At present, the polycrystalline semiconductor film produced by the conventional laser crystallization method on the glass substrate has poor crystallinity, and has various arbitrary lattice directions, so that the electrical characteristics and uniformity of the elements or circuits fabricated in the polycrystalline semiconductor film are obtained. Sex is very poor.

Therefore, it is necessary to produce a semiconductor film having good crystallinity (for example, a nanowire structure in a single crystal state), and to control its lattice direction, thereby effectively improving electrical characteristics and uniformity of components or circuits.

In view of the above, the present invention provides a method for fabricating a nanowire structure, which has a simple and rapid process and can produce a nanowire with high crystalline properties to effectively improve the electrical characteristics and uniformity of components or circuits.

The present invention provides a method of manufacturing a nanowire structure. First, a single crystal sacrificial layer and a dielectric pattern are sequentially formed on the substrate. Then, a single crystal semiconductor film is formed on the substrate to cover the single crystal sacrificial layer and the dielectric pattern. Next, a portion of the single crystal semiconductor film is removed to form a nanowire structure in the form of a spacer on the sidewall of the dielectric pattern.

In an embodiment of the invention, the method of forming the above-described single crystal semiconductor film comprises epitaxially growing a single crystal semiconductor film with a single crystal sacrificial layer as a seed layer.

In an embodiment of the present invention, a method of forming the above-described single crystal semiconductor film is described below. First, an amorphous semiconductor film is formed on the substrate to cover the single crystal sacrificial layer and the dielectric pattern. A method of forming an amorphous semiconductor film on a substrate includes performing a chemical vapor deposition process. Then, the amorphous semiconductor film is recrystallized into a single crystal semiconductor film by using a single crystal sacrificial layer as a seed layer.

In one embodiment of the present invention, a method of recrystallizing the amorphous semiconductor film into a single crystal semiconductor film includes solid state recrystallization. The process conditions of the solid state recrystallization process include heating at a temperature of about 600 ° C for about 24 hours.

In one embodiment of the present invention, a method of recrystallizing the amorphous semiconductor film into a single crystal semiconductor film includes a laser recrystallization method.

In an embodiment of the invention, the single crystal sacrificial layer comprises a single crystal germanium film or a single crystal germanium film.

In an embodiment of the invention, the single crystal semiconductor film comprises a single crystal germanium film, a single crystal germanium film, a single crystal germanium alloy film or a single crystal germanium carbon alloy film.

In an embodiment of the invention, after the step of forming the nanowire structure, the method further comprises fabricating the first component with the nanowire structure as the channel region.

In an embodiment of the invention, after the step of fabricating the first component with the nanowire structure as the channel region, the method further includes removing the single crystal sacrificial layer. The method of removing the single crystal sacrificial layer includes performing a dry etching process or a wet etching process. Dry etching process the etching gas comprises ammonia (NH ₄ OH) gas or hydrogen peroxide (H ₂ O ₂₎ gas. The etchant of the wet etching process includes an aqueous ammonia solution or an aqueous hydrogen peroxide solution. Then, the first component including the nanowire structure is transferred to the target substrate. The target substrate includes a flexible plastic substrate, a metal substrate, a glass substrate, or a semiconductor substrate.

In an embodiment of the invention, after the step of fabricating the first component with the nanowire structure as the channel region, the method further includes forming at least one second component on the first component.

In one embodiment of the invention, a method of removing a portion of the above-described single crystal semiconductor film includes performing a dry etching process.

In an embodiment of the invention, the material of the dielectric pattern comprises tantalum nitride.

In an embodiment of the invention, the dielectric pattern is a single layer structure.

In an embodiment of the invention, the dielectric pattern is a two-layer structure including a top dielectric pattern and a bottom dielectric pattern, and a cross section of the top dielectric pattern and the bottom dielectric pattern forms an inverted T shape. The material of the top dielectric pattern and the bottom dielectric pattern may be the same or different.

In an embodiment of the invention, the dielectric pattern is a multi-step multilayer structure, and the multi-step multilayer structure has a top width smaller than a bottom width thereof.

Based on the above, the present invention uses a single crystal sacrificial layer on a substrate as a seed layer to induce recrystallization or epitaxial growth of a single crystal semiconductor film on a dielectric pattern. Then, a part of the single crystal semiconductor film is removed by a dry etching process to form a nanowire structure in the form of a spacer on the sidewall of the dielectric pattern. The nanowire structure in the form of the above-mentioned spacers can be used as a channel region to fabricate desired components. The process of the invention is simple, rapid and can produce nanowires with high crystalline properties to effectively improve the electrical characteristics and uniformity of components or circuits.

Further, the nanowire structure of the present invention has wide applicability, and the element including the nanowire structure of the present invention can be transferred to a target substrate such as a soft plastic substrate; or can be formed over the element including the nanowire structure of the present invention. Another component is to form a three-dimensional stacked integrated circuit.

The above described features and advantages of the present invention will be more apparent from the following description.

First embodiment

1A to 1E are schematic cross-sectional views showing a method of fabricating a nanowire structure according to a first embodiment of the present invention.

First, referring to FIG. 1A, a single crystal sacrificial layer 102 and a dielectric pattern 104 are sequentially formed on the substrate 100. The substrate 100 is, for example, a semiconductor substrate such as a germanium substrate. The single crystal sacrificial layer 102 is, for example, a single crystal germanium film or a single crystal germanium film. The dielectric pattern 104 is, for example, a single layer structure, and the material thereof is, for example, tantalum nitride or hafnium oxide.

Then, a single crystal semiconductor film 106 is formed on the substrate 100 to cover the single crystal sacrificial layer 102 and the dielectric pattern 104. The single crystal semiconductor film 106 is, for example, a single crystal germanium film, a single crystal germanium film, a single crystal germanium alloy film, or a single crystal germanium carbon alloy film. In one embodiment, the method of forming the single crystal semiconductor film 106 includes epitaxially growing the single crystal semiconductor film 106 with the single crystal sacrificial layer 102 as a seed layer. In another embodiment, the method of forming the single crystal semiconductor film 106 includes forming an amorphous semiconductor film (not shown) on the substrate 100 to cover the single crystal sacrificial layer 102 and the dielectric pattern 104. A method of forming an amorphous semiconductor film on the substrate 100 is, for example, a chemical vapor deposition (CVD) process. Then, the amorphous semiconductor film is recrystallized into the single crystal semiconductor film 106 by using the single crystal sacrificial layer 102 as a seed layer. The method of recrystallizing the amorphous semiconductor film into the single crystal semiconductor film 106 is, for example, a solid state recrystallization method, and the process conditions include heating at a temperature of about 600 ° C for about 24 hours. The method of recrystallizing the amorphous semiconductor film into the single crystal semiconductor film 106 may also be a laser recrystallization method.

Next, referring to FIG. 1C, a portion of the single crystal semiconductor film 106 is removed to form a nanowire structure 108 in the form of a spacer on the sidewall of the dielectric pattern 104. The method of removing a portion of the single crystal semiconductor film 106 includes performing a dry etching process, such as an anisotropic dry etching process. It is particularly noted that the nanowire structure 108 in the form of a spacer is a channel region (or active region) of a subsequent component such as an integrated circuit (IC), a thin film transistor (TFT), or a sensor. Thereafter, additional features (not shown) such as a gate oxide layer, a gate, a source/drain, etc., may be stacked on the nanowire structure 108 to fabricate the desired components. These components and methods of forming the same are well known to those of ordinary skill in the art and will not be described again.

After the desired elements are formed, the single crystal sacrificial layer 102 can be removed, as shown in FIG. 1D. In one embodiment, the method of removing the single crystal sacrificial layer 102 is, for example, a dry etching process, and the etching gas includes ammonia water or hydrogen peroxide gas. In another embodiment, the method of removing the single crystal sacrificial layer 102 is, for example, a wet etching process, and the etchant thereof includes an aqueous ammonia solution or an aqueous hydrogen peroxide solution. In this step, the substrate 100 separated from the dielectric pattern 104 and the nanowire structure 108 can be recycled and reused, and the steps of FIGS. 1A to 1D are repeated again. Next, the component including the nanowire structure 108 can be transferred onto the target substrate 110 as shown in FIG. 1E. The target substrate 110 includes a flexible plastic substrate, a metal substrate, a glass substrate, a semiconductor substrate, or the like.

Of course, after forming the desired elements (first elements), it is also possible to continue stacking upwards to form a three-dimensionally stacked integrated circuit, the method of which is described below. First, a passivation layer (not shown) is formed on the substrate 100 to protect the first component. Then, an opening connected to the sacrificial layer 102 of the single crystal state is formed in the protective layer. Then, another dielectric pattern is formed on the protective layer, and then the single crystal sacrificial layer 104 is used as the seed layer, and the single crystal semiconductor film is formed along the opening on the other dielectric pattern. Thereafter, a second element is formed over the aforementioned first element in accordance with the steps of FIG. 1C. The above steps can be repeated multiple times to form a three-dimensional stacked integrated circuit.

In the above embodiment, the dielectric pattern 104 is exemplified as a single layer structure, but the invention is not limited thereto. It should be understood by those of ordinary skill in the art that the dielectric pattern 104 can also be an inverted T-shaped two-layer structure or a multi-stepped multilayer structure with a top width that is less than its bottom width. Hereinafter, a manufacturing method in the case where the dielectric pattern 104 is an inverted T-shaped double layer structure will be described.

Second embodiment

2A to 2C are schematic cross-sectional views showing a method of fabricating a nanowire structure according to a second embodiment of the present invention. The second embodiment is similar to the first embodiment, and the differences will be described below, and the same portions will not be described again.

First, referring to FIG. 2A, a single crystal sacrificial layer 102 and a dielectric pattern 104 are sequentially formed on the substrate 100. The substrate 100 is, for example, a semiconductor substrate such as a germanium substrate. The single crystal sacrificial layer 102 is, for example, a single crystal germanium film or a single crystal germanium film. The dielectric pattern 104 is, for example, a two-layer structure including a top dielectric pattern 104a and a bottom dielectric pattern 104b, and the cross sections of the top dielectric pattern 104a and the bottom dielectric pattern 104b form an inverted T shape, that is, the top width thereof is smaller than Its bottom width. The material of the top dielectric pattern 104a and the bottom dielectric pattern 104b is, for example, tantalum nitride or tantalum oxide, and the materials of the top dielectric pattern 104a and the bottom dielectric pattern 104b may be the same or different. In one embodiment, the material of the top dielectric pattern 104a is, for example, tantalum oxide, and the material of the bottom dielectric pattern 104b is, for example, tantalum nitride.

Then, referring to FIG. 2B, a single crystal semiconductor film 106 is formed on the substrate 100 to cover the single crystal sacrificial layer 102 and the dielectric pattern 104. The single crystal semiconductor film 106 is, for example, a single crystal germanium film, a single crystal germanium film, a single crystal germanium alloy film, or a single crystal germanium carbon alloy film. In one embodiment, the method of forming the single crystal semiconductor film 106 includes epitaxially growing the single crystal semiconductor film 106 with the single crystal sacrificial layer 102 as a seed layer. In another embodiment, the method of forming the single crystal semiconductor film 106 includes forming an amorphous semiconductor film (not shown) on the substrate 100 to cover the single crystal sacrificial layer 102 and the dielectric pattern 104. Then, the amorphous semiconductor film is recrystallized into the single crystal semiconductor film 106 by using the single crystal sacrificial layer 102 as a seed layer. The method of recrystallizing the amorphous semiconductor film into the single crystal semiconductor film 106 is, for example, a solid state recrystallization method or a laser recrystallization method.

Next, referring to FIG. 2C, a portion of the single crystal semiconductor film 106 is removed to form a nanowire structure 108 in the form of a spacer on the sidewall of the dielectric pattern 104. In this embodiment, since the dielectric pattern 104 is an inverted T-shaped double layer structure including the top dielectric pattern 104a and the bottom dielectric pattern 104b, the nanowire structures 108a, 108b in the form of spacers are respectively formed in the top dielectric layer. The sidewalls of the electrical pattern 104a and the bottom dielectric pattern 104b. The method of removing a portion of the single crystal semiconductor film 106 includes performing a dry etching process, such as an anisotropic dry etching process. It is particularly noted that when the material of the nanowire structure 108 is, for example, germanium, the nanowire structure 108a on the sidewall of the top dielectric pattern 104a and the underlying dielectric pattern 104b thereunder can be considered to be flawed on the insulator ( The structure of silicon-on-insulator; SOI). Thereafter, the nanowire structure 108 in the form of a spacer is used to fabricate the desired components for the channel region.

Next, the single crystal sacrificial layer 102 can be removed and the component comprising the nanowire structure 108 can be transferred onto the target substrate; alternatively, another component can be formed over the component comprising the nanowire structure 108 to form a three-dimensional stack. The integrated circuit.

In summary, the present invention uses a single crystal sacrificial layer on a substrate as a seed layer to induce recrystallization or epitaxial growth of a single crystal semiconductor film on a dielectric pattern. Then, a part of the single crystal semiconductor film is removed by a dry etching process to form a nanowire structure in the form of a spacer on the sidewall of the dielectric pattern. The method of manufacturing a nanowire structure of the present invention has at least the following advantages:

1. The present invention can be used for a flexible plastic substrate, a metal substrate, a glass substrate, a semiconductor substrate or the like.

2. The invention can be used in a three-dimensional stacked integrated circuit process technology.

3. The present invention can produce a semiconductor channel having high crystallinity (or single crystal property) on a substrate having a low melting point.

4. The single crystal semiconductor film produced by the present invention has good crystallinity and can control its lattice direction, thereby effectively improving electrical characteristics and uniformity of components or circuits.

5. This technology can greatly advance the development of system-on-panel.

6. This technology can be used to fabricate silicon-on-insulator (SOI) on a low-cost basis, thus providing an opportunity to replace the current high-cost SOI production.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100. . . Substrate

102. . . Single crystal sacrificial layer

104. . . Dielectric pattern

104a. . . Top dielectric pattern

104b. . . Bottom dielectric pattern

106. . . Single crystal semiconductor film

108, 108a, 108b. . . Nanowire structure

110. . . Target substrate

1A to 1E are schematic cross-sectional views showing a method of fabricating a nanowire structure according to a first embodiment of the present invention.

2A to 2C are schematic cross-sectional views showing a method of fabricating a nanowire structure according to a second embodiment of the present invention.

100. . . Substrate

102. . . Single crystal sacrificial layer

104. . . Dielectric pattern

104a. . . Top dielectric pattern

104b. . . Bottom dielectric pattern

108a, 108b, 108. . . Nanowire structure

Claims (21)

A method for fabricating a nanowire structure comprises: sequentially forming a single crystal sacrificial layer and a dielectric pattern on a substrate; forming a single crystal semiconductor film on the substrate to cover the single crystal sacrificial layer and a dielectric pattern; and removing a portion of the single crystal semiconductor film to form a nanowire structure in the form of a spacer on the sidewall of the dielectric pattern, wherein the single crystal sacrificial layer comprises a single crystal germanium film or The single crystal germanium film includes a single crystal germanium film, a single crystal germanium film, a single crystal germanium alloy film or a single crystal germanium carbon alloy film. The method for producing a nanowire structure according to claim 1, wherein the method of forming the single crystal semiconductor film comprises epitaxially growing the single crystal semiconductor film with the single crystal sacrificial layer as a seed layer. The method for fabricating a nanowire structure according to claim 1, wherein the method for forming the single crystal semiconductor film comprises: forming an amorphous semiconductor film on the substrate to cover the single crystal sacrificial layer; The dielectric pattern; and the single crystal sacrificial layer is a seed layer, and the amorphous semiconductor film is recrystallized into the single crystal semiconductor film. The method for fabricating a nanowire structure according to claim 3, wherein the method of forming the amorphous semiconductor film on the substrate comprises performing a chemical vapor deposition process. The method for fabricating a nanowire structure according to claim 3, wherein the amorphous semiconductor film is recrystallized into the single crystal state semiconductor The method of bulk film includes a solid state recrystallization method. The method for producing a nanowire structure according to claim 5, wherein the process conditions of the solid state recrystallization method comprise heating at a temperature of 600 ° C for 24 hours. The method for producing a nanowire structure according to claim 3, wherein the method of recrystallizing the amorphous semiconductor film into the single crystal semiconductor film comprises a laser recrystallization method. The method for manufacturing a nanowire structure according to claim 1, wherein after the step of forming the nanowire structure, the method further comprises: fabricating a first component by using the nanowire structure as a channel region. The method for manufacturing a nanowire structure according to the eighth aspect of the invention, after the step of fabricating the first component by using the nanowire structure as a channel region, further comprising: removing the single crystal sacrificial layer; The first component including the nanowire structure is transferred to a target substrate. The method for manufacturing a nanowire structure according to claim 9, wherein the method of removing the single crystal sacrificial layer comprises performing a dry etching process or a wet etching process. The method for manufacturing a nanowire structure according to claim 10, wherein the etching gas of the dry etching process comprises ammonia gas or hydrogen peroxide gas. The method for manufacturing a nanowire structure according to claim 10, wherein the wet etching process etchant comprises an aqueous ammonia solution or a double oxygen solution. Aqueous solution. The method for manufacturing a nanowire structure according to claim 9, wherein the target substrate comprises a flexible plastic substrate, a metal substrate, a glass substrate or a semiconductor substrate. The method for manufacturing a nanowire structure according to claim 8, wherein after the step of fabricating the first component by using the nanowire structure as a channel region, further comprising forming at least one second on the first component element. The method for fabricating a nanowire structure according to claim 1, wherein the method of removing a portion of the single crystal semiconductor film comprises performing a dry etching process. The method for fabricating a nanowire structure according to claim 1, wherein the material of the dielectric pattern comprises tantalum nitride or hafnium oxide. The method of manufacturing a nanowire structure according to claim 1, wherein the dielectric pattern is a single layer structure. The method for fabricating a nanowire structure according to claim 1, wherein the dielectric pattern is a two-layer structure including a top dielectric pattern and a bottom dielectric pattern, and the top dielectric pattern and the The cross section of the bottom dielectric pattern constitutes an inverted T shape. The method for fabricating a nanowire structure according to claim 18, wherein the top dielectric pattern is the same material as the bottom dielectric pattern. The method for fabricating a nanowire structure according to claim 18, wherein the top dielectric pattern is different from the material of the bottom dielectric pattern. The method for manufacturing a nanowire structure according to claim 1, wherein the dielectric pattern is a multi-stepped multi-layer structure, and The multi-stepped multilayer structure has a top width that is less than its bottom width.