TWI412232B - Frequency generator with frequency jitter - Google Patents

Abstract

A frequency generator with frequency jitter is disclosed. The frequency generator comprises a capacitor, a comparing unit, a charging and discharging unit, a delay unit, and a charging and discharging switch unit. The comparing unit is coupled to the capacitor and generates a charging and discharging control signal according to a voltage of the capacitor. The charging and discharging unit is coupled to the capacitor. The delay unit is coupled to the comparing unit and receives a delay signal. The delay unit delays the charging and discharging control signal according to the delay signal to generate a charging and discharging delay signal. The charging and discharging switch unit is coupled to the charging and discharging unit and the delay unit, and charges or discharges the capacitor according to the charging and discharging delay signal.

Description

Frequency generator with frequency jitter

The present invention relates to a frequency generator, and more particularly to a frequency generator with frequency jitter.

The first picture shows the circuit diagram of a conventional frequency generator. A first current source I1 and a second current source I2 respectively charge and discharge a capacitor C through a corresponding first switch SW1 and a second switch SW2. A first comparator COM1 receives a first reference voltage V1 at an inverting terminal and a capacitor C at a non-inverting terminal to compare the voltage of the capacitor C with the first reference voltage V1. A second comparator COM2 receives a second reference voltage V2 at a non-inverting terminal, and a capacitor C coupled to an inverting terminal to compare the voltage of the capacitor C with the second reference voltage V2. An SR flip-flop SRIN receives the output signals of the first comparator and the second comparator to generate a clock signal CLK accordingly. The clock signal CLK serves as a control signal for the first switch SW1 and the second switch SW2 at the same time. When the pulse signal CLK is at the high level, the first switch SW is turned off, and the second switch SW2 is turned on, and the second current source I2 is discharged to the capacitor C. When the voltage of the capacitor C gradually decreases and is equal to the second reference voltage V2, the second comparator COM2 outputs a high level signal to turn the clock signal CLK to a low level. When the pulse signal CLK is at the low level, the first switch SW is turned on, and the second switch SW2 is turned off, and the first current source I1 charges the capacitor C. When the voltage of the capacitor C gradually rises and is equal to the first reference voltage V1, the first comparator COM1 outputs a high level signal to turn the clock signal CLK into a high level. Since the voltage difference between the first reference voltage V1 and the second reference voltage V2 is fixed, the magnitudes of the currents of the first current source I1 and the second current source I2 are fixed. Therefore, a fixed frequency clock signal CLK can be generated.

In order to obtain the frequency jitter of the conventional circuit, the current value of the first current source I1 and the second current source I2, the voltage values of the first reference voltage V1 and the second reference voltage V2 can be shaken. Obtained with frequency jitter Clock signal CLK. This way of implementing jitter is more suitable for regular and slow jitter, but if the actual application requires fast and random jitter, this method cannot be applied.

In view of the jitter mode of the frequency generator in the prior art, it is unable to provide fast and random jitter, and the present invention utilizes the delay mode to logically shift the clock signal of the frequency generator (ie, the high level is turned to the low level and The time point at which the low level is turned to the high level is delayed to achieve fast and random jitter.

To achieve the above objective, the present invention provides a frequency generator with frequency jitter, comprising a capacitor, a comparison unit, a charge and discharge unit, a delay unit, and a charge and discharge switch unit. The comparison unit is coupled to the capacitor to generate a charge and discharge control signal according to the voltage of the capacitor. The charge and discharge unit is coupled to the capacitor. The delay unit is coupled to the comparison unit to receive a delay signal and delay the charge and discharge control signal to become a charge and discharge delay signal. The charge and discharge switch unit is coupled to the charge and discharge unit and the delay unit to control the charge and discharge unit to charge or discharge the capacitor according to the charge and discharge delay signal.

The above summary and the following detailed description are exemplary in order to further illustrate the scope of the claims. Other objects and advantages of the present invention will be described in the following description and drawings.

The second figure is a circuit diagram of a frequency generator with frequency jitter in accordance with a preferred embodiment of the present invention. The frequency generator includes a capacitor C, a comparison unit COM, a charge and discharge unit, a delay unit 10, and a charge and discharge switch unit SW. The charge and discharge unit includes a charge current source Ich and a discharge current source Ids. The comparison unit COM is coupled to the capacitor C to generate a charge and discharge control signal SRO according to the capacitor voltage Vc of the capacitor C. The delay unit 10 is coupled to the comparison unit COM, and receives a delay signal Delay at the input terminal IN. The delay unit 10 generates a first control signal S1 and a second control signal S2 as charging and discharging delay signals according to the delay signal Delay and the delayed charging and discharging control signal SRO at the charging control terminal CHRG and the discharging control terminal DSRG, respectively. The charge and discharge switch unit SW is coupled to the charge and discharge unit and the delay unit 10 to control the charge current source Ich and the discharge current source Ids of the charge and discharge unit to charge the capacitor C according to the first control signal S1 and the second control signal S2, respectively, to change The voltage Vc of the capacitor C. The charge and discharge switch unit SW in this embodiment includes a charge switch M1 and a discharge switch M2. The charge switch M1 and the discharge switch M2 are not turned on at the same time. That is to say, when the charging switch M1 is turned on, the discharging switch M2 is turned off, and when the charging switch M1 is turned off, the discharging switch M2 is turned on. In this embodiment, the charging switch M1 is a P-type gold-oxygen half-field effect transistor and the discharge switch M2 is an N-type gold-oxygen half-field effect transistor, so that the same signal can achieve the above-mentioned on and off timing requirements. That is, the first control signal S1 and the second control signal S2 may be the same signal. The actual circuit design may set a delay between the end of the first control signal S1 and the beginning of the second control signal S2, and/or after the end of the second control signal S2 to the beginning of the first control signal S1. In this embodiment, a delay time is set according to the delay signal Delay between the first control signal S1 and the second control signal S2.

Next, the detailed operation of the frequency generator will be described. Please also refer to the third figure, which is the signal waveform diagram of the frequency generator shown in the second figure. The comparison unit COM includes a discharge comparator 12, a charge comparator 14, and an SR flip-flop 16. The non-inverting input of the discharge comparator 12 is coupled to the capacitor C at the same time as the inverting input of the charge comparator 14. The discharge comparator 12 receives a first reference signal Ref1 at an inverting input, and the charge comparator 14 receives a second reference signal Ref2 at a non-inverting input. The first reference signal Ref1 is higher than the first reference signal Ref1. The reference signal Ref2 is at the level. The output end of the discharge comparator 12 is coupled to the set terminal S of the SR flip-flop 16 , and the output end of the charge comparator 14 is coupled to the reset terminal R of the SR flip-flop 16 .

When the capacitor C is in the charging state, the capacitor voltage Vc gradually rises. When the capacitor voltage Vc reaches the level of the first reference signal Ref1, the discharge comparator 12 outputs a high level signal to the set terminal S of the SR flip-flop 16 to cause the charge and discharge control signal output by the SR flip-flop at the output terminal Q. The SRO transitions to a high level and simultaneously triggers the delay unit 10 to directly turn the first control signal S1 to a high level. The delay unit 10 uses the time point of the logic transition state of the charge and discharge control signal SRO as a reference and according to the delay signal Delay, the transition time of the second control signal S2 from the low level to the high level will be more charged and discharged. The signal SRO is delayed by a time difference, that is, the time difference d1, d3, d5 shown in the third figure. Therefore, when the charge and discharge control signal SRO is turned to the high level, the second control signal S2 will be turned into a high level later, and the charging switch M1 is turned off because the first control signal S1 is at a high level during this time. Therefore, the capacitor voltage Vc is maintained at the level of the first reference signal Ref1. After the second control signal S2 is turned to the high level, the discharge switch M2 is turned on, so that the discharge current source Ids starts to discharge the capacitor C, and the capacitor C enters the discharge state to cause the capacitor voltage Vc to start to decrease. When the capacitor voltage Vc falls to the level of the second reference signal Ref2, the charge comparator 14 outputs a high level signal to the reset terminal R of the SR flip-flop 16 to charge and discharge the output of the SR flip-flop at the output terminal Q. The control signal SRO is turned to a low level, and the delay unit 10 is simultaneously triggered to directly turn the second control signal S2 to a low level. The delay unit 10 also adjusts the high-level of the first control signal S1 to the low-level transition time point based on the time point of the delay signal delay to delay the logic transition state of the charge-discharge control signal SRO. The SRO is delayed by a time difference, that is, the time difference d2, d4, d6 shown in the third figure. Therefore, when the charge and discharge control signal SRO is turned to the low level, the first control signal S1 will be turned to a low level later, and the discharge switch M2 is turned off because the second control signal S2 is at the low level during this time. Therefore, the capacitor voltage Vc is maintained at the level of the second reference signal Ref2. After the first control signal S1 is turned to the low level, the charging switch M1 is turned on to cause the charging current source Ich to start charging the capacitor C, and the capacitor C enters the charging state to cause the capacitor voltage Vc to start to rise.

In this embodiment, the charge and discharge control signal SRO, the first control signal S1 The second control signal S2 has a frequency jitter. Therefore, the delay unit 10 can output the clock signal CLK according to one of the signals, so that the clock signal CLK is a signal with frequency jitter. The delay signal Delay may be a noise, and the delay unit 10 may change the delay length with the noise level; or the delay signal Delay may be a digital random signal, and the delay unit 10 is a digital circuit, which is random according to the digital position. The signal sets the length of time for the delay. In particular, the delay signal Delay can be a programmable digital circuit, which can make the frequency jitter of the frequency generator programmable, and can achieve the advantage of programmable jitter.

As described above, the present invention fully complies with the three requirements of the patent: novelty, advancement, and industrial applicability. The invention has been described above in terms of the preferred embodiments, and it should be understood by those skilled in the art that the present invention is not intended to limit the scope of the invention. It should be noted that variations and permutations equivalent to those of the embodiments are intended to be included within the scope of the present invention. Therefore, the scope of the invention is defined by the scope of the following claims.

Prior art:

I1‧‧‧ first current source

I2‧‧‧second current source

SW1‧‧‧ first switch

SW2‧‧‧second switch

C‧‧‧ capacitor

COM1‧‧‧First Comparator

COM2‧‧‧Second comparator

V1‧‧‧ first reference voltage

V2‧‧‧second reference voltage

SRIN‧‧‧SR flip-flop

CLK‧‧‧ clock signal

this invention:

10‧‧‧Delay unit

12‧‧‧Discharge comparator

14‧‧‧Charging comparator

16‧‧‧SR flip-flop

C‧‧‧ capacitor

COM‧‧‧ comparison unit

SW‧‧‧Charge and discharge switch unit

Ich‧‧‧Charging current source

Ids‧‧‧discharge current source

Vc‧‧‧ capacitor voltage

SRO‧‧‧charge and discharge control signal

CHRG‧‧‧Charging console

DSRG‧‧‧Discharge control terminal

S1‧‧‧ first control signal

S2‧‧‧second control signal

M1‧‧‧Charge switch

M2‧‧‧discharge switch

Ref1‧‧‧ first reference signal

Ref2‧‧‧second reference signal

S‧‧‧Setting end

R‧‧‧Reset

Q‧‧‧output

Delay‧‧‧delay signal

D1~d6‧‧‧ time difference

CLK‧‧‧ clock signal

The first picture shows the circuit diagram of a conventional frequency generator.

The second figure is a circuit diagram of a frequency generator with frequency jitter in accordance with a preferred embodiment of the present invention.

The third figure is the signal waveform diagram of the frequency generator shown in the second figure.

10‧‧‧Delay unit

12‧‧‧Discharge comparator

14‧‧‧Charging comparator

16‧‧‧SR flip-flop

C‧‧‧ capacitor

COM‧‧‧ comparison unit

SW‧‧‧Charge and discharge switch unit

Ich‧‧‧Charging current source

Ids‧‧‧discharge current source

Vc‧‧‧ capacitor voltage

SRO‧‧‧charge and discharge control signal

CHRG‧‧‧Charging console

DSRG‧‧‧Discharge control terminal

S1‧‧‧ first control signal

S2‧‧‧second control signal

M1‧‧‧Charge switch

M2‧‧‧discharge switch

Ref1‧‧‧ first reference signal

Ref2‧‧‧second reference signal

S‧‧‧Setting end

R‧‧‧Reset

Q‧‧‧output

Delay‧‧‧delay signal

Claims (7)

A frequency generator with frequency jitter includes: a capacitor; a comparison unit coupled to the capacitor to generate a charge and discharge control signal according to the voltage of the capacitor; a charge and discharge unit coupled to the capacitor; a delay unit coupled Receiving a delay signal and delaying the charge and discharge control signal to become a charge and discharge delay signal; and a charge and discharge switch unit coupled to the charge and discharge unit and the delay unit to receive the charge and discharge delay signal Controlling the charging and discharging unit to charge or discharge the capacitor, wherein a time difference between an enabling period of the charging and discharging delay signal and an enabling period of the charging and discharging control signal is determined according to the delay signal, and the charging and discharging delay signal is A pulse signal output, wherein the enable period refers to a time during which the charge and discharge control signal and the charge and discharge enable signal are maintained at a high level or a low level. The frequency generator of claim 1 , wherein the comparison unit comprises a first comparator and a second comparator, and an inverting input of the first comparator receives a first a non-inverting input terminal of the second comparator receives a second reference voltage, and an inverting input terminal of the second comparator and a non-inverting input terminal of the first comparator are coupled to the second comparator a capacitor, and the first reference voltage is higher than the second reference voltage. The frequency generator of the frequency jitter as described in claim 2, wherein the comparing unit further includes a flip-flop, the flip-flop receiving the output signals of the first comparator and the second comparator, According to this, the charge and discharge control signal is generated and the charge and discharge control signal is used as a pulse signal. The frequency generator of the frequency jitter according to claim 1, wherein the time difference between the enable period of the charge and discharge delay signal and the enable period of the charge and discharge control signal is randomly determined according to the delay signal. The frequency generator of claim 4, wherein the comparison unit comprises a first comparator and a second comparator, and the inverting input of the first comparator receives a first a non-inverting input terminal of the second comparator receives a second reference voltage, and an inverting input terminal of the second comparator and a non-inverting input terminal of the first comparator are coupled to the second comparator a capacitor, and the first reference voltage is higher than the second reference voltage. The frequency generator of the frequency jitter according to claim 5, wherein the comparison unit further comprises a flip-flop, the flip-flop receiving the output signals of the first comparator and the second comparator, Accordingly, the charge and discharge control signal is generated. The frequency generator having frequency jitter according to claim 6 , wherein the charging and discharging unit comprises a charging current source for charging the capacitor, and a discharging current source for discharging the capacitor.