TWI412022B - Recursive discrete cosine transform and inverse discrete cosine transform system - Google Patents

Abstract

The invention provides a recursive discrete cosine transform and inverse discrete cosine transform system. The first unit receives N digital signals and performs operation on the N digital signals to generate first temporal signals. The second unit performs an operation on the first temporal signals to generate second temporal signals. An IDCT-II unit performs operation on the second temporal signals to generate third temporal signals. The third unit performs an operation on third temporal signals to generate first output signals. The fourth unit performs an operation on the first output signals to generate second output signals. When the N digital signals are the input of the system, the first output signals are the discrete cosine transform of the N digital signals, and when first temporal signals are the input of the system, the second output signals are the inverse discrete cosine transform of the first temporal signals.

Description

Recursive discrete cosine forward and inverse conversion system

The invention relates to the technical field of digital signal processing, in particular to a recursive discrete cosine forward and inverse conversion system.

Due to the increasingly developed technology of digital signal processing, it is convenient to obtain information and enjoy various multimedia information in daily life. Based on the subband analysis/synthesis method, the modified discrete cosine transform (MDCT) and the inverse modified discrete cosine transform (IMDCT) have been widely used in various audio coding. Decoding standard.

In AC-3, MP3 and AAC decoding, the filter bank accounts for most of the computational complexity of each decoder, and the main function of the filter bank is to transfer audio from the spectrum signal to the time axis signal. Perform inverse modified Discrete Cosine Transform (IMDCT); the original inverse modified discrete cosine transform (IMDCT) method is complex. Times, where N is the window length.

Each codec standard specifies the size of the window length. For long windows, MP3 decoding requires 36 points, and the digital radio mondiale advanced Audio coding, DRM AAC) requires 1920 points, and MPEG-2/4 advanced audio coding (MPEG-2/4 AAC) requires 2048 points, thus increasing the complexity of the operation. Although the prior art has improved discrete cosine transform (MDCT) and inverse modified discrete cosine transform (IMCT) designs using parallel techniques, which are based on a butterfly-type design architecture, such designs increase the data frequency of the circuit architecture. The complexity of the width and control. At the same time, under the format constraints of MPEG-2/4 Advanced Audio Coding (MPEG-2/4 AAC) and Digital Radio Advanced Audio Coding (DRM AAC), the parallel architecture circuit design is not appropriate if a fully parallel architecture is used ( Fully parallel implementation will have a problem of excessive hardware area.

In the paper "Regressive implementations for the forward and inverse MDCT in MPEG audio coding" published by Chiang & Liu in Signal Processing Letters, IEEE, vol. 3 pp. 116-118, 1996, a sinusoidal recursive architecture is proposed. As a core, a method for calculating improved discrete cosine transform (MDCT) and inverse modified discrete cosine transform (IMDCT) is performed. The paper "Computation of forward and inverse MDCT using Clenshaw's recurrence formula" proposed by Nikolajevic & Fettweis in Signal Processing, IEEE Transactions on, vol. 51, pp. 1439-1444, 2003 is based on the Clenshaw recursive architecture. To design a general length of modified discrete cosine transform (MDCT) and inverse modified discrete cosine transform (IMDCT).

In the Chiang & Liu paper and the Nikolajevic & Fettweis paper, the calculation of N-point MDCT is required. Cycles are required to get the result of the operation. In order to speed up the processing speed, Chen et al., "Recursive architectures for realizing modified discrete cosine transform and" in Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on, vol. 50, pp. 38-45, 2003. In its inverse paper, an efficient architecture is proposed to implement the improved discrete cosine transform (MDCT) and inverse modified discrete cosine transform (IMDCT) methods with the Chebyshev polynomial idea. The proposed architecture calculates each improved type. The discrete cosine transform (MDCT) operation requires only N/4 cycles, which converts the discrete cosine fourth type (DCT-IV) pattern of the core part into discrete cosine type 2 (DCT-II) and Discrete sinusoidal type 2 (DST-II) type.

Although the core architecture proposed by Chen et al. uses multiply the coefficient of inverse cosine to reduce computational complexity and increase data throughput, it also increases the dynamic range of the signal and reduces the improved The accuracy of discrete cosine transform (MDCT) and inverse modified discrete cosine transform (IMCT) fixed-point arithmetic operations.

Lei et al., "A high-precision algorithm for the forward and inverse MDCT using the unified recursive architecture" in Consumer Electronics, 2008. ISCE 2008. IEEE International Symposium for improved discrete cosine transform (MDCT) and inverse improvement The operation of the Discrete Cosine Transform (IMCT) proposes a unified architecture whose multiplication uses the same cosine value. Compared with the method proposed by Chiang and Liu and Chen et al., Lei et al.'s pre-processing has a small dynamic range, so its core fixed-point arithmetic operations will have more accurate operations. It transforms the modified discrete cosine transform (MDCT) and inverse modified discrete cosine transform (IMDCT) from the core form of discrete cosine fourth type (DCT-IV) into discrete cosine type 2 (DCT-II) and discrete sine The core type of the second type (DST-II), so the modified discrete cosine transform (MDCT) and the inverse modified discrete cosine transform (IMDCT) can be derived into the same formula and use the same core architecture.

Lei et al., Papers and Systems II: Express Briefs, IEEE Transactions on, vol. 56, pp. 793-797, 2009, "Common Architecture Design of Novel Recursive MDCT and IMDCT Algorithms for Application to AAC, AAC in DRM, and MP3 Codecs" simplifies the amount of coefficients used in multiplication, and derives improved discrete cosine transform (MDCT) and inverse modified discrete cosine transform with discrete cosine fourth type (DCT-IV) as the core. (IMDCT) A common architectural approach to storing the coefficients of the operation with minimal memory.

L. Lin et al., "Efficient architectures of MDCT/IMDCT implementation for MPEG audio codec", Anti-counterfeiting, Security, and Identification in Communication, 2009. ASID 2009. 3rd International Conference on, 2009, pp. 156-159 A high-efficiency method is also proposed, which splits the modified discrete cosine transform (MDCT) function of point N into odd/even parts, and then reduces them into discrete cosine fourth type (DCT-IV), and then Fast Fourier Transform (FFT) to achieve its core architecture.

Lei et al.'s paper "Low Complexity and Fast Computation for Recursive MDCT and IMDCT Algorithms" published in IEEE Transactions on Circuits and Systems II: Express Briefs Vol.57, No.7, July 2010 The Field Programming Gate Array (FPGA) is used to implement hardware acceleration. The concept of recursive and hardware implementation can also effectively reduce the hardware requirements and achieve a low-cost design consideration.

Although the system of discrete cosine forward and reverse conversion has been developed for many years, in order to further reduce the computational complexity, reduce the hardware cost, and improve the performance of data calculation, the above system with discrete cosine forward and reverse conversion still has improvement. Need.

The main object of the present invention is to provide a recursive discrete cosine forward and inverse conversion system which has low computational complexity and uses a small amount of multiplication coefficient usage and has high performance data calculation.

According to a feature of the present invention, the present invention provides a recursive discrete cosine forward and inverse conversion system, which is based on an inverse discrete cosine second type (IDCT-II), the system comprising a first arithmetic unit, a a second arithmetic unit, an inverse discrete cosine second type (IDCT-II) unit, a third arithmetic unit, and a fourth arithmetic unit. The first computing unit receives N input digital signals, and performs operations on the N digital signals to generate N/2 first temporary signals, where N is a positive integer of a multiple of 4. The second computing unit is connected to the first computing unit, and the N/2 first temporary messages The number performs an arrangement operation to generate N/2 second temporary signals. The inverse discrete cosine second type (IDCT-II) unit is connected to the second operation unit, and performs operations on the N/2 second temporary signals to generate N/2 third temporary corresponding to the input digital signal. Signal. The third operation unit is connected to the IDCT-II unit, and performs an arrangement operation on the N/2 third temporary signals to generate N/2 first output digital signals. The fourth operation unit is connected to the third operation unit, and performs an arrangement operation on the N/2 first output digital signals to generate N second output digital signals; wherein, when the input of the system is the N inputs The digital output signal, the N/2 first output digital signals outputted by the third computing unit are discrete cosine signals corresponding to the N input digital signals, when the input of the system is the first temporary signal, The N second output digit signals output by the fourth computing unit are inverse discrete cosine signals corresponding to the first temporary signal.

According to another feature of the present invention, the present invention provides a recursive discrete cosine forward and inverse conversion system, which is based on an inverse discrete cosine second type (IDCT-II), the system comprising a first arithmetic unit, a second arithmetic unit, a third arithmetic unit, a fourth arithmetic unit, a first inverse discrete cosine second type (IDCT-II) unit, a second inverse discrete cosine second type (IDCT-II) unit, a fifth arithmetic unit, a sixth arithmetic unit, and a seventh arithmetic unit. The first operation unit receives N input digital signals, and performs operations on the N digital signals to generate N/2 first temporary signals, where N is a positive integer of a multiple of 8. The second operation unit is connected to the first operation unit, and performs an arrangement operation on the N/2 first temporary signals to generate N/2 second temporary signals. The third operation unit is connected to the second operation unit, and performs an operation on the N/2 second temporary signals, To generate N/4 third temporary signals and N/4 fourth temporary signals. The fourth operation unit is connected to the third operation unit, and performs an operation on the N/4 fourth temporary signals to generate N/4 fifth temporary signals. The first inverse discrete cosine second type (IDCT-II) unit is connected to the third arithmetic unit, and performs an operation on the N/4 third temporary signals to generate N/4 sixth temporary signals. The second inverse discrete cosine second type (IDCT-II) unit is connected to the fourth arithmetic unit, and performs an operation on the N/4 fifth temporary signals to generate N/4 seventh temporary signals. The fifth arithmetic unit is coupled to the second inverse discrete cosine second type (IDCT-II) unit, and performs an operation on the N/4 seventh temporary signals to generate N/4 eighth temporary signals. The sixth arithmetic unit is connected to the first inverse discrete cosine second type (IDCT-II) unit and the fifth arithmetic unit, and performs the N/4 sixth temporary signals and the N/4 eighth temporary signals. Operate to generate N/2 first output signals. The seventh operation unit is connected to the sixth operation unit, and performs operations on the N/2 first output signals to generate N second output signals. Wherein, when the input of the system is the N input digit signals, the N/2 first output signals output by the sixth operation unit are discrete cosine signals corresponding to the N input digital signals, when the system When the input is the first temporary signal, the N second output digital signals output by the seventh computing unit are inverse discrete cosine signals corresponding to the first temporary signal.

1 is a schematic diagram of one embodiment of a system 100 of recursive discrete cosine forward and reverse conversions of the present invention. It is based on the inverse discrete cosine second type (IDCT-II), which includes a first arithmetic unit. 110. A second computing unit 120, an inverse discrete cosine second type (IDCT-II) unit 130, a third computing unit 140, and a fourth computing unit 150.

The first computing unit 110 receives N input digital signals (x[0~7]), and performs operations on the N digital signals to generate N/2 first temporary signals (p[0~3]). Where N is a positive integer of a multiple of four. For convenience of explanation, in the specification and the drawings, N is 8 to be described.

The second operation unit 120 is connected to the first operation unit 110 to perform an arrangement operation on the N/2 first temporary signals (p[0~3]), and generates N/2 second temporary signals (z [0~3]).

The inverse discrete cosine second type (IDCT-II) unit 130 is connected to the second operation unit 120 to perform an operation on the N/2 second temporary signals (z[0~3]), and generate the input The digital signal (x[0~7]) corresponds to N/2 third temporary signals (Z[0~3]).

The third operation unit 140 is connected to the inverse discrete cosine second type (IDCT-II) unit 130 to perform an arrangement operation on the N/2 third temporary signals (Z[0~3]) to generate N/ 2 first output digital signals (X[0~3]).

The fourth operation unit 150 is connected to the third operation unit 140 to perform an arrangement operation on the N/2 first output digital signals (X[0~3]), and generate N second output digital signals (x) '[0~7]).

When the input of the system is the N input digit signals (x[0~7]), the N/2 first output digit signals (X[0~3]) output by the third operation unit are The N input digital signals (x[0~7]) correspond to discrete cosine signals.

When the input of the system is the first temporary signal (p[0~3]), the N second output digital signals (x'[0~7]) output by the fourth computing unit are Is an inverse discrete cosine signal corresponding to the first temporary signal (p[0~3]). At this time, the first temporary signal (p[0~3]) is input from the outside, not generated by the first operation unit 110.

The modified real discrete cosine transform (MDCT) conversion of the N real number input digital signals (x[0~7]) can be expressed by the formula (1):

According to the symmetry of cosine, formula (1) can be reduced to formula (2): among them, Suppose p[n]=z[n]+z[n+1], n is from N/2 to 1, and p[n] is returned to the formula (1) and can be reduced to z[n] and X[k The relational formula, the simplification process is shown in formula (4).

make And In the formula (4), the relationship between z[n] and X[k] can be rewritten into the formula (5); where Z[k] is assumed to be as shown in equation (6), and equation (4) can be simplified. A simpler formula is shown in equation (5);

Equation (6) is a type with the inverse discrete cosine type II (IDCT-II) as the core, according to C. Che-Hong, L. Bin-Da, and Y. Jar-Ferr, in Circuits and Systems II: Analog And Digital Signal Processing, IEEE Transactions on, vol. 50, pp. 38-45, 2003, published in the paper "Recursive architectures for realizing modified discrete cosine transform and its inverse", the sequence Z[k] Add the head and tail, and then apply the trigonometric function To simplify it, you can eliminate the odd number of k, and only calculate the value of the even term as shown in equation (8); similarly, subtract the head and tail of the sequence Z[k], and then apply the trigonometric function. To simplify it, you can eliminate the even term of k as shown in equation (9).

Hypothesis , the flow derivation represented by P _N/2-2 [k] in the formula (8) is as shown in the formula (10), and the flow derivation represented by Q _{N /2-2} [ k ] in the formula (9) is as the formula (11) is shown.

According to the above-mentioned derivation process, from the formula (1) to the formula (7), a schematic diagram of the modified discrete cosine transform (MDCT) is shown in FIG. 2, and FIG. 2 is an N/4 point modified discrete cosine transform ( A schematic diagram of MDCT), where N is 8 as an example. The modified discrete cosine transform (MDCT) inverse discrete cosine second type (IDCT-II) core architecture is represented by equation (10) to equation (11), and Figure 3 is the inverse discrete cosine second type (IDCT-II) The block diagram of core architecture 130 is comprised of adders 310, 311, 312, 320, 321, 322, 323, multipliers 313, 314, 315, 324, 325, 326, delay devices 316, 317, 327, 328.

The inverse modified discrete cosine transform (IMDCT) conversion of the N/2 point input is shown in equation (12). Suppose a new sequence y[n] is defined as shown in equations (13a) and (13b), and the original equation applied to the inverse modified discrete cosine transform (IMDCT) can be reduced to the fourth form of discrete cosine ( The type of DCT-IV) is shown in formula (14); and according to the above derivation flow, such as formula (4) to formula (7), formula (14) can be deduced to be inverse discrete cosine type 2 (IDCT- II) is the core diagram, Figure 4 is the N/4 point inverse Schematic diagram of good-form discrete cosine transform (IMDCT). The improved discrete cosine transform (MDCT) and inverse modified discrete cosine transform (IMDCT) difference in the modified discrete cosine transform (MDCT) need to be done first on the formula (3a) and the formula (3b), inverse modified discrete cosine transform ( IMDCT) needs to make the corresponding formula (13a) and formula (13b), so the intermediate derivation process can be shared, so according to FIG. 2 and FIG. 4, the recursive discrete cosine forward and inverse conversion system 100 of the present invention in FIG. 1 can be obtained. Schematic diagram.

Since the modified discrete cosine transform (MDCT) can be reduced to a discrete cosine fourth type (DCT-IV) by one pre-processing, as shown in equation (2), and discrete cosine fourth type (DCT-IV) The characteristic is that k and n are symmetric, and the result of the operation will be the same, and the purpose of this derivation is to make the pre-processing operation faster and more streamlined, and the core is unified by the inverse discrete cosine type II (IDCT-II). The type is implemented.

The process from the pre-processing of the modified discrete cosine transform (MDCT) to the inverse discrete cosine second type (IDCT-II) is shown in equations (1) through (7). The processing of this part requires N-1 Addition, and N/2 multiplication operations and N/2 multiplication coefficient usage.

As can be seen from the foregoing description, the first computing unit 110, the N input digital signals (x[0~7]), and the N/2 first temporary signals (p[0~3]) are described by the following formula: Where p[n] is the N/2 first temporary signals, and x[n] is the N input digital signals.

The second operation unit 120, the N/2 first temporary signals (p[0~3]) and the N/2 second temporary signals (z[0~3]) are described by the following formula: p[ n]=z[n]+z[n+1], for n=N/2-1 to 1, where z[n] is the N/2 second temporary signals (z[0~3]) , p[n] is the N/2 first temporary signals (p[0~3]).

The inverse discrete cosine second type (IDCT-II) unit 130, the N/2 second temporary signals (z[0~3]), and the N/2 third temporary signals (Z[0~3]) It is expressed by the following formula: Where Z[k] is the N/2 third temporary signals (Z[0~3]), and z[n] is the N/2 second temporary signals (z[0~3]).

The third operation unit 140, the N/2 third temporary signals (Z[0~3]), and the N/2 first output digital signals (X[0~3]) are expressed by the following formula: Where Z[k] is the N/2 third temporary signals (Z[0~3]), and X[k] is the N/2 first output digital signals (X[0~3]).

The fourth computing unit 150, the N/2 first output digital signals (X[0~3]), and the N second output digital signals (x[0~7]) are represented by the following formula: Where x'[n] is the N second output digit signals (x[0~7]), and X[k] is the N/2 first output digit signals (X[0~3]).

In order to increase the processing sequence of the recursive discrete cosine forward and reverse conversion system 100 of the present invention, a register group 160 may be added to the second operation unit 120 to enable the recursive discrete cosine forward and inverse conversion system. 100 can be parallelized, but the register set 160 can also be unused without affecting the functionality of the present invention.

5 is a schematic diagram of another embodiment of a recursive discrete cosine forward and reverse conversion system 500 of the present invention. It is N/8 points and is based on the inverse discrete cosine second type (IDCT-II), where N is a positive integer of a multiple of 8. The system 500 includes a first computing unit 510, a second computing unit 520, a third computing unit 530, a fourth computing unit 540, a first inverse discrete cosine second type (IDCT-II) unit 550, and a The second inverse discrete cosine second type (IDCT-II) unit 560, a fifth arithmetic unit 570, a sixth arithmetic unit 580, and a seventh arithmetic unit 590. In this embodiment The description is made with N being 16 , but this is not a limitation of the present invention, and those skilled in the art can expand to other numbers according to the technology of the present invention.

The first operation unit 510 receives N input digital signals (x[0~15]) to perform operations on the N digital signals, and generates N/2 first temporary signals (p[0~7]).

The second operation unit 520 is connected to the first operation unit 510 to perform an arrangement operation on the N/2 first temporary signals (p[0~7]), and generates N/2 second temporary signals (z [0~7]).

The third operation unit 530 is connected to the second operation unit 520 to perform an operation on the N/2 second temporary signals (z[0~7]) to generate N/4 third temporary signals (z _e [0~3]) and N/4 fourth temporary signals (z _o [0~3]).

The fourth operation unit 540 is connected to the third operation unit 530 to perform an operation on the N/4 fourth temporary signals (z _o [0~3]) to generate N/4 fifth temporary signals (z _o [n] ⁽¹⁾ ).

The first inverse discrete cosine second type (IDCT-II) unit 550 is connected to the third operation unit 530 to perform an operation on the N/4 third temporary signals (z _e [0~3]) to generate N/4 sixth temporary signals (Z _e [K]).

The second inverse discrete cosine second type (IDCT-II) unit 560 is connected to the fourth arithmetic unit 540 to perform an operation on the N/4 fifth temporary signals (z _o [n] ⁽¹⁾ ), and Generate N/4 seventh temporary signals (Z _o [K] ⁽¹⁾ ).

The fifth arithmetic unit 570 is connected to the second inverse discrete cosine second type (IDCT-II) unit 560 to perform an operation on the N/4 seventh temporary signals (Z _o [K] ⁽¹⁾ ), and Generate N/4 eighth temporary signals (Z _o [K]).

The sixth arithmetic unit 580 is connected to the first inverse discrete cosine second type (IDCT-II) unit and the fifth arithmetic unit 570 to the N/4 sixth temporary signals (Z _e [K]) and The N/4 eighth temporary signals (Z _o [K]) perform an operation to generate N/2 first output signals (X[K]).

The seventh operation unit 590 is connected to the sixth operation unit 580 to perform an operation on the N/2 first output signals (X[K]) to generate N second output signals (x'[n]) .

When the input of the system is the N input digit signals (x[0~15]), the N/2 first output signals (X[K]) output by the sixth operation unit 580 are associated with the N Enter the discrete cosine signal corresponding to the digital signal (x[0~15]).

When the input of the system is the first temporary signal (p[0~7]), the N second output digit signals (x'[0~15]) output by the seventh operation unit 590 are The inverse temporary cosine signal corresponding to the first temporary signal (p[0~7]). At this time, the first temporary signal (p[0~7]) is input from the outside, not generated by the first operation unit 510.

According to formula (5), formula (6), and formula (7), the odd and even splits of n in Z[k] can be discussed as follows:

When n is an even number (n=2n), substituting into Z[k] equation (6) gives the result as in equation (15). From equation (15), it can be clearly seen that Z _e [k] is an inverse discrete cosine second type (IDCT-II) type, in which it can be found that when k=0 to k=N/4-1, Ze[k] ]=Ze[N/2-1-k], so directly applying the inverse discrete cosine second type (IDCT-II) architecture formula (6) to formula (9), we can get the formulas (16) and (17) result. Where PN/4-2[k] and QN/4-1[k] are as shown in equations (10) and (11).

among, , (15)

When n is an odd number (n=2n+1) and substituted into Z[k] equation (6), the result of equation (18) can be obtained. It can be found that equation (18) is the fourth type of inverse discrete cosine (IDCT-IV). The type can be reduced to the inverse discrete cosine second type (IDCT-II) by inverse discrete cosine fourth type (IDCT-IV). Suppose z _o [n]=z _o [n] ⁽¹⁾ +z _o [n+1] ⁽¹⁾ Substituting into equation (18), the derivation process and result are as shown in equation (19).

among, , (18)

Suppose z _o [N/4] ⁽¹⁾ =0 and And substituting back into the formula (19), the relationship between z _o [n] ⁽¹⁾ and Z _o [k] can be rewritten into the formula (10), where Z _o [k] is assumed to be as shown in the formula (12). The simpler formula that can be reduced to is as follows:

It can be clearly seen that the formula (21) is the inverse discrete cosine second type (IDCT-II) type, on the other hand, it can be found that when k=0 to k=N/4-1, Zo[k](1) =Zo[N/2-1-k], so the result of formula (23) and formula (24) can be obtained by directly applying the inverse discrete cosine second type (IDCT-II) architecture formula (6) to formula (9). . Wherein P _N/4-2 [k] and Q _N/4-1 [k] are as shown in equations (10) and (11).

According to the above-mentioned derivation process formulas (15) to (14), a schematic diagram of the N/8 point modified discrete cosine transform (MDCT) is shown in Fig. 6, where equation (16), formula (17), and formula (23), formula (24) constitutes the inverse discrete cosine second type (IDCT-II) core architecture, and FIG. 7 is a block diagram of the inverse discrete cosine second type (IDCT-II) core architecture 550, 560 of the present invention, which is added by The units are 510, 511, 512, 520, 521, 522, 523, multipliers 513, 514, 515, 524, 525, 526, delay devices 516, 517, 527, 528, and register sets 518, 529.

As shown in FIG. 7, the Data Throughput Per Transformation (DTPT) is 4 and 8, and the operation speed is (N ² /64 + N / 4) cycles.

The improved discrete cosine transform (IMDCT) equation for the N/2 point input can be reduced to the discrete cosine fourth type (DCT-IV) type, as shown in equations (12) through (14). 14) Derivation into inverse discrete The second type of string (IDCT-II) is a schematic diagram of the core N/8 point inverse modified discrete cosine transform (IMDCT), and FIG. 8 is the N/8 point of the present invention with the inverse discrete cosine second type (IDCT-II) as the core. Schematic diagram of inverse modified discrete cosine transform (IMDCT). Since the modified discrete cosine transform (MDCT) and the inverse modified discrete cosine transform (IMDCT) can be decomposed into the discrete cosine fourth type (DCT-IV) type equation, the difference is that the modified discrete cosine transform (MDCT) goes through The pre-processed bifurcation formula (3a) and formula (3b), inverse modified discrete cosine transform (IMDCT) require post-processing data mapping formula (13a) and formula (13b), so a common architecture can be used to calculate the improved type. Discrete cosine transform (MDCT) and inverse modified discrete cosine transform (IMDCT), the schematic diagram of the recursive discrete cosine forward and inverse transform system 500 of the present invention in FIG. 5 can be obtained according to FIG. 6 and FIG.

As can be seen from the foregoing description, the first computing unit 510, the N input digital signals (x[0~15]), and the N/2 first temporary signals (p[0~7]) are described by the following formula: Where p[n] is the N/2 first temporary signals, and x[n] is the N input digital signals.

The second operation unit 520, the N/2 first temporary signals (p[0~7]) and the N/2 second temporary signals (z[0~7]) are described by the following formula: p[ n]=z[n]+z[n+1],for n=N/2-1 to 1, Where z[n] is the N/2 second temporary signals (z[0~7]), and p[n] is the N/2 first temporary signals (p[0~7]).

The third operation unit 530, the N/2 second temporary signals (z[0~7]), the N/4 third temporary signals (z _e [0~3]), and the N/4th The four temporary signals (zo[0~3]) are expressed by the following formula: Where z[n] is the N/2 second temporary signals (z[0~7]), and z _e [n] is the N/4 third temporary signals (z _e [0~3]), z _o [n] is the N/4 fourth temporary signals (z _o [0~3]).

The fourth operation unit 540, the N/4 fourth temporary signals (z _o [0~3]), and the N/4 fifth temporary signals (z _o [n] ⁽¹⁾ ) are based on the following formula Representation: z _o [n]=z _o [n] ⁽¹⁾ +z _o [n+1] ⁽¹⁾ , where z _o [n] is the N/4th fourth temporary signal (z _o [0 ~3]), z _o [n] ^{(1) is} the N/4 fifth temporary signals (z _o [n] ⁽¹⁾ ).

The first inverse discrete cosine second type (IDCT-II) unit 550, the N/4 third temporary signals (z _e [0~3]), and the N/4 sixth temporary signals (Z _e [K ]) is expressed by the following formula: Where z _e [n] is the N/4 third temporary signals (z _e [0~3]), and Z _e [K] is the N/4 sixth temporary signals (Z _e [K]).

The second inverse discrete cosine second type (IDCT-II) unit 560, the N/4 fifth temporary signals (z _o [n] ⁽¹⁾ ) and the N/4 seventh temporary signals (Z _o [ K] ⁽¹⁾ ) is expressed by the following formula: Where Z _o [K] ^{(1) is} the N/4th seventh temporary signal (Z _o [K] ⁽¹⁾ ), z _o [n] ^{(1) is} the N/4th fifth temporary signal ( z _o [n] ⁽¹⁾ ).

The fifth arithmetic unit 570, the N/4 seventh temporary signals (Z _o [K] ⁽¹⁾ ), and the N/4 eighth temporary signals (Z _o [K]) are expressed by the following formula: Among them, Z _o [K] is the N/4 eighth temporary signals (Z _o [K]), and Z _o [K] ^{(1) is} the N/4 seventh temporary signals (Z _o [K] ^{( 1)} ).

The sixth arithmetic unit 580, the N/4 sixth temporary signals (Z _e [K]), the N/4 eighth temporary signals (Z _o [K]), and the N/2 first output signals (X[K]) is expressed by the following formula: Where X[K] is the N/2 first output signals (X[K]), Z[K] is the N/4 sixth temporary signals (Z _e [K]) and the N/4 The combination of the eighth temporary signal (Z _o [K]).

The seventh operation unit 590, the N/2 first output signals (X[K]), and the N second output signals (x'[n]) are expressed by the following formula: Where x'[n] is the N second output digit signals (x'[0~15]), and X[k] is the N/2 first output digit signals (X[0~7]).

The present invention proposes a system based on inverse discrete cosine second type (IDCT-II) as a core, fast and common architecture for improved discrete cosine transform (MDCT) and inverse modified discrete cosine transform (IMDCT) conversion, with the aim of reducing digital programming. Hardware implementation cost of modified discrete cosine transform (MDCT) and inverse modified discrete cosine transform (IMDCT) on the decoder (codec) platform.

It can be seen from Fig. 5 that the preprocessing of this part requires N-1 addition operations, and N/2 multiplication operations and the usage of N/2 multiplication coefficients, and then according to the oddity of n in Z[k] Even discussed separately, deduced into two groups with the inverse discrete cosine second type (IDCT-II) as the core, the preprocessing of this part requires N/4-1 addition operations, and N/4 multiplication operations and N/ 4 multiplication factor usage. The core part of Figure 7 is the two types of inverse discrete cosine second type (IDCT-II). The computational complexity requires N/2+3 addition operations and N/4+2 multiplication operations to output two. The result of the pen is calculated by a total of N/8 operations, and the core part uses 3*N/8 multiplication coefficients.

Tables 4.1 and 4.2 show the additive usage of each method, and illustrate the modified discrete cosine transform (MDCT) and the inverse modified discrete cosine transform (IMDCT). At the same time, Tables 4.3 and 4.4 are the multiplications of each method, also The modified discrete cosine transform (MDCT) and inverse modified discrete cosine transform (IMDCT) are described separately. Each table is separately counted for Pre-/Post-processing, Recursive kernel, Total, and last block, and other methods are counted based on the technology of the present invention. An example of a percentage of the additional amount of computation (Increase (%)).

It can be known from the previous introduction that for the modified discrete cosine transform (MDCT) method, the preprocessing of the L.Lin et al. method requires N addition operations and the core needs to use 3*N ² /8+N/2 For addition, the pre-processing of Lei et al. requires 5*N/4-1 additions and the core requires 3*N ² /8 additions. The pre-processing of Lei et al. requires 7*N/ 4-2 additions and the core needs to use 3*N ² /16 addition operations. The pre-processing of the technique of the present invention requires the addition of 5*N/4-2, and the core needs to use N ² /8+3 *N/4 addition operations.

For the modified discrete cosine transform (MDCT) method, the pre-processing of the above method reduces N/2 addition operations and the addition amount of the core part is the same. Table 4.1 and Table 4.2 are for 2048 points. For comparison purposes.

It can be seen from Tables 4.1 and 4.2 that the overall additive total computation of the present invention is minimal, compared to the method proposed by Lei et al. in modified discrete cosine transform (MDCT) and inverse modified discrete cosine transform (IMDCT). Both sides reduced the use of addition by 49.52% and 49.61% respectively. Compared with L. Li et al., the present invention reduces the amount of addition used by 198.26%. It can be seen from Table 4.2 that Lei et al. and the technique of the present invention are better choices.

For the modified discrete cosine transform (MDCT) method, the preprocessing of the L.Lin et al. method requires N multiplication operations, and its core needs to use N ² /8+N/2 multiplication operations. The preprocessing of the Lei et al. method requires N/2 multiplication operations, while the core needs to use N ² /8+N/2 multiplication operations. The preprocessing of the Lei et al. method requires 3*N/4 multiplications. The operation requires the core to use N ² /16+N/2 multiplication operations. The pre-processing of the present invention requires the use of 3*N/4 multiplication operations, while the core requires N ² /16+N/2 multiplication operations.

For the modified discrete cosine transform (MDCT) method, the preprocessing of the foregoing method and the multiplication of the core part are the same, and Tables 4.3 and 4.4 are based on 2048 points.

As can be seen in Tables 4.3 and 4.4, the total multiplication amount of the technique of the present invention and Lei et al. is the same. Other methods have nearly doubled or more multiplication usage than the present invention.

Observed from the statistical data in Tables 4.1 to 4.4, the improved discrete cosine transform (MDCT) and inverse modified discrete cosine transform (IMDCT) methods of the present invention are compared with other recent papers in terms of computational complexity. A small number of addition and multiplication operations are used, which also means improved differential discrete cosine transform (MDCT) and inverse modified discrete cosine transform (IMDCT) for the same number of points, and the method of the present invention can obtain operations more quickly and efficiently. result.

Secondly, for the comparison of the multiplication coefficient usage of each method, for the improved discrete cosine transform (MDCT) method, the preprocessing of the L.Lin et al. method requires the use of N multiplication coefficients, and the core needs to be used. 3*N/4 multiplication coefficient usage, Lei et al.'s pre-processing requires N/2 multiplication coefficient usage, while the core needs to use N multiplication coefficient usage, and Lei et al.'s pre-processing needs to use 3 *N/4 multiplication coefficient usage, and the core needs to use N/2 multiplication coefficient usage. The preprocessing of the present technology requires 3*N/4 multiplication coefficient usage, and the core needs to use 3*N/ 8 multiplication factor usage. For the modified discrete cosine transform (MDCT) method, the preprocessing of the foregoing method and the multiplication coefficient usage of the core portion are the same.

Tables 4.5 and 4.6 are the multiplicative coefficient usage analysis of each method, which are modified discrete cosine transform (MDCT) and inverse modified discrete cosine transform. Change (IMDCT) multiplication factor usage analysis. The method proposed by Lai et al. in Table 4.5 uses the least amount of memory to store the coefficients of the operation, which is the characteristic of the proposed method; in addition to Lai et al., Lei et al. is 11 more than the technique of the present invention. The multiplication factor usage of %, the other method is more than 30% of the multiplication factor usage.

From equation (1), it can be seen that N memory is needed to store the input N data x[n], and equation (2) is used to simplify the symmetry of the modified discrete cosine transform (MDCT). The data p[n] only needs N/2 memory to store the operation result. Since the x[n] serialization is simply p[n], it is no longer used, so it can be written back to the memory location where the original input is stored. And the remaining N/2 memory can be used as the location of the operation after the temporary storage, to achieve the purpose of alternate use and save the need for additional memory. In the operation of equation (4), p[n] is serialized into a z[n] sequence, and z[n] in equation (5) also uses N/2 memories to store the operation result. In equations (15) and (18), z[n] is serialized into two sequences z _e [n] and z _o [n], respectively, requiring N/4 memory to store the operation result, z The operation data of _e [n] is directly fed into the core for operation, and the sequence z _o [n] needs to be pre-processed to simplify the z _o [n] ⁽¹⁾ sequence, as shown in equation (19). z _o [n] ^{(1) The} sequence requires N/4 memory to store the result of the operation and feed it to the core for operation. The results of the two core outputs require N/4 memory to store the operation results to store the two sequences Z _e [k] and Z _o [k] ⁽¹⁾ . Finally, after the post-processing, the final N/2 pen data is output. It can be known that, according to such evaluation results, the present invention can store data of all calculation processes by only requiring N memories at most.

According to this evaluation method, it can be known that L. Li et al. and Lei et al. only need N memories to store data of all calculation processes. The derivation process of inverse modified discrete cosine transform (IMDCT) can be found by L.Li et al. and Lei et al. and the method of the present invention can store all of only N memory. Information on the calculation process.

In summary, the method of the present invention has three main features.

1. Low computational complexity: According to the statistical data of Tables 4.1 to 4.4, the method of the present invention has the least amount of pre-processing and core computation compared with other methods.

2. A small amount of multiplication factor usage: According to the statistical data of Tables 4.5 to 4.6, the method of the present invention uses the multiplicative coefficient used in comparison with other methods in addition to Lai et al.

3. High-performance data calculation: According to the statistical data of Tables 4.7 to 4.8, the DTPT of the method of the present invention is the most and the calculation cycle is the shortest.

From the above, it can be seen that the present invention is extremely useful in terms of its purpose, means, and efficacy, both of which are different from those of the prior art. It should be noted that the various embodiments described above are merely illustrative for ease of explanation, and the scope of the invention is intended to be limited by the scope of the claims.

100‧‧‧Return-type discrete cosine forward and reverse conversion systems

110‧‧‧First arithmetic unit

120‧‧‧Second arithmetic unit

130‧‧‧Inverse Discrete Cosine Type II (IDCT-II) Unit

140‧‧‧ third arithmetic unit

150‧‧‧ fourth arithmetic unit

310,311,312,320,321,322,323‧‧‧Adder

313,314,315,324,325,326‧‧‧multiplier

316,317,327,328‧‧‧ delay device

500‧‧‧Return-type discrete cosine forward and reverse conversion systems

510‧‧‧First arithmetic unit

520‧‧‧Second arithmetic unit

530‧‧‧ third arithmetic unit

540‧‧‧ fourth arithmetic unit

550‧‧‧First Inverse Discrete Cosine Type II (IDCT-II) Unit

560‧‧‧Second Inverse Discrete Cosine Type II (IDCT-II) unit

570‧‧‧ fifth arithmetic unit

580‧‧‧ sixth arithmetic unit

590‧‧‧ seventh arithmetic unit

510, 511, 512, 520, 521, 522, 523 ‧ ‧ adders

513,514,515,524,525,526‧‧‧multiplier

516,517,527,528‧‧‧ delay device

518, 529‧‧ ‧ register group

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a schematic illustration of one embodiment of a recursive discrete cosine forward and reverse conversion system of the present invention.

2 is a schematic diagram of an N/4 point modified discrete cosine transform (MDCT) of the present invention.

3 is a block diagram of the discrete sinusoidal second type (IDCT-II) core architecture of the present invention.

4 is a schematic diagram of an N/4-point inverse modified discrete cosine transform (IMDCT) of the present invention.

Figure 5 is a schematic illustration of another embodiment of a system for recursive discrete cosine forward and inverse conversion of the present invention.

Figure 6 is a schematic illustration of an N/8 point modified discrete cosine transform (MDCT) of the present invention.

7 is a block diagram of the core architecture of the inverse discrete cosine second type (IDCT-II) of the present invention.

Figure 8 is a schematic illustration of an N/8 point inverse modified discrete cosine transform (IMDCT) of the present invention.

100‧‧‧Return-type discrete cosine forward and reverse conversion systems

110‧‧‧First arithmetic unit

120‧‧‧Second arithmetic unit

130‧‧‧Anti-discrete cosine second type unit

140‧‧‧ third arithmetic unit

150‧‧‧ fourth arithmetic unit

Claims (11)

A recursive discrete cosine forward and inverse conversion system, which is based on an inverse discrete cosine second type (IDCT-II), the system comprising: a first arithmetic unit that receives N input digital signals, The N digital signals perform an operation to generate N/2 first temporary signals, wherein N is a positive integer of a multiple of 4; a second arithmetic unit is connected to the first operational unit, and the N/2 A temporary signal performs an arrangement operation to generate N/2 second temporary signals; an inverse discrete cosine second type (IDCT-II) unit is connected to the second arithmetic unit, and the N/2 second temporary signals are Performing an operation to generate N/2 third temporary signals corresponding to the input digital signal; a third arithmetic unit connected to the inverse discrete cosine second type (IDCT-II) unit, the N/2 The third temporary signal performs an arrangement operation to generate N/2 first output digital signals; and a fourth arithmetic unit is coupled to the third operational unit to perform an arrangement operation on the N/2 first output digital signals to Generating N second output digital signals; wherein, when the input of the system is the N When the digital signal is input, the N/2 first output digital signals output by the third computing unit are discrete cosine signals corresponding to the N input digital signals. When the input of the system is the first temporary signal, The N second output digit signals output by the fourth computing unit are inverse discrete cosine signals corresponding to the first temporary signal. The system of recursive discrete cosine forward and reverse conversion according to claim 1, wherein the first operation unit, the N input digit signals, and the N/2 first temporary signals are according to the following formula description: Where p[n] is the N/2 first temporary signals, and x[n] is the N input digital signals. The system of recursive discrete cosine forward and reverse conversion according to claim 2, wherein the second computing unit, the N/2 first temporary signals, and the N/2 second temporary signal systems It is described by the following formula: p[n]=z[n]+z[n+1], for n=N/2-1 to 1, where z[n] is the N/2 second temporary signals, p[n] is the N/2 first temporary signals. The system of recursive discrete cosine forward and reverse conversion according to claim 3, wherein the inverse discrete cosine second type (IDCT-II) unit, the N/2 second temporary signals, and the N The /2 third temporary signals are expressed by the following formula: Where Z[k] is the N/2 third temporary signals, and z[n] is the N/2 second temporary signals. The system of recursive discrete cosine forward and reverse conversion according to claim 4, wherein the third operation unit, the N/2 third temporary signals, and the N/2 first output digital signals It is expressed by the following formula: Where Z[k] is the N/2 third temporary signals, and X[k] is the N/2 first output digital signals. The system of recursive discrete cosine forward and reverse conversion according to claim 5, wherein the fourth operation unit, the N/2 first output digital signals, and the N second output digital signals are Expressed by the following formula: Where x'[n] is the N second output digit signals, and X[k] is the N/2 first output digit signals. A recursive discrete cosine forward and inverse conversion system, which is based on an inverse discrete cosine second type (IDCT-II), the system comprising: a first arithmetic unit that receives N input digital signals, Performing operations on the N digital signals to generate N/2 first temporary signals, where N is a positive integer of a multiple of 8; a second arithmetic unit is coupled to the first operational unit, to the N/2 Performing an arrangement operation on a temporary signal to generate N/2 second temporary signals; a third computing unit, connected to the second computing unit, performing operations on the N/2 second temporary signals to generate N/4 third temporary signals and N/4 fourth temporary signals; The operation unit is connected to the third operation unit, and performs an operation on the N/4 fourth temporary signals to generate N/4 fifth temporary signals; a first inverse discrete cosine second type (IDCT-II) unit And connecting to the third operation unit, performing an operation on the N/4 third temporary signals to generate N/4 sixth temporary signals; and a second inverse discrete cosine second type (IDCT-II) unit, connecting Up to the fourth computing unit, performing an operation on the N/4 fifth temporary signals to generate N/4 seventh temporary signals; and a fifth arithmetic unit connected to the second inverse discrete cosine second type (IDCT) -II) unit, performing an operation on the N/4 seventh temporary signals to generate N/4 eighth temporary signals; a sixth arithmetic unit connected to the first inverse discrete cosine second type (IDCT-II And the fifth arithmetic unit performs an operation on the N/4 sixth temporary signals and the N/4 eighth temporary signals to generate N/2 An output signal; and a seventh arithmetic unit connected to the sixth operational unit, performing operations on the N/2 first output signals to generate N second output signals; wherein, when the input of the system is the N When the digital signal is input, the N/2 first output signals output by the sixth computing unit are discrete cosine signals corresponding to the N input digital signals. When the input of the system is the first temporary signal, The N second inputs output by the seventh computing unit The digital signal is an inverse discrete cosine signal corresponding to the first temporary signal. The system of recursive discrete cosine forward and reverse conversion according to claim 7 , wherein the first operation unit, the N input digit signals, and the N/2 first temporary signals are according to the following formula description: Where p[n] is the N/2 first temporary signals, and x[n] is the N input digital signals. The recursive discrete cosine forward and reverse conversion system of claim 8, wherein the second computing unit, the N/2 first temporary signals, and the N/2 second temporary signal systems It is described by the following formula: p[n]=z[n]+z[n+1], for n=N/2-1 to 1, where z[n] is the N/2 second temporary signals, p[n] is the N/2 first temporary signals; the third computing unit, the N/2 second temporary signals, the N/4 third temporary signals, and the N/4 fourth temporary signals It is expressed by the following formula: Where z[n] is the N/2 second temporary signals, z _e [n] is the N/4 third temporary signals, and z _o [n] is the N/4 fourth temporary signals; The fourth arithmetic unit, the N/4 fourth temporary signals, and the N/4 fifth temporary signals are represented by the following formula: z _o [n]=z _o [n] ⁽¹⁾ +z _o [n+ 1] ⁽¹⁾ , where z _o [n] is the N/4 fourth temporary signals, and z _o [n] ^{(1) is} the N/4 fifth temporary signals. The system of recursive discrete cosine forward and reverse conversion according to claim 9, wherein the first inverse discrete cosine second type (IDCT-II) unit, the N/4 third temporary signals and The N/4 sixth temporary signals are expressed by the following formula: Where z _e [n] is the N/4 third temporary signals, Z _e [K] is the N/4 sixth temporary signals; the second inverse discrete cosine second type (IDCT-II) unit, The N/4 fifth temporary signals and the N/4 seventh temporary signals are expressed by the following formula: Among them, Z _o [K] ^{(1) is} the N/4 seventh temporary signals, and z _o [n] ^{(1) is} the N/4 fifth temporary signals. The system of recursive discrete cosine forward and reverse conversion according to claim 10, wherein the fifth arithmetic unit, the N/4 seventh temporary signals, and the N/4 eighth temporary signal system Expressed by the following formula: Where Z _o [K] is the N/4 eighth temporary signals, Z _o [K] ^{(1) is} the N/4 seventh temporary signals; the sixth arithmetic unit, the N/4 sixth The temporary signal, the N/4 eighth temporary signals, and the N/2 first output signals are expressed by the following formula: Wherein, X[K] is the N/2 first output signals, and Z[K] is a combination of the N/4 sixth temporary signals and the N/4 eighth temporary signals; the seventh arithmetic unit, The N/2 first output signals and the N second output signals are represented by the following formula: Where x'[n] is the N second output digit signals, and X[k] is the N/2 first output digit signals.