TWI411999B - Scan signal generation circuit - Google Patents

Abstract

A scan signal generation circuit includes plural stages of scan units, for generating scan signals for a pixel circuit. Each scan unit includes a shift circuit and an NOR gate. The shift circuit transmits a shifted signal and generates a scan signal with double pulse width. The NOR gate receives the scan signal generated by the shift circuit and the scan signal generated by the preceding stage of the scan unit so as to generate a driving signal.

Description

Scan signal generation circuit

The present invention relates to a scanning signal generating circuit, and more particularly to a scanning signal generating circuit capable of generating a driving signal of three times the pulse width.

Please refer to FIG. 1 , which is a schematic diagram of a display panel of a prior art organic light emitting diode (OLED). The display panel 10 includes a material drive 11, a scan driver 12, and a display array 13. The data driver 11 controls the data lines DL ₁ to DL _n , and the scan driver 12 controls the scan lines SL ₁ to SL _m . The display array 13 is formed by interleaving the data lines DL ₁ to DL _n and the scan lines SL ₁ to SL _m , and each of the interleaved data lines and scan lines form a display unit, for example, the data line DL ₁ and the scan line SL ₁ The display unit 14 is formed. As shown in FIG. 1, the equivalent circuit of the display unit 14 (the other display units are also the same) includes a switching transistor T11, a storage capacitor Cst, a driving transistor T12, and an organic light emitting diode D1, wherein the switching transistor T11 is N. The type transistor, the driving transistor T12 is a P-type transistor.

The scan driver 12 sequentially sends the scan signals to the scan lines SL ₁ to SL _m so that only the switch transistors of all the display units in one column are turned on at the same instant, and the switch transistors of all the display units on the other columns are turned off. The data driver 11 sends the corresponding video signal (grayscale value) to the display unit of one column via the data lines DL ₁ to DL _n according to the image data to be displayed. For example, when SL ₁ the scan driver 12 sends a scanning signal to the scan lines, the display unit switch transistor T11 is turned on 14, the data driver 11 through data line DL ₁ corresponding to the pixel data transmitted to the display unit 14, The voltage of the pixel data is stored by the storage capacitor Cst. The driving transistor T12 drives the organic light emitting diode D1 according to the voltage stored by the storage capacitor Cst to provide the driving current Isd1.

Since the organic light emitting diode D1 is a current driving element, the value of the driving current Isd1 determines the brightness of the light generated by the organic light emitting diode D1. The driving current Isd1 is the source current of the driving transistor T12, which can be expressed as Isd1=k(Vsg−|Vth|) ² , where Isd1 represents the value of the driving current Isd1, k represents the conduction parameter of the driving transistor T12, and Vsg represents the driving. The value of the source-gate voltage Vsg of the transistor T12, and Vth represents the threshold voltage value of the driving transistor T12.

However, due to the process factors of the thin film transistor, the difference in electrical characteristics of the driving transistors of the respective regions in the display array 13, that is, the difference in the threshold voltage values of the driving transistors. Therefore, when the plurality of display units of different regions receive the pixel data having the same voltage, the values of the driving currents supplied to the organic light-emitting diodes are inconsistent in the display units due to the difference in the threshold voltages of the driving transistors. The brightness generated by the organic light emitting diode is different, and the display panel 10 displays an uneven picture.

Accordingly, it is an object of the present invention to provide a scanning signal generating circuit for a pixel circuit of an organic light emitting diode having a threshold voltage compensation.

The invention provides a scanning signal generating circuit comprising a plurality of scanning units for generating a scanning signal of a pixel circuit, wherein each scanning unit comprises a shift circuit and an inverse gate. The shift circuit is configured to transmit a shift signal and generate a scan signal having a double pulse width. The anti-gate has a first input for receiving the scan signal generated by the shift circuit, a second input for receiving the scan signal generated by the scan unit of the previous stage, and an output for outputting a drive signal.

Please refer to FIG. 2, which is a schematic diagram of a pixel circuit of an organic light emitting diode with threshold voltage compensation. The pixel circuit includes six transistors M1 to M6, a storage capacitor Cst, and an organic light emitting diode D1. The transistors M1 and M3 are NMOS transistors, and the transistors M2, M4, M5, and M6 are PMOS transistors. The first end of the transistor M1 receives the pixel data Vdata, and the gate of the transistor M1 receives the scanning signal S(N). The gate of the transistor M2 is electrically connected to the gate of the transistor M1, and the second end of the transistor M2 is electrically connected to the second end of the transistor M1. The first end of the transistor M3 receives the reference voltage Vref1, the gate of the transistor M3 is electrically connected to the gate of the transistor M1, and the second end of the transistor M3 is electrically connected to the first end of the transistor M2. The first end of the storage capacitor Cst is electrically connected to the first end of the transistor M2. The first end of the transistor M4 is electrically connected to the second end of the storage capacitor Cst, and the gate of the transistor M4 is electrically connected to the second end of the transistor M1. The first end of the transistor M5 receives the power supply voltage VDD, the gate of the transistor M5 receives the control signal EM, and the second end of the transistor M5 is electrically connected to the first end of the transistor M4. The first end of the transistor M6 is electrically connected to the second end of the transistor M4, the gate of the transistor M6 receives the driving signal BP(N), and the second end of the transistor M6 receives the reference voltage Vref2. The first end of the organic light emitting diode D1 is electrically connected to the second end of the transistor M4, and the second end of the organic light emitting diode D1 receives the power supply voltage VSS.

Please refer to FIG. 3, which is a schematic diagram of the signal waveform of the pixel circuit of FIG. At time t1, the scanning signal S(N) is at a low level, so the transistors M3, M1 are turned off, the transistor M2 is turned on; the control signal EM is at a low level, so the transistor M5 is turned on; the driving signal BP(N) is The low level, so the transistor M6 is turned on, and the connection of the pixel circuit is the same as that of the display unit of Fig. 1. At time t2, the scanning signal S(N) is at a high level, so the transistors M3 and M1 are turned on, the transistor M2 is turned off; the control signal EM is at a low level, so the transistor M5 is turned on; the driving signal BP(N) is Low level, so the transistor M6 is turned on. Therefore, the first end of the storage capacitor Cst is the voltage Vref1, the second end of the storage capacitor Cst is the voltage VDD, the pixel data Vdata is transmitted to the control terminal of the transistor M4, and the second end of the transistor M4 is the reference voltage Vref2. At time t3, the control signal EM is converted to a low level by the low level, so the transistor M5 will be turned off. Therefore, the second end of the storage capacitor Cst will be discharged from the voltage VDD to the voltage level of the pixel data Vdata plus the threshold voltage Vth of the transistor M4 (Vdata+|Vth|). At time t4, the scanning signal S(N) is at a low level, so the transistors M3, M1 are turned off, the transistor M2 is turned on; the control signal EM is converted from the high level to the low level, so the transistor M5 will be turned on; The signal BP(N) is at a high level, so the transistor M6 is turned off. Therefore, a varying voltage ΔV = VDD - (Vdata + | Vth |) is generated. The first end of the storage capacitor Cst is electrically connected to the control terminal of the transistor M4, and the voltage is Vref1+ΔV. The second end of the storage capacitor Cst is electrically connected to the first end of the transistor M4, and the voltage is VDD. The voltage across the two ends of the storage capacitor Cst is Vsg = VDD - (Vref1 + ΔV), so the current flowing through the transistor M4 can be expressed as Id1 = k (Vsg - | Vth |) ² = k (Vdata - Vref1) ² , wherein k is the conductive parameter of the transistor M4. Therefore, the current of the organic light-emitting diode D1 is independent of the threshold voltage Vth, and is determined by the pixel data Vdata.

Please refer to FIG. 4, which is a schematic diagram of the scanning signal generating circuit of the present invention. The pixel circuit of Fig. 2 can compensate for the influence of the threshold voltage on the current of the organic light emitting diode, but the pixel circuit of Fig. 2 requires the scanning signal S(N) of twice the pulse width and the driving signal BP of the triple pulse width. (N). Therefore, the scan signal generating circuit of the present invention comprises a plurality of scanning units, each of which includes a shift circuit and a NOR gate. The shift circuit receives the shift signal Si(N-1) generated by the scanning unit of the first stage, wherein the shift circuit of the first stage scanning unit receives the start signal VST to generate the shift signal Si(N). The scan signal S(N) having a double pulse width can be generated according to the signal of the node H of the shift circuit. The first input terminal of the inverse gate G2 receives the scan signal S(N) generated by the shift circuit, and the second input terminal of the reverse gate G2 receives the scan signal S(N-1) generated by the upper-level scan unit, or the gate The output of G2 generates a drive signal BP. The shift circuit includes three inverters B1 to B3, eight transistors T1 to T8, and a transmission gate G1. The input of the inverter B1 receives the shift signal Si(N-1). The first end of the transistor T1 is electrically connected to the output end of the inverter B1, and the gate of the transistor T1 is electrically connected to the input end of the inverter B1. The first end of the transistor T2 is electrically connected to the second end of the transistor T1, and the gate of the transistor T2 is electrically connected to the gate of the transistor T1. The first end of the transistor T3 receives the clock signal CK/XCK, and the gate of the transistor T3 is electrically connected to the second end of the transistor T2. The first end of the transistor T4 is electrically connected to the second end of the transistor T1, the gate of the transistor T4 is electrically connected to the second end of the transistor T3, and the second end of the transistor T4 is electrically connected to the transistor. The second end of T3. The input end of the inverter B2 is electrically connected to the second end of the transistor T4, and the output end of the inverter B2 outputs the shift signal Si(N). The first end of the transmission gate G1 is electrically connected to the output end of the inverter B2, the negative control terminal of the transmission gate G1 is electrically connected to the output end of the inverter B1, and the positive control terminal of the transmission gate G1 is electrically connected to the opposite end. The input of phase comparator B1. The first end of the transistor T5 is electrically connected to the second end of the transmission gate G1, the gate of the transistor T5 is electrically connected to the negative control end of the transmission gate G1, and the second end of the transistor T5 receives the low level voltage VGL. . The first end of the transistor T6 is electrically connected to the second end of the transistor T2, the gate of the transistor T6 is electrically connected to the second end of the transmission gate G1, and the second end of the transistor T6 is electrically connected to the transistor. The second end of T4. The first end of the transistor T7 is electrically connected to the second end of the transistor T6, and the gate of the transistor T7 is electrically connected to the second end of the transmission gate G1. The first end of the transistor T8 is electrically connected to the second end of the transistor T7, the gate of the transistor T8 is electrically connected to the second end of the transmission gate G1, and the second end of the transistor T8 receives the low level voltage VGL. . The input end of the inverter B3 is electrically connected to the second end of the transmission gate G1, and the output end of the inverter B3 outputs the scanning signal S(N). The output terminal of the inverter B2 is electrically connected to a first output buffer circuit, and the first output buffer circuit includes inverters B4 and B5 for outputting the shift signal Si(N). In addition, the scan signal generating circuit further includes a second output buffer circuit and a third output buffer circuit. The second output buffer circuit includes inverters B6 and B7 for outputting the scan signal S(N). The third output buffer circuit includes inverters B8 and B9 for outputting the driving signal BP(N).

Please refer to FIG. 5, which is a schematic diagram of the signal waveform of the scanning signal generating circuit of FIG. VST is the start signal, CK is the clock signal, and XCK is the inverted clock signal. The start signal VST input shift circuit generates a shift signal Si(1). Taking the first-level scanning unit (N=1) as an example, at time ta, the start signal VST is at a low level, which causes the transmission gate G1 to be turned off. At this time, the transistor T5 is turned on to make the node H be at a low level. The output signal of the bit signal Si(1) is at a high level, and the output of the scanning signal S(1) is at a high level. At the time tb, the start signal VST is at a high level, which causes the transmission gate G1 to be turned on, and the clock signal is turned on at this time. CK is high level, inverter B2 transmits output low level to transmission gate G1, so that node H gets low level. At this time, scanning signal S(1) is high level, and shift signal Si(1) is Low level. In the first scanning unit, the second terminal S(N-1) of the inverse gate G2 is floating, so the driving signal BP(1) is inverted from the scanning signal S(1). Taking the second-level scanning unit (N=2) as an example, at time tb, the shift signal Si(1) is at a low level, which causes the transmission gate G1 to be turned off. At this time, the transistor T5 is turned on to make the node H low. Bit, shift signal Si(2) output is high level, scan signal S(2) output is high level; at time tc, shift signal Si(1) is high level, which will make transmission gate G1 open At this time, the clock signal CK is at a high level, and the inverter B2 transmits the output low level to the transmission gate G1, so that the node H obtains a low level, and the output of the scanning signal S(2) is also at a high level. The signal Si(2) output is at a low level. The drive signal BP(2) is the output of the scan signal S(1) and the scan signal S(2) through the inverse gate G2. Therefore, after the second-stage scanning unit, the scanning signal S(N) generated by the shifting circuit and the scanning signal S(N-1) generated by the scanning unit of the previous stage can be driven by the triple pulse width via the inverse gate G2. Signal BP(N).

In summary, the scanning signal generating circuit of the present invention can generate a scanning signal of twice the pulse width and a driving signal of three times the pulse width required for the pixel circuit of the organic light emitting diode with threshold voltage compensation. The scan signal generating circuit includes a plurality of scanning units for generating a scanning signal of a pixel circuit. Each level of scanning unit includes a shift circuit and an inverse or gate. The shift circuit is configured to transmit a shift signal and generate a scan signal having a double pulse width. The inverse thyristor is configured to receive the scan signal generated by the shift circuit and the scan signal generated by the scan unit of the previous stage to output a drive signal having a pulse width of three times.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

10‧‧‧ display panel

11‧‧‧Data Drive

12‧‧‧ scan driver

13‧‧‧Display array

14‧‧‧Display unit

DL ₁ ~ DL _n ‧‧‧ data line

SL ₁ ~SL _m ‧‧‧ scan line

T11‧‧‧Switching transistor

T12‧‧‧ drive transistor

Cst‧‧‧ storage capacitor

D1‧‧‧Organic Luminescent Diode

M1~M6‧‧‧O crystal

T1~T8‧‧‧O crystal

B1~B9‧‧‧Inverter

Si(N)‧‧‧ Shift signal

S(N)‧‧‧ scan signal

G1‧‧‧Transmission gate

G2‧‧‧Anti-gate

BP(N)‧‧‧ drive signal

EM‧‧‧ control signal

VDD, VSS‧‧‧ power supply voltage

Vref1, Vref2‧‧‧ reference voltage

Vdata‧‧‧ pixel data

CK/XCK‧‧‧ clock signal

VGL‧‧‧ low level voltage

H‧‧‧ node

FIG. 1 is a schematic view of a display panel of a prior art organic light emitting diode.

Figure 2 is a schematic diagram of a pixel circuit of an organic light emitting diode with threshold voltage compensation.

Figure 3 is a schematic diagram of the signal waveform of the pixel circuit of Figure 2.

Figure 4 is a schematic diagram of the scanning signal generating circuit of the present invention.

Fig. 5 is a schematic diagram showing the signal waveform of the scanning signal generating circuit of Fig. 4.

T1~T8. . . Transistor

B1~B9. . . inverter

G1. . . Transmission gate

G2. . . Reverse or gate

Si(N). . . Shift signal

S(N). . . Scanning signal

BP(N). . . Drive signal

CK/XCK. . . Clock signal

VGL. . . Low level voltage

H. . . node

Claims (10)

A scanning signal generating circuit includes a plurality of scanning units for generating a scanning signal of a pixel circuit, wherein each scanning unit comprises: a shifting circuit for transmitting a shift signal and generating a pulse having twice a scan signal of a width; and a NOR gate having a first input for receiving the scan signal generated by the shift circuit, and a second input for receiving the scan signal generated by the scan unit of the previous stage, And an output terminal for outputting a driving signal. The scan signal generating circuit of claim 1, wherein the shift circuit comprises: a first inverter having an input for receiving a shift signal output by the scanning unit of the previous stage, and an output; a transistor having a first end electrically connected to the output end of the first inverter, a control end electrically connected to the input end of the first inverter, and a second end; a second electric The crystal has a first end electrically connected to the second end of the first transistor, a control end electrically connected to the control end of the first transistor, and a second end; a third transistor having a first end is configured to receive a clock signal, a control end is electrically connected to the second end of the second transistor, and a second end; a fourth transistor has a first end electrically connected to the a second end of the first transistor, a control end electrically connected to the second end of the third transistor, and a second end electrically connected to the second end of the third transistor; a second inversion The device has an input end electrically connected to the second end of the fourth transistor, and an output end The output gate has a first end electrically connected to the output end of the second inverter, and a negative control end is electrically connected to the output end of the first inverter, The positive control terminal is electrically connected to the input end of the first inverter, and a second end; a fifth transistor has a first end electrically connected to the second end of the transmission gate, and a control terminal is electrically And a second terminal for receiving a low level voltage; a sixth transistor having a first end electrically connected to the second end of the second transistor, a control terminal is electrically connected to the second end of the transmission gate, and a second end is electrically connected to the second end of the fourth transistor; a seventh transistor has a first end electrically connected to the a second end of the sixth transistor, a control end electrically connected to the second end of the transmission gate, and a second end; an eighth transistor having a first end electrically connected to the seventh transistor a second end, a control end is electrically connected to the second end of the first transmission gate, and a second end is used to receive the low level Voltage; and a third inverter having an input terminal electrically connected to the second end of the transmission gate, and an output terminal for outputting the scan signal. The scan signal generating circuit of claim 2, wherein the first transistor and the second transistor are PMOS transistors, and the third transistor to the eighth transistor are NMOS transistors. The scan signal generating circuit of claim 2, further comprising: a first output buffer circuit electrically connected to the output end of the second inverter for outputting the shift signal; and a second output buffer The circuit is electrically connected to the output end of the third inverter for outputting the scan signal. The scan signal generating circuit of claim 4, wherein the first output buffer circuit comprises: a fourth inverter having an input electrically connected to the output of the second inverter, and an output And a fifth inverter having an input electrically connected to the output of the fourth inverter, and an output for outputting the shift signal; and the second output buffer circuit includes: a six-inverter having an input electrically connected to the output of the third inverter and an output; and a seventh inverter having an input electrically coupled to the sixth inverter The output end and an output end are used to output the scan signal. The scan signal generating circuit of claim 1, further comprising: an output buffer circuit electrically connected to the inverse gate for outputting the driving signal. The scan signal generating circuit of claim 6, wherein the output buffer circuit comprises: an eighth inverter having an input electrically connected to the output of the inverse or gate, and an output; and a ninth The inverter has an input terminal electrically connected to the output end of the eighth inverter, and an output terminal for outputting the driving signal. The scan signal generating circuit of claim 1, wherein the drive signal has three pulse widths. The scanning signal generating circuit of claim 1, wherein the pixel circuit comprises: a first transistor having a first end for receiving a pixel data, a control terminal for receiving the scanning signal, and a a second end; a second transistor having a first end, a control end electrically connected to the control end of the first transistor, and a second end electrically connected to the second end of the first transistor a third transistor having a first terminal for receiving a first reference voltage, a control terminal electrically connected to the control terminal of the first transistor, and a second terminal electrically connected to the second transistor a first end of the crystal; a storage capacitor having a first end electrically connected to the first end of the second transistor, a second end; a fourth transistor having a first end electrically connected to the first end a second end of the storage capacitor, a control end electrically connected to the second end of the first transistor, and a second end; a fifth transistor having a first end for receiving a first power supply voltage, a control terminal is configured to receive a control signal, and a second terminal is electrically connected to the first a first transistor of the fourth transistor; a sixth transistor having a first end electrically connected to the second end of the fourth transistor, a control terminal for receiving the driving signal, and a second terminal for Receiving a second reference voltage; and an organic light emitting diode having a first end electrically connected to the second end of the fourth transistor, and a second end for receiving a second power voltage. The scan signal generating circuit of claim 9, wherein the first transistor and the third transistor are NMOS transistors, the second transistor, the fourth transistor, the fifth transistor, and the sixth The transistor is a PMOS transistor.