TWI410774B - A Fast Response Device and Method for Switching Power Converter - Google Patents
A Fast Response Device and Method for Switching Power Converter Download PDFInfo
- Publication number
- TWI410774B TWI410774B TW97118458A TW97118458A TWI410774B TW I410774 B TWI410774 B TW I410774B TW 97118458 A TW97118458 A TW 97118458A TW 97118458 A TW97118458 A TW 97118458A TW I410774 B TWI410774 B TW I410774B
- Authority
- TW
- Taiwan
- Prior art keywords
- fast response
- signal
- channels
- output voltage
- power converter
- Prior art date
Links
Landscapes
- Dc-Dc Converters (AREA)
Abstract
Description
本發明係有關一種切換式電源轉換器，特別是關於一種切換式電源轉換器的快速響應裝置及方法。The present invention relates to a switched power converter, and more particularly to a fast response apparatus and method for a switched power converter.
圖1顯示傳統的多相切換式電源轉換器10，其中誤差放大器14根據電源轉換器10的輸出電壓Vcore及參考電壓產生器12所提供的參考電壓Vref產生誤差信號Vcomp，鋸齒波產生器16提供鋸齒波Vramp1及Vramp2，脈寬調變(Pulse Width Modulation；PWM)比較器18根據誤差信號Vcomp及鋸齒波Vramp1產生信號Vpwm1以控制通道22，PWM比較器20根據誤差信號Vcomp及鋸齒波Vramp2產生信號Vpwm2以控制通道24。圖2顯示圖1中信號的波形圖，其中波形26為輸出電壓Vcore，波形28為鋸齒波Vramp1，波形30為鋸齒波Vramp2，波形32為誤差信號Vcomp，波形34為信號Vpwm1，波形36為信號Vpwm2。當鋸齒波Vramp2低於誤差信號Vcomp時，如時間t1，信號Vpwm2轉為高準位以打開(turn on)通道24，如波形36所示，通道24在被打開後將提供電荷至電容C2以使輸出電壓Vcore上升，如波形26所示，當鋸齒波Vramp2高於誤差信號Vcomp時，如時間t2，信號Vpwm2轉為低準位以關閉(turn off)通道24。當鋸齒波Vramp1低於誤差信號Vcomp時，如時間t3，信號Vpwm1轉為高準 位以打開通道22，如波形34所示，通道22在被打開後將提供電荷至電容C1以使輸出電壓Vcore上升，當鋸齒波Vramp1高於誤差信號Vcomp時，如時間t4，信號Vpwm1轉為低準位以關閉通道22。1 shows a conventional multi-phase switching power converter 10 in which an error amplifier 14 generates an error signal Vcomp according to an output voltage Vcore of the power converter 10 and a reference voltage Vref supplied from a reference voltage generator 12, which is provided by a sawtooth wave generator 16. The sawtooth wave Vramp1 and Vramp2, the pulse width modulation (PWM) comparator 18 generates a signal Vpwm1 according to the error signal Vcomp and the sawtooth wave Vramp1 to control the channel 22, and the PWM comparator 20 generates a signal according to the error signal Vcomp and the sawtooth wave Vramp2. Vpwm2 controls channel 24. 2 shows a waveform diagram of the signal of FIG. 1, wherein the waveform 26 is the output voltage Vcore, the waveform 28 is the sawtooth wave Vramp1, the waveform 30 is the sawtooth wave Vramp2, the waveform 32 is the error signal Vcomp, the waveform 34 is the signal Vpwm1, and the waveform 36 is the signal. Vpwm2. When the sawtooth wave Vramp2 is lower than the error signal Vcomp, as time t1, the signal Vpwm2 turns to a high level to turn on the channel 24, as shown by the waveform 36, the channel 24 will provide a charge to the capacitor C2 after being turned on. The output voltage Vcore is raised, as shown by waveform 26, when the sawtooth wave Vramp2 is higher than the error signal Vcomp, as time t2, the signal Vpwm2 is turned to a low level to turn off the channel 24. When the sawtooth wave Vramp1 is lower than the error signal Vcomp, if the time t3, the signal Vpwm1 turns to the high level Bits open channel 22, as shown by waveform 34, channel 22 will provide charge to capacitor C1 to cause output voltage Vcore to rise when turned on. When sawtooth wave Vramp1 is above error signal Vcomp, as time t4, signal Vpwm1 turns Low level to close channel 22.
然而，現今CPU的負載電流不論是由低變高或由高變低，其變化是相當快速，變化的時間在1us之內，這與電源轉換器10的切換週期相比是相當短的，如果負載暫態出現在信號Vpwm1或Vpwm2的脈衝時，如時間t1至t2或時間t3至t4，由於通道22或24打開，因此能緩和輸出電壓Vcore下降的速度，但是當負載暫態出現在信號Vpwm1及Vpwm2的脈衝之間時，如時間t2至t3，由於信號Vpwm1及Vpwm2均為低準位，因此輸出電壓Vcore將脫離控制，再者，就算負載暫態是出現在信號Vpwm1或Vpwm2的脈衝期間，如果負載變化太大，輸出電壓Vcore仍然劇降，故需要快速響應(quick response)迴路以在負載暫態出現時能同時打開通道22及24。However, the current load current of the CPU is changed from low to high or from high to low, and the change is quite fast, and the change time is within 1 us, which is quite short compared with the switching period of the power converter 10. When the load transient occurs in the pulse of the signal Vpwm1 or Vpwm2, as time t1 to t2 or time t3 to t4, since the channel 22 or 24 is turned on, the speed at which the output voltage Vcore falls can be alleviated, but when the load transient occurs in the signal Vpwm1 And between the pulses of Vpwm2, as time t2 to t3, since the signals Vpwm1 and Vpwm2 are both low, the output voltage Vcore will be out of control, and even if the load transient is present during the pulse of the signal Vpwm1 or Vpwm2 If the load changes too much, the output voltage Vcore still drops sharply, so a quick response loop is needed to open channels 22 and 24 simultaneously when load transients occur.
要有良好的輸出電壓Vcore，就要有良好的快速響應，而要達成良好的快速響應有兩個關鍵，一個是觸發快速響應的時機，另一個是快速響應的時間長短。如果太慢觸發快速響應，可能使輸出電壓Vcore低於規格書的規定，即出現低超(undershoot)的情況，相反的，如果太快觸發快速響應，可能導致輸出電壓Vcore出現尖波(spike)。如果快速響應的時間太短，輸出電壓Vcore仍然會出現低超的情況，但是如果快速響應的時間太長，輸出電壓Vcore 將上升過頭而出現回彈(ringback)情況。To have a good output voltage Vcore, there must be a good fast response, and there are two key points to achieve a good fast response, one is to trigger the timing of fast response, and the other is the length of time for quick response. If the fast response is triggered too slowly, the output voltage Vcore may be lower than the specifications of the specification, that is, an undershoot occurs. Conversely, if the fast response is triggered too quickly, the output voltage Vcore may be spiked. . If the response time is too short, the output voltage Vcore will still be low, but if the fast response time is too long, the output voltage Vcore It will rise too far and there will be a ringback situation.
圖3顯示一種習知用以實現快速響應的適應相位校準(Adaptive Phase Alignment；APA)電路40，其包括誤差放大器42根據電源轉換器的輸出電壓Vcore及參考電壓Vref之間的差值產生誤差信號Vcomp，低通濾波器44濾波誤差信號Vcomp產生信號V2，電流源48提供電流Iapa經電阻Rapa產生電壓Vapa偏移誤差信號Vcomp產生信號V1，比較器46根據信號V1及V2產生快速響應信號QR。圖4用以說明習知快速響應的操作，假設將圖3中APA電路40應用在N相切換式電源轉換器時，在正常的迴路控制下，該電源轉換器的多個通道將依序被信號Vpwm1、Vpwm2、Vpwm3…及信號VpwmN打開，如波形52、54、56及58所示，當發生負載暫態時，如時間t5，誤差信號Vcomp將下降，信號V2也將隨之下降，由於電容Capa的關係，信號V1不會立即下降，當信號V2低於信號V1時，快速響應信號QR轉為高準位以觸發快速響應，如波形50所示，在快速響應期間，該電源轉換器的所有通道都將被打開。3 shows an Adaptive Phase Alignment (APA) circuit 40 for implementing a fast response, which includes an error amplifier 42 that generates an error signal based on a difference between an output voltage Vcore of the power converter and a reference voltage Vref. Vcomp, the low pass filter 44 filters the error signal Vcomp to generate the signal V2, the current source 48 provides the current Iapa via the resistor Rapa to generate the voltage Vapa offset error signal Vcomp to generate the signal V1, and the comparator 46 generates the fast response signal QR based on the signals V1 and V2. 4 is used to illustrate the operation of the conventional fast response. It is assumed that when the APA circuit 40 of FIG. 3 is applied to the N-phase switching power converter, under normal loop control, multiple channels of the power converter will be sequentially The signals Vpwm1, Vpwm2, Vpwm3... and the signal VpwmN are turned on, as shown by waveforms 52, 54, 56 and 58. When a load transient occurs, as time t5, the error signal Vcomp will fall and the signal V2 will also drop, due to In the relationship of the capacitance Capa, the signal V1 does not fall immediately. When the signal V2 is lower than the signal V1, the fast response signal QR turns to a high level to trigger a fast response, as shown by the waveform 50, during the fast response, the power converter All channels will be opened.
在APA電路40中，由於快速響應的觸發是由信號V1決定，而信號 V1＝Vcomp－Iapa×Rapa 公式1 因此，可以藉由調整在晶片外部的電阻Rapa來改變觸發 快速響應的時間點，例如，使用較大的電阻Rapa來延遲快速響應的觸發電壓。然而，在APA電路40中，快速響應的持續時間是由低通濾波器44決定，而低通濾波器44係內建在晶片中，因此無法調整快速響應的時間。In the APA circuit 40, since the trigger of the fast response is determined by the signal V1, the signal V1=Vcomp-Iapa×Rapa Formula 1 Therefore, the trigger can be changed by adjusting the resistance Rapa outside the wafer. The point in time of fast response, for example, using a larger resistor Rapa to delay the fast response trigger voltage. However, in the APA circuit 40, the duration of the fast response is determined by the low pass filter 44, and the low pass filter 44 is built into the wafer, so the time for fast response cannot be adjusted.
在習知的快速響應方法中，係藉由打開全部的通道來避免輸出電壓Vcore出現低超的情況，但是在將全部的通道打開後將提供大量的電荷至輸出端Vcore，因此，當快速響應信號QR的寬度因非理想效應而稍微大於理論值時，將很容易出現回彈現象，如圖4的波形60所示，非理想效應包括延遲、寄生電阻及寄生電容等，當回彈的峰值超過一臨界值時，電源轉換器輸出端上的電路可能損毀，例如CPU，雖然增加在該電源轉換器輸出端上的電容可以抑制回彈現象，但是這將導致成本增加。In the conventional fast response method, the output voltage Vcore is prevented from appearing super low by turning on all the channels, but a large amount of charge is supplied to the output terminal Vcore after all the channels are turned on, so when responding quickly When the width of the signal QR is slightly larger than the theoretical value due to the non-ideal effect, the rebound phenomenon is likely to occur, as shown by the waveform 60 in Fig. 4, the non-ideal effects include delay, parasitic resistance and parasitic capacitance, etc., when the rebound peak Above a critical value, the circuit on the output of the power converter may be damaged, such as a CPU, although increasing the capacitance at the output of the power converter can suppress springback, but this will result in increased cost.
因此，一種能避免回彈現象的快速響應裝置及方法，乃為所冀。Therefore, a quick response device and method capable of avoiding rebound phenomenon is a problem.
本發明的目的，在於提出一種切換式電源轉換器的快速響應裝置及方法，其能避免回彈現象。It is an object of the present invention to provide a fast response apparatus and method for a switched power converter that avoids springback.
一切換式電源轉換器包含多個通道以提供一輸出電壓，根據本發明一種應用在該電源轉換器的快速響應裝置及方法包括一偵測電路，偵測該輸出電壓直接偵測該輸出電壓，當該輸出電壓低於一臨界值時觸發快速響應，以及一調節電路在該快速響應觸發時打開該多個通道中的至 少二個，該調節電路在該快速響應的期間，將隨著時間增加而減少所打開的通道的數量，因此，在該快速響應快結束時，送至該電源轉換器輸出端的電荷將變少，因而避免回彈現象。A switching power converter includes a plurality of channels to provide an output voltage. According to the present invention, a fast response device and method for the power converter includes a detecting circuit that detects the output voltage and directly detects the output voltage. A fast response is triggered when the output voltage is below a threshold, and an adjustment circuit opens the plurality of channels in the fast response trigger In less than two, the adjustment circuit will reduce the number of channels opened during the fast response period, so that the charge sent to the output of the power converter will be less at the end of the fast response. , thus avoiding rebound.
由於造成回彈現象是因為注入大多電荷至電源轉換器的輸出端，而快速響應的時間又因為非理想效應或偵測方法的固有缺點而難以控制，因此，本發明提出一種方法來模糊快速響應的結束時間。Since the rebound phenomenon is caused by injecting most of the charge to the output of the power converter, and the time of rapid response is difficult to control due to the inherent disadvantages of non-ideal effects or detection methods, the present invention proposes a method to blur the fast response. The end time.
圖5顯示本發明的實施例，在4相切換式電源轉換器70中，誤差放大器78根據電源轉換器70的輸出電壓Vcore及參考電壓產生器76所提供的參考電壓Vref產生誤差信號Vcomp，鋸齒波產生器80提供鋸齒波Vramp1、Vramp2、Vramp3及Vramp4，PWM比較器82根據誤差信號Vcomp及鋸齒波Vramp1產生信號Vpwm1以控制通道90，PWM比較器84根據誤差信號Vcomp及鋸齒波Vramp2產生信號Vpwm2以控制通道92，PWM比較器86根據誤差信號Vcomp及鋸齒波Vramp3產生信號Vpwm3以控制通道94，PWM比較器88根據誤差信號Vcomp及鋸齒波Vramp4產生信號Vpwm4以控制通道96，偵測電路72偵測輸出電壓Vcore，其包括電流源7202提供電流Iqr至電阻Rqr以產生電壓Vofs偏移輸出電壓Vcore產生電壓Vcf，比較器7204比較電壓Vcf及參考電壓Vref產生快速響應信號 Vqr，當電壓Vcf低於參考電壓Vref時，信號Vqr轉為高準位以觸發快速響應，由於偵測電路72是直接偵測輸出電壓Vcore，因此能精確的觸發快速響應，在觸發快速響應時，調節電路74送出信號VQR1、VQR2、VRQ3及VQR4以打開通道90、92、94及96中至少二個，在該快速響應的期間，調節電路74將隨時間增加而減少打開的通道的數量，進而減少注入輸出端Vcore的電荷。5 shows an embodiment of the present invention. In the 4-phase switching power converter 70, the error amplifier 78 generates an error signal Vcomp according to the output voltage Vcore of the power converter 70 and the reference voltage Vref supplied from the reference voltage generator 76. The wave generator 80 supplies sawtooth waves Vramp1, Vramp2, Vramp3, and Vramp4. The PWM comparator 82 generates a signal Vpwm1 according to the error signal Vcomp and the sawtooth wave Vramp1 to control the channel 90. The PWM comparator 84 generates a signal Vpwm2 according to the error signal Vcomp and the sawtooth wave Vramp2. In the control channel 92, the PWM comparator 86 generates a signal Vpwm3 according to the error signal Vcomp and the sawtooth wave Vramp3 to control the channel 94. The PWM comparator 88 generates a signal Vpwm4 according to the error signal Vcomp and the sawtooth wave Vramp4 to control the channel 96, and the detection circuit 72 detects The output voltage Vcore is measured, which includes a current source 7202 providing a current Iqr to a resistor Rqr to generate a voltage Vofs offset output voltage Vcore generating a voltage Vcf, and a comparator 7204 comparing the voltage Vcf and the reference voltage Vref to generate a fast response signal Vqr, when the voltage Vcf is lower than the reference voltage Vref, the signal Vqr turns to a high level to trigger a fast response. Since the detecting circuit 72 directly detects the output voltage Vcore, it can accurately trigger a fast response when triggering a fast response. The conditioning circuit 74 sends the signals VQR1, VQR2, VRQ3, and VQR4 to turn on at least two of the channels 90, 92, 94, and 96. During this fast response, the conditioning circuit 74 will increase over time to reduce the number of open channels. In turn, the charge injected to the output terminal Vcore is reduced.
圖6顯示調節電路74的第一實施例，其包括二控制電路7402及7404，在控制電路7402中，最小工作時間產生電路7406根據信號Vqr產生快速響應信號QR_all，驅動電路7408在信號QR_all的工作時間打開所有通道90、92、94及96，在控制電路7404中，最小工作時間產生電路7410根據信號Vqr產生快速響應信號QR_3rd，驅動電路7412在信號QR_3rd的工作時間打開通道90、92、94及96其中三個。圖7用以說明圖6中調節電路74的操作，在時間t1時，偵測電路72所輸出的信號Vqr轉為高準位，如波形108所示，最小工作時間產生電路7406及7410同時分別送出快速響應信號QR_all及QR_3rd，如波形110及112所示，其中，信號QR_all的工作時間Ton1小於信號QR_3rd的工作時間Ton2，因此，整個快速響應分為兩階段，在時間t1至t2期間，信號VQR1、VQR2、VRQ3及VQR4均為高準位，如波形100、102、104及106所示，故所有所有通道90、92、94及96都被打開，在時間t2至t3期間，只打開三個通道92、94及96，以減少注入輸 出端Vcore的電荷，進而抑制回彈現象。等效的快速響應結束點在時間t2及t3之間，由於快速響應結束點已經被模糊了，因此對快速響應結束點的精確需求也變得不是很重要。在此實施例中，驅動電路7412設定為同時打開三個通道，但在其他實施例中，也可以設定驅動電路7412只打開二個或一個通道。6 shows a first embodiment of the adjustment circuit 74, which includes two control circuits 7402 and 7404. In the control circuit 7402, the minimum operating time generation circuit 7406 generates a fast response signal QR_all based on the signal Vqr, and the drive circuit 7408 operates at the signal QR_all. All channels 90, 92, 94 and 96 are opened in time. In the control circuit 7404, the minimum working time generating circuit 7410 generates a fast response signal QR_3rd according to the signal Vqr, and the driving circuit 7412 opens the channels 90, 92, 94 during the working time of the signal QR_3rd and 96 of them three. 7 is used to illustrate the operation of the adjustment circuit 74 of FIG. 6. At time t1, the signal Vqr outputted by the detection circuit 72 is turned to a high level. As shown by the waveform 108, the minimum operation time generation circuits 7406 and 7410 are simultaneously The fast response signals QR_all and QR_3rd are sent, as shown by waveforms 110 and 112, wherein the working time Ton1 of the signal QR_all is smaller than the working time Ton2 of the signal QR_3rd, therefore, the entire fast response is divided into two phases, during the period t1 to t2, the signal VQR1, VQR2, VRQ3, and VQR4 are all high-level, as shown by waveforms 100, 102, 104, and 106, so all channels 90, 92, 94, and 96 are turned on, and only three are turned on during time t2 to t3. Channels 92, 94 and 96 to reduce injection and loss The charge of the Vcore at the end, which in turn suppresses the rebound phenomenon. The equivalent fast response end point is between time t2 and t3, and since the fast response end point has been blurred, the precise need for a fast response end point becomes less important. In this embodiment, the drive circuit 7412 is set to open three channels simultaneously, but in other embodiments, the drive circuit 7412 can also be set to open only two or one channel.
對於N相切換式電源轉換器而言，其最多可以將快速響應分為N階段，階段越多，結束點就越模糊，也越能抑制回彈現象。圖8顯示調節電路74的第二實施例，其除了同樣包括控制電路7402及7404之外，還包含控制電路7414，在控制電路7414中，最小工作時間產生電路7416根據信號Vqr產生快速響應信號QR_2nd，驅動電路7418在信號QR_2nd的工作時間打開通道90、92、94及96其中二個。圖9顯示圖8中信號的波形圖，其中波形114為快速響應信號Vqr，波形116為快速響應信號QR_all，波形118為快速響應信號QR_3rd，波形120為快速響應信號QR_2nd。在時間t1時，信號Vqr轉為高準位，最小工作時間產生電路7406、7410及7416分別提供信號QR_all、QR_3rd及QR_2nd，其中信號QR_3rd的工作時間Ton2大於QR_all的工作時間Ton1，信號QR_2nd的工作時間Ton3大於信號QR_3rd的工作時間Ton2，因此，在此實施例中，整個快速響應被分為三個階段，在時間t1至t2期間，所有所有通道90、92、94及96都被打開，在時間t2至t3期間，只打開通道90、92、94及96中的三個，在時間t3 至t4期間，只打開通道90、92、94及96中的二個。由前述實施例可知，當最小工作時間產生電路所提供的信號的工作時間越長，所打開的通道數量就越少。For the N-phase switching power converter, it can divide the fast response into N stages at most. The more stages, the more blurred the end point, and the more it can suppress the rebound phenomenon. 8 shows a second embodiment of the adjustment circuit 74, which includes a control circuit 7414 in addition to the control circuits 7402 and 7404. In the control circuit 7414, the minimum operating time generation circuit 7416 generates a fast response signal QR_2nd based on the signal Vqr. The drive circuit 7418 opens two of the channels 90, 92, 94 and 96 during the operating time of the signal QR_2nd. 9 shows a waveform diagram of the signal of FIG. 8, wherein the waveform 114 is a fast response signal Vqr, the waveform 116 is a fast response signal QR_all, the waveform 118 is a fast response signal QR_3rd, and the waveform 120 is a fast response signal QR_2nd. At time t1, the signal Vqr is turned to a high level, and the minimum working time generating circuits 7406, 7410, and 7416 provide signals QR_all, QR_3rd, and QR_2nd, respectively, wherein the working time Ton2 of the signal QR_3rd is greater than the working time Ton1 of the QR_all, and the operation of the signal QR_2nd The time Ton3 is greater than the working time Ton2 of the signal QR_3rd, therefore, in this embodiment, the entire fast response is divided into three phases, during which all all channels 90, 92, 94 and 96 are turned on, at time t1 to t2 During time t2 to t3, only three of channels 90, 92, 94 and 96 are opened, at time t3 During t4, only two of the channels 90, 92, 94 and 96 are opened. As can be seen from the foregoing embodiments, the longer the operating time of the signal provided by the minimum operating time generating circuit, the less the number of channels opened.
在驅動電路7408、7412及7418中各包括一預設圖樣以在信號信號QR_all、QR_3rd及QR_2nd轉為高準位時決定所要打開的通道。圖10顯示驅動電路7408中預設圖樣的實施例，在此預設圖樣中包括四個信號S1、S2、S3及S4分別對應通道90、92、94及96，如波形122、124、126及128所示，當信號QR_all轉為高準位時，如時間t1，驅動電路7408將此時的信號S1、S2、S3及S4送出以打開通道90、92、94及96，由於四個信號S1、S2、S3及S4在任何時間均為高準位，因此不論是何時觸發快速響應，驅動電路7408都將打開全部的通道90、92、94及96。圖11顯示驅動電路7412中預設圖樣的實施例，在此預設圖樣中包括四個信號S5、S6、S7及S8分別對應通道90、92、94及96，如波形130、132、134及136所示，由於在任何時間，四個信號S5、S6、S7及S8中都有三個維持在高準位，因此不論是何時觸發快速響應當信號QR_3rd，驅動電路7412都可以打開通道90、92、94及96其中三個，例如在時間t1時，信號S5、S7及S8為高準位，因此如果在此時觸發快速響應時，驅動電路7412將打開通道90、94及96。圖12顯示驅動電路7418中預設圖樣的實施例，在此預設圖樣中包括四個信號S9、S10、S11及S12分別對應通道90、92、94及96，如波形138、140、 142及144所示，由於在任何時間，四個信號S9、S10、S11及S12中都有二個維持在高準位，因此不論是何時觸發快速響應當信號QR_2nd，驅動電路7418都可以打開通道90、92、94及96其中二個，例如在時間t1時，信號S9及S12為高準位，因此如果在此時觸發快速響應時，驅動電路7418將打開通道90及96。Each of the drive circuits 7408, 7412, and 7418 includes a predetermined pattern to determine the channel to be opened when the signal signals QR_all, QR_3rd, and QR_2nd are turned to a high level. 10 shows an embodiment of a preset pattern in the driver circuit 7408, wherein the preset pattern includes four signals S1, S2, S3, and S4 corresponding to the channels 90, 92, 94, and 96, respectively, such as waveforms 122, 124, and 126. As shown at 128, when the signal QR_all is turned to the high level, as time t1, the drive circuit 7408 sends the signals S1, S2, S3 and S4 at this time to open the channels 90, 92, 94 and 96, due to the four signals S1. , S2, S3, and S4 are all high-level at any time, so whenever the fast response is triggered, the driver circuit 7408 will turn on all channels 90, 92, 94, and 96. 11 shows an embodiment of a preset pattern in the driving circuit 7412, wherein the preset pattern includes four signals S5, S6, S7 and S8 corresponding to the channels 90, 92, 94 and 96, respectively, such as waveforms 130, 132, 134 and As shown at 136, since at any time, three of the four signals S5, S6, S7, and S8 are maintained at a high level, the drive circuit 7412 can open the channels 90, 92 whenever the fast response is triggered as the signal QR_3rd. Three of 94, 96, for example, at time t1, signals S5, S7, and S8 are at a high level, so if a fast response is triggered at this time, drive circuit 7412 will open channels 90, 94, and 96. 12 shows an embodiment of a preset pattern in the driving circuit 7418. The preset pattern includes four signals S9, S10, S11 and S12 corresponding to the channels 90, 92, 94 and 96, respectively, such as waveforms 138, 140, As shown in 142 and 144, since at any time, two of the four signals S9, S10, S11, and S12 are maintained at a high level, the drive circuit 7418 can open the channel whenever the fast response signal QR_2nd is triggered. Two of 90, 92, 94 and 96, for example, at time t1, signals S9 and S12 are at a high level, so if a fast response is triggered at this time, drive circuit 7418 will open channels 90 and 96.
圖13顯示最小工作時間產生電路7406的實施例。圖14顯示圖13中信號的波形圖。當正反器146的輸入端C上的信號Vqr轉為高準位時，如波形154及時間t1所示，快速響應信號QR_all將轉為高準位，如波形162所示，同時正反器146的輸出端QB上的信號Vg將轉為低準位以關閉(turn off)開關148，如波形156所示，因此電流源150提供電流I1對電容C充電，故電容C上的電壓Vc開始上升，如波形158所示，在電壓Vc上升期間，由於正反器146所輸出的信號SL1維持在高準位，因此信號QR_all也維持在高準位，當電壓Vc達到目標值Vtrip時，如時間t2所示，反相器152將送出低準位的信號，因而使重置信號Sreset轉為高準位以重置正反器146，如波形160所示，因此信號QR_all轉為低準位，同時信號Vg也轉為高準位以打開(turn on)開關152以使電容C放電。最小工作時間產生電路7410及7416亦如圖13所示。FIG. 13 shows an embodiment of a minimum working time generating circuit 7406. Figure 14 shows a waveform diagram of the signal in Figure 13. When the signal Vqr at the input C of the flip-flop 146 is turned to a high level, as indicated by the waveform 154 and the time t1, the fast response signal QR_all will be turned to a high level, as shown by the waveform 162, while the flip-flop Signal Vg at output QB of 146 will transition to a low level to turn off switch 148, as shown by waveform 156, so current source 150 provides current I1 to charge capacitor C, so voltage Vc on capacitor C begins. Rising, as shown by waveform 158, during the rise of voltage Vc, since signal SL1 output by flip-flop 146 is maintained at a high level, signal QR_all is also maintained at a high level, when voltage Vc reaches a target value of Vtrip, such as As indicated by time t2, the inverter 152 will send a low level signal, thereby causing the reset signal Sreset to go to a high level to reset the flip flop 146, as shown by the waveform 160, so the signal QR_all is turned to a low level. At the same time, the signal Vg also turns to a high level to turn on the switch 152 to discharge the capacitor C. The minimum working time generating circuits 7410 and 7416 are also shown in FIG.
以上對於本發明之較佳實施例所作的敘述係為闡明之目的，而無意限定本發明精確地為所揭露的形式，基於以上的教導或從本發明的實施例學習而作修改或變化是可 能的，實施例係為解說本發明的原理以及讓熟習該項技術者以各種實施例利用本發明在實際應用上而選擇及敘述，本發明的技術思想企圖由以下的申請專利範圍及其均等來決定。The above description of the preferred embodiments of the present invention is intended to be illustrative, and is not intended to limit the scope of the invention. The embodiments are described and illustrated in the practical application by the skilled person in the various embodiments using the present invention. The technical idea of the present invention is intended to be equivalent to the scope of the following claims. To decide.
10‧‧‧電源轉換器10‧‧‧Power Converter
12‧‧‧參考電壓產生器12‧‧‧Reference voltage generator
14‧‧‧誤差放大器14‧‧‧Error amplifier
16‧‧‧鋸齒波產生器16‧‧‧Sawtooth generator
18‧‧‧PWM比較器18‧‧‧PWM comparator
20‧‧‧PWM比較器20‧‧‧PWM comparator
22‧‧‧通道22‧‧‧ channel
24‧‧‧通道24‧‧‧ channel
26‧‧‧輸出電壓Vcore的波形26‧‧‧ waveform of output voltage Vcore
28‧‧‧鋸齒波Vramp1的波形28‧‧‧Sawtooth waveform of Vramp1
30‧‧‧鋸齒波Vramp2的波形30‧‧‧Sawtooth waveform of Vramp2
32‧‧‧誤差信號Vcomp的波形32‧‧‧ Waveform of error signal Vcomp
34‧‧‧信號Vpwm1的波形34‧‧‧ Waveform of signal Vpwm1
36‧‧‧信號Vpwm1的波形36‧‧‧ Waveform of signal Vpwm1
40‧‧‧適應相位校準電路40‧‧‧Adapted to phase calibration circuit
42‧‧‧誤差放大器42‧‧‧Error amplifier
44‧‧‧低通濾波器44‧‧‧Low-pass filter
46‧‧‧比較器46‧‧‧ comparator
48‧‧‧電流源48‧‧‧current source
50‧‧‧快速響應信號QR的波形50‧‧‧ Waveform of fast response signal QR
52‧‧‧信號Vpwm1的波形52‧‧‧ Waveform of signal Vpwm1
54‧‧‧信號Vpwm2的波形54‧‧‧ Waveform of signal Vpwm2
56‧‧‧信號Vpwm3的波形56‧‧‧ Waveform of signal Vpwm3
58‧‧‧信號Vpwm4的波形58‧‧‧ Waveform of signal Vpwm4
60‧‧‧輸出電壓Vcore的波形60‧‧‧ waveform of output voltage Vcore
70‧‧‧電源轉換器70‧‧‧Power Converter
72‧‧‧偵測電路72‧‧‧Detection circuit
7202‧‧‧電流源7202‧‧‧ Current source
7204‧‧‧比較器7204‧‧‧ Comparator
74‧‧‧調節電路74‧‧‧Adjustment circuit
7402‧‧‧控制電路7402‧‧‧Control circuit
7404‧‧‧控制電路7404‧‧‧Control circuit
7406‧‧‧最小工作時間產生電路7406‧‧‧Minimum working time generation circuit
7408‧‧‧驅動電路7408‧‧‧Drive circuit
7410‧‧‧最小工作時間產生電路7410‧‧‧Minimum working time generation circuit
7412‧‧‧驅動電路7412‧‧‧ drive circuit
7414‧‧‧控制電路7414‧‧‧Control circuit
7416‧‧‧最小工作時間產生電路7416‧‧‧Minimum working time generation circuit
7418‧‧‧驅動電路7418‧‧‧ drive circuit
76‧‧‧參考電壓產生器76‧‧‧Reference voltage generator
78‧‧‧誤差放大器78‧‧‧Error amplifier
80‧‧‧鋸齒波產生器80‧‧‧Sawtooth generator
82‧‧‧PWM比較器82‧‧‧PWM comparator
84‧‧‧PWM比較器84‧‧‧PWM comparator
86‧‧‧PWM比較器86‧‧‧PWM comparator
88‧‧‧PWM比較器88‧‧‧PWM comparator
90‧‧‧通道90‧‧‧ channel
92‧‧‧通道92‧‧‧ channel
94‧‧‧通道94‧‧‧ channel
96‧‧‧通道96‧‧‧ channel
100‧‧‧信號VQR1的波形100‧‧‧ Waveform of signal VQR1
102‧‧‧信號VQR2的波形102‧‧‧ Waveform of signal VQR2
104‧‧‧信號VQR3的波形104‧‧‧ Waveform of signal VQR3
106‧‧‧信號VQR4的波形106‧‧‧ Waveform of signal VQR4
108‧‧‧快速響應信號Vqr的波形108‧‧‧ Waveform of fast response signal Vqr
110‧‧‧快速響應信號QR_all的波形110‧‧‧ Waveform of fast response signal QR_all
112‧‧‧快速響應信號QR_3rd的波形112‧‧‧ Waveform of fast response signal QR_3rd
114‧‧‧快速響應信號Vqr的波形114‧‧‧ Waveform of fast response signal Vqr
116‧‧‧快速響應信號QR_all的波形116‧‧‧ Waveform of fast response signal QR_all
118‧‧‧快速響應信號QR_3rd的波形118‧‧‧ Waveform of fast response signal QR_3rd
120‧‧‧快速響應信號QR_2nd的波形120‧‧‧ Waveform of fast response signal QR_2nd
122‧‧‧信號S1的波形122‧‧‧ Waveform of signal S1
124‧‧‧信號S2的波形124‧‧‧ Waveform of signal S2
126‧‧‧信號S3的波形126‧‧‧ Waveform of signal S3
128‧‧‧信號S4的波形128‧‧‧ Waveform of signal S4
130‧‧‧信號S5的波形130‧‧‧ Waveform of signal S5
132‧‧‧信號S6的波形132‧‧‧ Waveform of signal S6
134‧‧‧信號S7的波形134‧‧‧Signal S7 waveform
136‧‧‧信號S8的波形136‧‧‧Signal waveform of signal S8
138‧‧‧信號S9的波形138‧‧‧ Waveform of signal S9
140‧‧‧信號S10的波形140‧‧‧Signal of signal S10
142‧‧‧信號S11的波形142‧‧‧ Waveform of signal S11
144‧‧‧信號S12的波形144‧‧‧ Waveform of signal S12
146‧‧‧正反器146‧‧‧Factor
148‧‧‧開關148‧‧‧ switch
150‧‧‧電流源150‧‧‧current source
152‧‧‧反相器152‧‧‧Inverter
154‧‧‧快速響應信號Vqr的波形154‧‧‧ Waveform of fast response signal Vqr
156‧‧‧信號Vg的波形156‧‧‧Signal Vg waveform
158‧‧‧電壓Vc的波形158‧‧‧Vc waveform of voltage Vc
160‧‧‧重置信號Sreset的波形160‧‧‧Reset signal Sreset waveform
162‧‧‧快速響應信號QR_all的波形162‧‧‧ Waveform of fast response signal QR_all
圖1顯示傳統的多相切換式電源轉換器；圖2顯示圖1中信號的波形圖；圖3顯示一種習知用以實現快速響應的適應相位校準電路：圖4用以說明習知快速響應的操作：圖5顯示本發明的實施例；圖6顯示圖5中調節電路的第一實施例；圖7用以說明圖6中調節電路的操作；圖8顯示圖5中調節電路的第二實施例：圖9顯示圖8中信號的波形圖；圖10顯示圖8中驅動電路7408中預設圖樣的實施例；圖11顯示圖8中驅動電路7412中預設圖樣的實施例；圖12顯示圖8中驅動電路7418中預設圖樣的實施例；圖13顯示最小工作時間產生電路的實施例；以及圖14顯示圖13中信號的波形圖。Figure 1 shows a conventional multiphase switched power converter; Figure 2 shows a waveform of the signal of Figure 1; Figure 3 shows a conventional adaptive phase calibration circuit for achieving fast response: Figure 4 illustrates a conventional fast response Figure 5 shows an embodiment of the invention; Figure 6 shows the first embodiment of the adjustment circuit of Figure 5; Figure 7 shows the operation of the adjustment circuit of Figure 6; Figure 8 shows the second of the adjustment circuit of Figure 5. Embodiment FIG. 9 shows a waveform diagram of the signal in FIG. 8; FIG. 10 shows an embodiment of a preset pattern in the driving circuit 7408 of FIG. 8; FIG. 11 shows an embodiment of a preset pattern in the driving circuit 7412 of FIG. 8; An embodiment of a preset pattern in the drive circuit 7418 of FIG. 8 is shown; FIG. 13 shows an embodiment of the minimum operating time generating circuit; and FIG. 14 shows a waveform diagram of the signal of FIG.
70‧‧‧電源轉換器70‧‧‧Power Converter
72‧‧‧偵測電路72‧‧‧Detection circuit
7202‧‧‧電流源7202‧‧‧ Current source
7204‧‧‧比較器7204‧‧‧ Comparator
74‧‧‧調節電路74‧‧‧Adjustment circuit
76‧‧‧參考電壓產生器76‧‧‧Reference voltage generator
78‧‧‧誤差放大器78‧‧‧Error amplifier
80‧‧‧鋸齒波產生器80‧‧‧Sawtooth generator
82‧‧‧PWM比較器82‧‧‧PWM comparator
84‧‧‧PWM比較器84‧‧‧PWM comparator
86‧‧‧PWM比較器86‧‧‧PWM comparator
88‧‧‧PWM比較器88‧‧‧PWM comparator
90‧‧‧通道90‧‧‧ channel
92‧‧‧通道92‧‧‧ channel
94‧‧‧通道94‧‧‧ channel
96‧‧‧通道96‧‧‧ channel
Claims (13)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW97118458A TWI410774B (en) | 2008-05-20 | 2008-05-20 | A Fast Response Device and Method for Switching Power Converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW97118458A TWI410774B (en) | 2008-05-20 | 2008-05-20 | A Fast Response Device and Method for Switching Power Converter |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW200949484A TW200949484A (en) | 2009-12-01 |
| TWI410774B true TWI410774B (en) | 2013-10-01 |
Family
ID=44870969
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW97118458A TWI410774B (en) | 2008-05-20 | 2008-05-20 | A Fast Response Device and Method for Switching Power Converter |
Country Status (1)
| Country | Link |
|---|---|
| TW (1) | TWI410774B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5724237A (en) * | 1996-06-11 | 1998-03-03 | Unipower Corporation | Apparatus and method for sharing a load current among frequency-controlled D.C.-to-D.C. converters |
| US6137274A (en) * | 2000-02-02 | 2000-10-24 | National Semiconductor Corporation | Switching DC-to-DC converter and conversion method with current sharing between paralleled channels |
| US20060261860A1 (en) * | 2005-05-17 | 2006-11-23 | Fuji Electric Device Technology Co., Ltd. | DC to DC converter and voltage detecting circuit and current detecting circuit thereof |
| US20070236204A1 (en) * | 2004-04-14 | 2007-10-11 | Koji Tateno | Power supply device and switching power supply device |
| US20080018427A1 (en) * | 2006-07-19 | 2008-01-24 | Texas Instruments Incorporated | Apparatus for and method of reducing power consumption in a cable modem |
-
2008
- 2008-05-20 TW TW97118458A patent/TWI410774B/en active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5724237A (en) * | 1996-06-11 | 1998-03-03 | Unipower Corporation | Apparatus and method for sharing a load current among frequency-controlled D.C.-to-D.C. converters |
| US6137274A (en) * | 2000-02-02 | 2000-10-24 | National Semiconductor Corporation | Switching DC-to-DC converter and conversion method with current sharing between paralleled channels |
| US20070236204A1 (en) * | 2004-04-14 | 2007-10-11 | Koji Tateno | Power supply device and switching power supply device |
| US20060261860A1 (en) * | 2005-05-17 | 2006-11-23 | Fuji Electric Device Technology Co., Ltd. | DC to DC converter and voltage detecting circuit and current detecting circuit thereof |
| US20080018427A1 (en) * | 2006-07-19 | 2008-01-24 | Texas Instruments Incorporated | Apparatus for and method of reducing power consumption in a cable modem |
Also Published As
| Publication number | Publication date |
|---|---|
| TW200949484A (en) | 2009-12-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP6356140B2 (en) | Slope compensation module | |
| US8022680B2 (en) | Switching DC-DC converter with adaptive-minimum-on-time control and method of adaptively controlling minimum-on-time of a switching DC-DC converter | |
| US8519691B2 (en) | Current limiting for DC-DC converters | |
| US7498789B2 (en) | Switching regulator with over-current protection | |
| TWI470390B (en) | Improved feedback control of a dc/dc power converter | |
| TWI465011B (en) | Control circuit and method for a pwm voltage regulator | |
| JP4981799B2 (en) | Control of switching power supply using phase shift | |
| US7345464B2 (en) | PWM power supply controller having multiple PWM signal assertions and method therefor | |
| US20090001952A1 (en) | Apparatus and method for improving a transient response of a power converter | |
| US9973085B2 (en) | Output voltage control in overcurrent conditions for switching converters | |
| US20220149714A1 (en) | High Performance Synchronous Rectification in Discontinuous Current Mode Converters | |
| US20060139074A1 (en) | Charge pump DC / DC converter | |
| US9954440B2 (en) | Controller for DC/DC power converters | |
| JP2019086295A (en) | Reliability test device | |
| TWI384737B (en) | A Fast Response Device and Method for Switching Power Converter | |
| US10833665B2 (en) | Phase error correction for clock signals | |
| EP0903838B1 (en) | Switching current mode converter with reduced turn-on delay of power devices | |
| US7205751B2 (en) | Enable and disable of diode emulation in a DC/DC converter | |
| CN101599692B (en) | Quick response device and method of switching power converter | |
| CN101599693A (en) | The quick response device of switch type power converter and method | |
| KR20070081076A (en) | Systems and methods for reducing input current in photoflash chargers | |
| TWI410774B (en) | A Fast Response Device and Method for Switching Power Converter | |
| US11165346B2 (en) | Converter circuit, corresponding electronic component, device and method | |
| Qiu et al. | Dual-edge pulse width modulation scheme for fast transient response of multiple-phase voltage regulators | |
| WO2019021169A1 (en) | Measurement of instantaneous current flowing through a coil |